New SI Techniques for Large System Performance Tuning (Part 2) byDonaldTelian,SIGUYS,andMichaelSteinberger,BarryKatz,SISOFT

ThispaperwasoriginallypublishedintheproceedingsofDesignCon2016.Part1ofthispaperwaspublishedintheJuly2016issueofThePCBDesignMagazine.

3.5FFEvs.CTLEvs.DFEWhileFFE,CTLEandDFEarealleffectiveformsofequalization,theyhavedifferentcharacteristics,bothinthetimedomainandthefrequencydomain.Often,severaloftheseformsofequalizationarecombinedinasinglechannel;andsothecharacteristicsofeachformofequalizationmustbeconsideredwhensearchingforanoptimumsolution.Figure11presentstheexampleofasinglepulseresponseequalizedbyFFE,CTLE,andDFE,thusillustratingthedifferencesincharacteristicsinthetimedomain.Theunequalizedpulseresponsesareshowninredwhiletheequalizedpulseresponsesareshowninblue.NotethattheequalizedpulseresponsesfromFFEandCTLElookremarkablysimilar,althoughthepulseresponsefromCTLEhasloweramplitudethanthatofthepulseresponsefromFFE.Thisdifferencewillbeexplainedbelowinthecontextofthefrequencydomaindifferences.ThepulseresponseduetoDFEisquitedifferentfromthoseduetoFFEorCTLE.WhereastheFFEandCTLEpulseresponsesarerelativelysmooth,theDFEpulseresponsecontainsdiscontinuitiesspacedoneUIapart.ThesediscontinuitiesareduetotherisingandfallingedgesoftherecovereddatadrivingtheDFEtaps.NotealsothatDFEdoesnotaffecttheamplitudeofthemainpulse.OnewaytolookatthetimedomaindifferencebetweenFFEandDFEisthatwhereasasingleFFEtapaffectstheintersymbolinterferenceatmultiplebitpositions,asingleDFEtaponlyaffectsasinglebitposition.Thus,DFEisamoreflexibleformequalizationthatiswellsuited

forcleaningupanyintersymbolinterferenceleftoverfromtheFFE/CTLEcombinationprovidedithasasufficientnumberoftaps.AnotherwaytolookatthetimedomaindifferencebetweenFFE/CTLEandDFEisthatFFEandCTLEtendtoequalizeacrosstheentirebittimewhereas,becauseofthediscontinuities,DFEisonlytryingtoequalizeinthemiddleoftheeye.Thus,FFEandCTLEtendtobebettersuitedforremovingthebulkoftheintersymbolinterference.It’salsoimportanttorecognizethatinmostcases,onlyFFEcanperformequalizationattheprecursorbitposition.Thatis,mostCTLEandDFEdesignscannotequalizetheeffectsofabitthathasn’tbeenreceivedyet.Thus,whenworkingwithaDFEthathasalargenumberoftaps,theoptimalconfigurationwillusuallyusetheFFEforprecursorequalizationonlyandlettheDFEdothepostcursorequalization[7].(Inotherwords,settheFFEpostcursorequalizationtapstozero.)ThetradeoffbetweenFFEandCTLEisaddressedlaterinthissection.

Figure11:ComparisonofEqualizedPulseResponsesfromFFE,CTLEandDFE

FFE

CTLE

DFE

Unequalized Equalized

Figure12presentsthetransferfunctionsofanexamplechannelequalizedbyFFE,CTLE,andDFE.Theunequalizedtransferfunctionisshowninredandtheequalizedtransferfunctionsareshowninblue.

Figure12:ComparisonofEqualizedTransferFunctionsfromFFE,CTLEandDFEFortheCTLEthereisanadditionaltransferfunction(showningreen)whichwouldbeproducedbyaCTLEwithabetterdesign.TheCTLEtransferfunctionshowninblueistypicalofmanyCTLEdesigns-thegainatlowfrequenciesisreducedsoastocreateanincreaseingainathigherfrequencies.Thisisacomparativelysimplecircuittodesign,forexamplebyinsertingdegenerativefeedbackinthesourcecircuitofadifferentialamplifier.It’smoredifficulttodesignacircuitthathasunitygainatlowfrequenciesandthenproducesagainpeakathigherfrequencies.

FFE

CTLE

DFE

Unequalized Equalized Equalized ( better design )

Less gain than FFE (!)

More gain than FFE (good)

TheadditionalinformationisinthecomparisonbetweentheFFEandCTLEresponses.Atthefrequenciesthatmatterthemost(thelowerfrequencies),theshapesofthetransferfunctionsarenearlyidentical.Themostimportantdifferenceisintheoverallgain.Atafrequencyequaltoonehalfthesymbolrate,theFFEhasexactlyunitygain.Incomparison,thelowerperformanceCTLEdesignhasasmallamountoflossatthatfrequencyandthehigherperformanceCTLEdesignhasasignificantamountofgain.Thus,forequivalentequalization,thelowerperformanceCTLEproducesalowereyeheightthantheFFEwhilethehigherperformanceCTLEproducesagreatereyeheight.

Figure13:EyeDiagramsProducedbyFFE,TypicalCTLEandDFE

Forthesakeofcompleteness,Figure13isacomparisonoftheeyediagramsproducedbythethreedifferenttypesofequalization.

FFE

CTLE

DFE

ThenetresultisthatifbothFFEandCTLEarepresentinthechannelandhavesimilarequalizationcapabilities(usuallythecase),thechoicebetweenFFEandCTLEwilldependonthenetgainoftheCTLE.InthecaseofthelowerperformanceCTLE,onewoulddependprimarilyontheFFEand,ifanything,disabletheCTLE;whereasinthecaseofthehigherperformanceCTLE,onewoulddefinitelychoosetheCTLEandsettheFFEtounitygain. 3.6ManualOptimizationSummary1. Theprocedureisbasedonananalysisofthepulseresponse.2. Recovertheclockfromthepulseresponseusingthehulahoopalgorithm.3. IftheFFEhasaprecursortap,determinethattapvalueusingtheprocedureinSection3.3.4. IftheCTLEhassufficientgain,choosetheCTLEconfigurationwhichminimizesintersymbol

interference.Otherwise,iftheDFEhasenoughtaps,dependontheDFEforthebulkoftheequalization.Otherwise,usetheproceduresinSection3.3andSection3.4tochoosetheFFEtapweights.

4.Cost/PerformanceTuningwithManufacturingTechniquesManufacturingimprovementsthatenhanceperformanceand/orreducecostaredescribedinthissection.4.1RemovingDiscontinuitiesUsingDesignandProcessControlSeriallinkperformanceisdirectlyrelatedtotheexistence,placementandmagnitudeofimpedancediscontinuitiesinthesignalpath.Whilesomediscontinuitiesareunavoidable,bycoordinatingmultipledisciplinesovertimeitispossibletosignificantlyreducethemagnitudeandimpactofdiscontinuities.

Figure14:TDRof7DiscontinuitiesAcrossDesignIterations

Figure14showstheimpedanceofsimilarsignalpathsacrossthreedesigniterations,asmeasuredonthreedifferentPCBsusingTimeDomainReflectometry(TDR).Thephysical

requirementsofthisinterconnectrequiredsevendiscontinuitiesinlessthanfourinchesacrossuptosevendifferentPCBlayers,bothmicrostripandstripline.Theplotillustrateshowthemagnitudeofthediscontinuitieswerereducedovertimeinrelationtoourtargetimpedance(blackline);thefirstiteration(red)showingvariationsupto20%,theseconditeration(blue)becomingmoreconsistentyetstillvaryingupto15%,andthethirditeration(green)lookingconsistentwithvariationsnowwithintypicaltolerancesof8%andmostlyrelatedtotheexternalcomponentoverwhichwehavelesscontrol.Theseconditeration(blue)showsgoodprogressinthediscontinuitiesunderdesigncontrol,yethighlightsthechallengeofachievingconsistenttraceimpedancewhenusingnewPCBmaterials.Thethirditeration(green)showsexcellentprogressinreducingdiscontinuitiesbyusingbothdesignandprocesscontrolacrosssevensignalsspreadacrosssevenPCBlayers. WhileTDRplotsrevealthemagnitudeandlocationofthediscontinuitiesofconcern,Figure15illustratestheimpactofthesediscontinuitiesintermsofmorefamiliareyeopenings.Thefirstthroughthirddesigniterationsareshownfromlefttoright.Thetoprowshowsthevariationduetoonlythesetraces,revealingtheirassociatedISIandimpactonaneyeopeningduetothediscontinuities.Asthediscontinuitiesshownrepresentonlyonesectionofalargerchannel,thebottomrowadds12”ofPCBtracetoexaminetheirsystemlevelimpact.Bothrowsaresimulatedat11.5Gbpsandutilizethetrace’smeasuredS-parameters,fromwhichtheTDRsabovewerederived.

Figure15:EyeOpeningIterations,DiscontinuitiesOnly(top)oratSystemLevel(bottom)

Thesystem-levelplotsaboveillustratetheimportanceofsimulatingandmeasuringasufficientnumberofbitsand/orfailingbitpatterns,withoutwhichthethreeeyesmightlookthesame.Inotherwords,ISIcausedbydiscontinuitiesmaynotappeartoaffecteyeopeningsinallsituations.Onechallengeindevelopingseriallinksistheygivetheillusionofworkingwhentheyarenotworkingwell.Whenworkingtoreducediscontinuities,thefollowingitemsarehelpful:

1. Use2Dand3Dfieldsolversderivedimensionsthatproducedesiredimpedancesforphysicalstructuressuchasdifferentialtraces,vias,BGApadsandbreakouts,capacitorplanecutouts,etc.

2. WorkcloselywithPCBfabricationvendorstoachieveanddemonstratepredictableandconsistentimpedances–particularlywhenworkingwithnewmaterials,processes,andfabricationfacilities.

3. Measure,measure,measure.Alwaysmeasureactualhardwarewheneverpossible.Ifyoudonothavetheequipmentorcapabilitytoproducereliablemeasurements,findathirdpartythatcandoso.Thecostofperformingmeasurementsismuchlowerthanthecostofdebuggingproductsinthefield.

4. Simulateyourdesignbeforeandafterfabrication,comparingandimprovingtheresultsusingbothextractedandmeasuredstructures.Surpriseshappen.

5. LearnhowtoreadTDRinformationfrombothsimulationandmeasurement.Thishelpsyoupinpointthecause,location,andmagnitudeofeachdiscontinuityenablingyoutodeterminewhichdiscontinuitiesareofconcernandwhattodoaboutthem.

6. Developanintuitivesenseofwhichstructuresarecapacitiveandinductive,andhowthatrelatestoimpedance.Thisenablesyoutomakechangestophysicalstructuresinlayout,fieldsolvers,andsimulatorstoreducediscontinuities.Capacitivestructuresarefatandclosetoground,whileinductivestructuresareskinnyandfurtheraway.Z=sqrt(L/C).

7. Determinewhatleveloftoleranceissufficientforthetechnologyanddatarateathand.Thisenablesyoutodeterminewhenthemagnitudesofyourdiscontinuitiesare“goodenough”.

4.2ReducingDiscontinuitiesUsingDual-DiameterViasIntheauthors’DesignCon2014paper[4]wedemonstratedperformanceimprovementsupto400%byimprovingdiscontinuitiesinlessthan1%ofachannel’sinterconnect,ormorespecificallytwooftheviasinthechannel.Inpractice,onewaytoimproveavia’simpedanceistousea“dual-diameter”viastructurethatusestwodrillstoallowasmuchnarrowholeaspossible.Thissectionaugmentstheanalysisshownin[4]byprovidingmeasuredconfirmationoftheimprovementsofferedbyincreasingviaimpedance.

Measureddatacomparingnormalanddual-diameterversionsofelevenvia’sdifferentialimpedanceisplottedatleftinFigure16,organizedwithdeeperPCBlayersfromlefttoright.Atrightisasampleplotcomparingoneofthelayer23vias(red=normal,green=dual-diameter)overlaidwithalayer8referencevia.Notethatdual-diameterviaimpedanceondeeperlayersisdifficulttodeterminebecauseitisnot“flat”,asshowningreen.Thisisduetothevariousimpedancesseeninthedual-diameterstructuresuchasthelargediameter,smalldiameter,viastub,andpads.Assuchanaveragemustbeused,asshownbythemarkerat84.5Ohms.Thisirregularimpedanceisincontrasttonormalviasthatshowmoreconsistentimpedance,asshowninred.

Figure16:MeasuredImpedances,NormalandDual-DiameterVias

Dimensionally,signalsonupperlayersneverseethesmallerdiameterasthetransitionoccursnearthoselayers.Asexpected,upperlayersdonotseeanimpedanceincrease.Ingeneral,itisthesedeeperlayersthatareofconcernastheypresentamoresignificantdiscontinuity.Thesemeasurementsconfirmthatthedual-diameterstructurerealizesa~20Ohmimprovementindifferentialimpedanceondeeperlayers,asdesired.

Figure17:System-levelTDRContrastingNormalandDual-DiameterVias

Figure17showsaTDRmeasurementofthesameviasinanend-to-endchannelinwhichtwoofthenormalvias(red)arereplacedwithdual-diametervias(green),asseenat~2.6nSand4.2nS.Inthisplot,thefull20Ohmimprovementisnotevidentbecausetheprobeswereplacedfurtherawayfromthevias.Notethatidenticalstructuresareassembledtotheleftandrightofthealteredvias.Simulatingthesignalsusingtheend-to-endmeasurementsaschannelmodelsconfirmsconsistentupto30%improvementineyeheightandwidthwhencomparingthesamechannelwithnormalvias(red)ordual-diametervias(green),asshowninFigure18.Inaddition,thereisamuchmoreconsistentclusteringofperformance(comparegreenagainstredinplotatleftbelow)acrosschannelsvaryingintotallengthfrom10to20inches.

Figure18:EyeOpeningMetrics,ChannelswithNormalandDual-DiameterVias

4.3TraceCompensation,ImprovementsandChallengesItiscommonknowledgethatthedifferentialimpedanceofdifferentialtracesincreaseswhentheybecomeuncoupled,asoftenoccurswhenroutingintoaBGApinfieldasshownatleftinFigure19.Belowtheroutearefieldsolvedimpedances,predictingan8Ohmincreaseforthistrace’sconstruction.MeasuredimpedanceintheTDRatrightconfirmsan~8OhmincreaseontworevisionsofthisPCB,forthistraceandashortertrace.

Figure19:UncoupledvsCoupledImpedances

DiffImp Uncoupled 102 Ohms Coupled 94 Ohms Difference 8 Ohms

Furtherinvestigationrevealsthatthesepredictablediscontinuitiescause,onaverage,an8%impactoneyeopeningswhenthebreakouttracesexceed¼”inlength.Assuch,itbecomesdesirabletocompensatetheimpedancebysimplywideningthetraceintheuncoupledregionhighlightedinyellow.Whilethisadaptationissimpleenoughtocomprehendintheory,itcanbemoredifficulttoachieveinpractice.Thisisbecauseon“controlledimpedance”PCBsfabricationvendorstypicallyalterlinewidthsonagivenlayeraccordingtomappingtablestunedfortheirmaterialsandprocess.Assuch,ifonlytheimpedanceofthedifferentialtraceisspecified,it’spossiblethethetraceinthecoupledregionwillbefabricatedwiderthanthetraceintheuncoupledregion–makingtheproblemevenworse.Thewaytocorrectthisproblemistoalsospecifythedesiredimpedanceoftheuncoupledsingle-endedportionsofthetrace.4.4ReducingCostbyRemovingPCBLayersAshighervolumePCBsarerevisedtoreducecostandlayers,itisimperativetoconfirmperformanceparity.TheplotsbelowcomparetwoversionsofaPCBbeforeandafterlayercountreductionbyexaminingtheirsimulatedperformancewithinthelargersystemmodel.BothplotscomparetheoriginalPCB’sperformanceontheYaxiswiththereduced-layercountPCB’sperformanceontheXaxis,showingeyewidthsatleft(blue)andeyeheightsatright(red).Thereareover2,500dotsineachdiagram,witheachdotrepresentingthesamechannelineachsystemmodel.Assuch,dotsontheblacklinesrepresentchannelsthatperformthesameonbothPCBs.DotsabovethelinerepresentchannelsthatperformbetterontheoriginalPCB,whiledotsbelowthelinerepresentchannelsthatperformbetteronthereduced-layerPCB.

Figure20:EyeWidth(left)andHeight(right)ContrastedAcrossPCBRevisions

Theplotsabovedemonstratethateyewidths(aboveleft,inblue)generallyvaryonlyupto~2%andthegreatestvariationsareseenwithchannelswithlotsofmargin(i.e.,thevariation

fromtheblacklinegetswiderastheplotmovestotheright).Assuch,eyewidthvariationisnotrelevantandbelowtheanticipatedaccuracyleveloftheanalysis.Eyeheights(aboveright,inred)generallyvaryupto~5%andvariationiswiderinchannelswithlessmargin–howevertheworst-casechannelsperformthesame(ontheblacklineatthelowerleft).Theseplotsconfirmthatthereduced-layercountPCBperformsonparwiththeoriginal,withneitherversionsignificantlyout-performingtheother.Assuch,system-levelanalysisisusedtoconfirmadequateperformanceofthereduced-layerimplementationallowingustorealizecostsavingsassociatedwithlaminatingfewerPCBlayers.

SummaryandConclusionsThispaperhasdemonstratedanddescribednewtechniquesforoptimizingperformanceinhigh-speedseriallinksthroughthesystem-levelmanipulationofSerDesequalizationsettings.Themanualoptimizationapproachdescribedminimizesintersymbolinterference(ISI)byderivingTxtapweightsfromachannel’spulseresponse.Thistechniqueimprovesperformance,increasesthesystemdeveloper’sunderstandingofrelevanttradeoffs,andhasbeenautomatedandscaledtobeapplicabletothousandsofchannels.Forthesystemsshown,automatedoptimizationimprovessimulatedperformancein95%ofchannelsacrossa4xrangeoflengths.Theseimprovementsareachievedbymanagingamplitude/ISItradeoffsresultingfromTx/Rxequalizationtradingtoachieverequiredandoptimaleyeheightsandwidths.Performanceofworst-casechannelsrouted25%longerthananticipatedisshowntoimprovebymorethan60%.Thispaperalsodetailedmethodsfortuningperformanceusingmanufacturingprocessimprovements.MultiplediscontinuitiesspreadacrossvariousPCBlayersweredemonstratedtobecomenearlytransparentovertime.Dual-diameterviaconstructionandbreakouttracecompensationwerealsodetailedaswaystoreducetheimpactofdiscontinuities.SIanalysisalsoverifiedacceptableperformanceinreducedlayer-countPCBstoachievelowercost.

AcknowledgementsTheauthorswishtothankandacknowledgeSergioCamerloatEricssonasthevisionaryandmotivatorbehindthisseriesofpapers,andforhisrelentlesspursuitofengineeringexcellence.TheauthorsalsowishtothankWhelingCheng,KusumaMatta,RobertWu,andRaduTalkadatEricssonandWalterKatz,FrankdeAlbequerqueandToddWesterhoffatSiSoftfortheirsupport.AdditionalthankstoOrlandoBellatGigaTestLabsforconsistentlydeliveringhighqualitymeasureddata.Withouttheeffortsoftheseandothers,thisworkwouldnothavebeenpossible.

References [1] DonaldTelian,2004[2] AnthonySanders,EETimes2007

[3] Steinberger,Westerhoff,SNUGBoston2007

[4] “SimulationTechniquesfor6+GbpsSerialLinks”Telian,Camerlo,Kirk,DesignCon2010

[5] “WhenShorterIsn’tBetter”Steinberger,Wildes,Higgins,BrockandKatz,DesignCon2010

[6] Steinberger,Brock,Telian,DesignCon2013paper8-TA1

[7] “SimulatingLargeSystemswithThousandsofSerialLinks”Telian,Camerlo,Steinberger,

Katz,Katz,DesignCon2012

[8] “MovingHigherDataRateSerialLinksintoProduction–Issues&Solutions”Telian,Camerlo,Matta,Steinberger,Katz,Katz,DesignCon2014BestPaper

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