New path balancing algorithm for glitch power reduction

S.Kim, J.Kim and S.-Y.Hwang

Abstract: The authors propose an efficient path balancing algorithm to reduce glitch power dissipation in CMOS logic circuits. The proposed algorithm employs gate sizing and buffer insertion methods to achievc path balancing. The gate sizing technique reduces not only glitches, but also the effective capacitance in the circuit. For the paths which remain unbalanced after gate sizing due to the limitation of gate size, buffer insertion is performcd. Since the buffer itself consumes power, it is inserted between the gates where power reduction achieved by glitch reduction is larger than the power consumed by the inserted buffer. Detennining thc location of the inserted buffer is a difficult problem, because the power reduction achieved by an inserted buffer is closely related to thc locations of the other inserted buflers. The ILP (integer linear program) has been employed to determine the locations of inserted buffers. The proposcd algorithm has been tested on LGSynth9 1 benchmark circuits. Experimental results show that 61.5% of glitch reduction and 30.4%) of power reduction are achicvcd without increasing the critical path delay.

1 Introduction

Recently, low power has become one of the major design issues due to thc increased demand in personal computing devices and wireless communication systems. The total power consumed by CMOS digital circuits is composed of dynanic power caused by signal transition, and the power due to short-circuit current and leakage current [l]. Among these, dynaniic power dissipation is the domiiiant source of power dissipation. The spurious signal transition that does not contribute to the function of a circuit is the glitch. Since glitch power can occupy 20%70"/0 [2, 31 of total power dis- sipation, we can expect a large amount of power reduction by reducing glitches.

Efficient power optimisation methods using gate sizing havc been proposed in [411]. These techniques optiiizise Lhe amount of capacitive load by down-sizing transistors or gates under given delay constraints [7, 81. However, the sized gates or transistors might break path balancing and cause additional glitches. A sizing algorithm to reduce glitches has been presented in [Ill. This approach selects gates by calculating the amount of powcr reduction achieved by glitch reduction and resizes them. It is a novel method for glitch reduction, which utilises perturbations for escaping a bad local solution. In addition to gate sizing, buffer insertion is a wcll known method to optimise power and delay of circuits. In [4], buffer insertion is employed to increase the driving capability of a node that drives a large capacitive load, but these approaches did not consider thc

0 IEE, 2001 IEE Procediqy online no. 20010143 D!X 10.1WY/ipds:2001343 P a ~ r first received 14th Febiuay and in revised foim 15th December 2000 SKin and J. Kim are with the Department of Coniputer ScienaEngineering, Sogang Univcrsity, CPO Box 1142, Seoul 100-611, Koiea S.-Y. Hwang is with Uie Departinail of Electronic Lngdring, Sogang Uii- versity, CPO Box 1142, Seoul 100-611, Korea

IEE Prw-Circuifs Devices S y s r . . Vol. 148. No . 3, .lune 2OOl

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glitches caused by signals having different arrival times. The power reduction achieved by gate sizing or buffer insertion can be offset due to glitches introduced by apply- ing these algorithms.

We propose an algorithm that maximises path balancing and reduces load capacitance at thc same time. The algo- rithm embodies two processes-gate sizing and buffer inser- tion. As the first step, thc gate sizing algorithm is applied prior to buffcr insertion. Signal arrival time, required time and slack are computed for each gate as proposed in [8]. Then, the minimLtni input signal rcquired time and the size of a gate are determined such that glitches and load capac- itance can be reduced. Duiing the gate sizing process, those signal paths that cannot be balanced are identified and markcd. These are considered as candidate locations for bufler insertion. Buffers are insertcd for the paths which remain unbalanced after gatc sizing. Among the candidate locations identified during gate sizing, we select the loca- tions and insert the buffers such that power reduction achieved by reducing glitches can be larger than thc power consumed by added buffers. Finding the buffer locations for optimised power is an NP-complete problem. In the proposed system, we formulate the buffer insertion prob- lem into the ILP-based approach to find the solution.

2

2. I Gate-level power model The average dynamic power consumed by a CMOS gatc i is given by eqn. 1, where C; is the load capacitance, V,, is the supply voltage, ,f is the clock frequency, and U(L] is the transition density of gate i which denotes the average number of signal transitions containing glitches per clock cycle,

Gate-level power and glitch model

The transition density concept was introduced in [12] but this model does not consider signal correlation. The proba- bilistic approaches to estimate transition density with

151

glitches have been proposed in [13]. Although this approach takes the spatial and temporal correlation into consideration, the CPU times are significant and itcralive application is infeasible. For an optimiser performing esti- mation at each step of iteration, the most important ractor is the run time. A straightfoiward method to estimate tran- sition density is to simulate a circuit with arbitrary gener- ated input vectors. In this case, the problem is how may input vectors have to bc applied to achieve given accuracy level. Given a user-specified allowcd percentage error E and confidence level a, the approach described in [14] computes the number of input vectors to be used to simulate the cir- cuit. With a x 100% confidcnce, the number of input vec- tors L is represented in eqn. 2, where p and s are the measured average and standard deviation of the power, P is the true average power dissipation and crf '(d2) is the inverse error function obtained from the normal distribu- tion. For typical circuits and reasonable error and confi- dencc level, thc number of input vectors is small, which malres this approach very cfficient. Although this technique has the limitation that it only guarantees accuracy for the average switching activity over all gates. we have employed it becau'sc of its fast run tinie and accurate glitch estirna- tion:

2.2 Glitch model In a CMOS digital circuit, signal transition from logic level 0 to logic level I or vice versa is the main source of power dissipation. An example of the glitch is given in Fig. 1.

b

The glitch is a spurious transition and also consuincs power just as a functional transition does. It can be classi- fied into a generated glitch and a propagating glitch depending on its precedence [ I l l . A glitch is generated when non-glitch input signals arrive at different times (larger than the inertial dclay of a gate) and the input signals make transitions to introduce a glitch. A propagat- ing glitch is caused by an input signal, which contains glitches. It can be propagated through gates or suppressed by a side-input signal. The width of a glitch is tils0 a factor in deteimining whether a glitch is propagated or suppressed. Since we adopt the simulation-based power estimation method, thc numher of signal transitions, signal arrival times, cause events. and pulse widths are easily obtained.

A glitch makes an even number of signal transitions on a node. If the number of signal transitions at a node for a given input vcctor obtained by siniulation is NI,,,,, the number of transitions by glitches can be represented by eqn. 3,

I52

Assume that a gate G with inertial delay dLG) has m faiiins n l , n2, ..., n,, where arrival times are t,(nl), tlr(nZ), ..., to(n,,J, respectively. When Max(t,(nJ, fh), ..., t,,(n,,)> ~

Min(t,(n,), f,(nZ), ..., tLl(nrJ) > dj(G?, glitches can bc gener- ated at the output of gate G depending on input signals. A glitch whose pulse width i s larger than d,{G) can be propa- gated to thc output node of gate G.

Thc transition density due to glitches at gate i, D(z), can be computed using NI,,,, as shown in eyn. 4, where T repi-e- sents the clock period:

X r

(4)

This equation can be used for eqn. 1 to estimate the dynamic power.

3 Path balancing algorithm for glitch reduction

Gate sizing and buffer insertion algorithms are applied to achicve path balancing. In gate sizing, signal arrival times, required times and slacks are coniputed. Although gate downsi7ing can reduce load capacitance, it may produce new glitches. The. proposed algorithm reduces load capaci- tance and glitches at the same time. Buffer insertion reduces the glitches that are not suppressed during gate sizing.

3.1 Gate sizing algorithm To apply our gate siring algorithm the arrival times, required times and slacks are computed for all the gates. Fig. 2 shows an example circuit showing the computed slacks. The delay of a gate can be increased through down- sizing by the amount of its slack without violating timing constraints. This can reduce load capacitance, but it may produce new glitches.

To determine the size of a gate (hence the delay of a gate) to reduce load capacitances and glitches, we define the minimum input signal required tiinc or a gate as follows. Dgfinition I : The minimum input signal required time of a gate G(t,,,,, ,.<,&C)) is the minimum of the input signal arrival time$ and can be obtained by eqn. 5 ,

Fig. 3 shows an example of finding the gate delay that can maximise path balancing. Because the slack of the output node of gate Cia in Fig. 3 is 3, the delay of Ga can be increased to 5. In this case, for the path balancing, the inputs of Gb, Cc and Gd which are not from Ga are required to be downsized to make signals arrive at tinie 5. The required time of the side input of Gd is 4, and the path balancing at Gd cannot be achieved. To achicve balancing at Gd, Ca must be downsized to have delay 4. The incre- ment of a gate delay Cor the path balancing of gates is given by eqn. 6. Downsizing a gate to incrcasc the delay by the amount of the slack can rcducc the capacitance of the sized gate. But it may introduce new glitches and prevent other gates from being downsized. Downsizing a gate by the amount of Sizub/e-edeluy causes more gates to be down- sized. As the number of sbed gates increases, path balanc- ing can be achieved:

41317 21214 G d M

~~ t,=4

Fig. 3 m ~ ~ ~ i n ~ l f i ~ n ~ f ' f i i l f ~ , &/UJ

GateSizitig(j I

Lcvelise the circnit; Compute the arrival time, required time, slack for each gate; for each gale G, Compute for ( I = I : I < niax-Level: I++) 1

for edcb gate G, in Level I { Di = Sizable-Delay of G,; i f@, > 01 i

r,,<,(GJ;

Downsize gate Gi: Upct;ite timing information by downsizing gate Gi ;

I } /"for*/ Find candidate locations for buffer insertion;

1 /'for*/

1 Fig. 4 Grw Jiziig crlgoriihni io r&ce g l i k h

It is very important to determine the sequence of gates to be sized. As mentioned earlier, glitches can be classified into generated glitches and propagating glitchcs. A gcner- ated glitch can occur at any gate of a circuit, but a propa- gating glitch is the propagation of an already existing glitch. A propagating glitch never occurs when there are not any glitches in thc input signal of a gate. Therefore, it is prefcrrcd to select gates ncar the primary inputs first. After

IEE Pi.or.-CTirriiit.? Devires S~rsr., Vol I48, No. 3, June 2001

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levelising the gates using eqn. 7, sizing is performed starting from the gates with lower lcvels:

let!eI(G) = niax le.vel(h) + 1 ( 7 ) h € . fan in ( C )

The proposed gate sizing algorithm is given in Fig. 4. During gate sizing, we can find that somc paths are ncvcr be balanced just by gate sizing alone. In such a case, loca- tions for the burrer insertion are marked and delays which can achieve path balancing are dctermined.

The example circuit in Fig. 2 is changed after gatc sizing as shown in Fig. 5. For simplicity, we assume in the exam- ple that the delay of all gates is in the range from 1 to 5. By the proposed algorithm, the delay of gate GI is increased from 1 to 5, G4 and G5 from 1 to 4, G8 froni 2 to 5, GI 1 froni 1 lo 5 and G20 from 1 to 4. The critical path delay which amounts to 11 is not increased after gate sizing.

3.2 Buffer insertion method based on ILP To determine the optimal locations for buffer insertion, all combinations of candidate buffers must be taken into con- sideration. However, when there are n candidate buffers, 2" power estimations are needed, and thus categorising the problem is NP-complete. The difficulties in determining the buffer locations arise from the spatial correlation between burrers as shown in Fig. 6.

Suppose that the achievable power reduction is AP(h,) when inserting buffer b, at GI, and 4P(h3 when inserting buffer b2 at G2. If we insert both buffers, the given circuit is completely balanced and glitches do not exist any more. Let us further suppose that the achievable power reduction is 4P(blh2) when both b, and bz are inserted. Through extensive experimentation, wc found that AP(h,h,) > U@,), U(b,h,) > U(h , ) in most cases. To solve the spa- tial correlation, we formulate buffer insertion problem as eqn. 8,

maximise Power redu.ction through h,u f f e r irrsertion

siil)jec:t to Th,e num.ber of h u f f e r s i n CL path 5 1 (8) 153

-m 51015 (2) r-

7,017

Fig . 5 Esumplle circuit .Jiw gute sizing

To formulate the mathematical model, two binary dcci- sion variables .xH and ai, are defined, as shown in eqns. 9 and 1 0 zn

1 0

if candida,te buffer TI, is t,o be inserted if mndidate buffer n is riot to be inscrted

(9) = {

1 0

if candidate buffer bj is on path .i if candidat,e buffer bj is not on path i a . . "3 - - {

(10) The gain function G can be written as follows:

G = z 1 A P ( bl )+z 2 A P ( ba ) + ~ 3 A P (b3 )+. . .+:x., AP ( b, ) +slz2AP(blba) + 21:L.3AP(h1B:3) + . . .

ecause one location is pcr path, a buffer is likcly to be inserted at the location close to the primary input. It makes the spatial correlation between candidate buffers trivial. Then the ILP formula- tion can be rewritten as eqn. 11:

rnaxirriise xlAP(b1) + zqAP(b2) + z3AP(b3) + +Z,AP(b,) (11)

subject to a1151 + al2TZ + 0133:3 + . . . a l n , Z , 5 1

u'L151 + a,'L2J'2 + u 2 y 5 : j + , . I cL.L,zn 5 1 ~ ~ 3 1 ~ 1 + ~ ~ 3 2 x 2 + 0 , 3 3 2 3 + . . . ( ~ 3 ~ 5 , 5 1

. . .

am1n.1 + am222 + flna3.T3 + , . . flmnx,, I 1 The power reduction achieved by inserling buffer b,,

AP(b,), is computed prior to the evaluation of the gain function. After finding the solution of eqn. 1 I , the buffer b, is inserted into the path if x, is equal to I . For the candi- date buffers which are not inserted, the ILP algorithm is repeated. The probpm is stopped when the gain function

I54

becomes positive. Fig. 7 shows the results of buller inser- tion for the circuit in Fig. 2. In this example, we assume that AP(b,) = 10, AP(b2) = 10, AP(D1) = 7, M(b4) = 7, AP(b5) = -9, AP(b6) = -1, AP(h7) = 5, AP(h,) = -9. AP(blo) = -9.

Fig. 6 Spatial "&ion henvem buffem

4 Experimental results

The algorithm described in this paper has bcen imple- mented in C on an Ultra Sparc workstation. For the accu- rate estimation of transition density by glitches, event- driven simulation has been employed. The number of input vectors to be applied to the benchmark circuits is deter- mined by the equation in [I41 with 10% error and 90% con- fidence level. The process of applying generated input vectors and monitoring the resulting power value is contin- ued until the average power obtained is within the specified confidence level. The number of signal transitions obtained by event-driven simulation was used to compute functional and glitch transitions, and the number of glitch transitions was computed separately using eqn. 2. Experiments have been performed on several combinational circuits from the LGSynth9 I benclmark suite. These circuits are initially mapped by the SIS [I51 using the command script 'map -n 1.0 AFG', which targets area minimisation. The library we used contains AND, OR, NAND, NOR, BUFFER and INVERTER gates. Each type of gate has five different implementations, each of which has a different area-delay ratio. For simplicity, we assumed that the gate capacitance and gate area are proportional to each other. The inertial delay model was used in our experiment.

As a result, the gate count, the percentage of power reduction obtained by gate sizing, and that obtained by

IEE Pi-oc,-CirmitT DmI'ces S y . ~ f . , Voi 148, No. 3, June 2001

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Fig . 7 Buffers lq, b ~ , b?, bd are inserted

fisult of hu& insertum

buffer insertion together with gate sizing are illustrated in Table I . The gate sizing alone achieved an average of 25.7% power reduction. An average of 30.4% power reduc- tion was achieved by buffer insertion with gate sizing. The insertion of buffers takes unwanted power dissipation. However, greater overall power savings can be obtained by compensating the power losses due to inserted buffers.

Table 1: Results of power reduction '

Gate sizing + buffer insertion

Gate sizing

Benchmark No. of circuits Gates NO. of Power No. of Power

sized reduction, inserted reduction, gates % buffers %

z4ml 20 12 33.3 4 34.7

decod 22

x2 42

vda 585

sct 91

unreg 97

la1 114

i7 47 1

i6 340

c43 27

C432 160

c499 202

C880 383

C1355 546

C 1908 880

C2670 1193

C3540 1669

10 15.0 1 18.5

15 28.2 1 28.6

417 32.8 22 33.1

29 15.5 8 16.0

77 40.5 0 40.5

66 30.6 3 30.8

346 38.6 2 38.8

209 27.6 0 27.6

11 8.5 7 21.3

88 29.4 21 32.1

168 13.0 35 32.3

212 27.2 7 27.5

80 3.8 97 28.6

556 27.2 98 33.0

959 38.5 290 41.2

1126 28.4 202 32.8 - - - Avg . 25.7 30.4

Table 2 reports results of glitch reduction. The first column of the table represents the percentage of glitches in the total switching activities of benchmark circuits. The percentage of glitches after gate sizing is given in the third

IEE Proc.-Circuils Devices SJW, Vol. 148, No. 3. June 2001

column. The C1908 circuit is composed of 880 gates, and 35.3% of the signal transitions are glitches. Before sizing, 482 gates were balanced. After sizing, 542 gates were balanced and 18.1'% of the capacitance was reduced, with a glitch reduction of 25.8%. The power reduction by gate sizing was 27.2% and the glitch ratio or the sized circuit was 29.5'1/0. During the sizing process, among 356 candidale buffers 98 buffers were selected by the proposed-ILP based buffer insertion method. As a result, 33.0% of power reduo tion was achieved by reducing 55.8% of the glitches. The circuits with low glitch ratio, such as la1 or i6, have few candidate buffers, and buffer insertion was rarely required.

Table 2: Result of glitch reductions

Gate sizing + buffer insertion

Gate sizing

Benchmark Glitches, Glitch Glitch

% % %

Yo Glitches, circuits ~~ reduction, Glitches' reduction,

z4ml 31.2 30.5 3.1 25.4 20.2

decod 13.5 4.0 73.3 0.1 96.7

x2 12.0 0.4 64.9 0.3 67.6 vda 16.4 11.3 30.9 9.9 38.2

sct 9.5 7.5 22.8 6.7 22.9

unreg 8.0 2.4 71.4 2.4 71.4

la1 6.6 5.2 23.1 4.3 32.5

i7 10.0 3.8 66.7 3.5 61.3

6.3 2.3 65.4 2.3 65.4 i6

c43 22.8 21.9 5.1 0.8 96.6

C432 31.1 19.2 47.5 14.0 59.5

c499 20.3 19.6 6.8 3.1 85.7

C880 33.7 32.5 5.5 29.4 11.8

C1355 28.7 21.6 2.9 5.8 86.7

C1908 35.3 29.5 25.8 16.0 55.8

40.3 38.7 10.8 3.2 85.3 C2670

C3540 37.6 35.7 17.6 8.4 82.4

Avg. 21.3 17.1 31.9 7.9 61.5

By gate sizing, an average of 31.9% of glitch reduction was achieved, as shown in the fourth column of the table. After buffer insertion, ghtches were reduced to 7.9%. As a result. an average of an additional 29.6% was obtained. This shows that buffer insertion combined with gate sizing are cffective for glitch reduction.

We performed Spice simulation for the circuits in Figs. 2, 5 and 7 to demonstrate the efficiency of the proposed algorithm. Since our implementation is at gate- level, we selected switch-level modules having the same delay as those of the gate-level library modules. Table 3 shows the result of power consumption for the circuits in Figs. 2, 5 and 7 (tagged as circuit A, circuit B and circuit C). When input vector (nl = I , n2 = 0, n3 = 1, n4 = 0, n5 = 1) is applied, the resultant waveforms at nodes n6 and n7 in thc circuits of Figs. 5 and 7 are shown in Figs. 8 and 9, respectively. Prior to buffer insertion, glitches can be observcd at nodcs 6 and 7. Those glitches are removed after buffer insertion as shown in Fig. 9.

0.6

0.2 !J -

0.21

- 0 . 2 : , I - , I I I I I

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

3.4

3 , O ~ 2.6

2.2

1.4

Table 3: Results of power estimation by Spice simulation

Circuit A Circuit B Circuit C

Power consumption, mW 9.98 6.44 4.97 Power reduction, % - 35.5 50.2

5 Conclusions

In this paper, a gate sizing and buffer insertion algorithm to reduce glitch power dissipation in CMOS circuits has been presented. The proposed gate sizing algorithm reduces load capacitance and glitches simultaneously considering path balancing. A buffer insertion algorithm based on ILP reduces glitches that cannot be removed by gate sizing only. With our algorithni, 61.5% of glitch reduction and 30.4% of total power reduction are achieved without violat- ing timing constraints.

Short-circuit power consumed by inserted small buffers is neglected because the proposed algorithm does not con- sider the power dissipation due to short-circuit current. If the estiinalion of short-circuit power is performed at the gate level; more accurate results can be obtained. Furthcr- more, if the gate sizing and buffer inscrtion aIgorithn can be interIemed into a single optimisation process, better results can be possible.

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156 IEE Pruc.-Circvit.s Device5 Syst., Vol. 148, N o 3, June 2001