new design of a map decoder
TRANSCRIPT
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
New Design of a MAP Decoder
Leila Sabeti
Advisor: Dr. M. AhmadiCo-Advisor: Dr. K. Tepe
April 2004University Of Windsor
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Outline• Objective• Digital Communication System• Turbo Encoder• Turbo Decoder• Algorithms History• Comparison• BCJR/MAP Algorithm• Max-Log-MAP Algorithm• Comparison between previous implementations• Proposed System Design• Proposed quantization• Metric normalization• RTL simulation• Synthesis• Future works
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Objective
•MAP/BCJR Decoder -can be used in communication systems (wireless, satellite, magnetic recording, digital video,…) -Minimizes the bit error rate of received channel information-regenerates the original information•Max-Log-MAP algorithm for implementation.
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Digital communication System
Information SourceInformation Source Source EncoderSource Encoder Digital ModulatorDigital Modulator
ChannelChannel
TransmitterTransmitter
ReceiverReceiverDigital DemodulatorDigital DemodulatorSource DecoderSource DecoderOutput informationOutput information
Channel EncoderChannel Encoder
Channel DecoderChannel Decoder
BPSK
AWGN
1/2
RSC
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
5
00
10 01
11
0/00
1/10
1/111/11
0/00
1/10
0/010/01
RSC Encoder (Two Memory,Rate ½,Generators (7,5))
State Diagram
Turbo Encoder• Recursive Systematic Convolutional Codes (RSCC), two memory, code
rate 1/2.• Parallel or Serial concatenation of (RSCC) and a pseudo random interleaver
and/or more memories.• The encoding process represented by a state transition diagram.
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
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Turbo Encoder
Zero Transition One Transition
•Expanding the state transition diagram
state K
00
10
01
11
00 00 00 00 00 0011 11 11 11
11
10
01
1001
00
10
11 1111
01
01 01
00
01
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Trellis diagram for (7,5) convolutional code
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Turbo Decoder (SISO)
• Important development in coding theory in recent years.• Standard(Consultative Committee for Space Data
Systems(CCSDS), and 3rd Generation Partnership Project (3GPP) )
• Strong requirement for the efficient implementation
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Turbo Decoder• MAP/BCJR Decoders, interleavers and deinterleavers• BCJR algorithm for received channel sequences • Passing information to the next decoder at each iteration• Reduction of Bit Error Rate (BER).
A Posteriori Probability
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Algorithms History
• 1948 : Shannon[6]
• 1967 : Viterbi Algorithm (VA)[6]
• 1972 : MAP/BCJR Algorithm[1]
• 1989 : Optimum Update (SOVA-SU)[7]
• 1990 : Max-Log-MAP[2]
• 1995 : Log-MAP[2]
• 1996 : SOVA[7]
• 2001 : Improved Max-Log-MAP [4][5]
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1.E-07
Uuencoded
MAP
ML-MAP
SOVA1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E-05
0 21 3Es/No (Signal to noise ratio)
BE
R (B
it E
rror
Rat
e)Performance of different Turbo decoders
•MAP and Log-MAP have the best accuracy.•SOVA is the worst.•ML-MAP is in between but it will be improved by iterative decoding and using scaling factor for APP.L-MAP
1.E-06
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
0 21 30 21 3
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Complexity Comparison
MAP/BCJR Max-Log-MAP Log-MAP Sliding MAP SOVA
)( 2nOM
)( 2nOs
)6( 2nOM
)6( 2nOs
)( 2nOc2
)( 2nOc
)2( 2nOs
)5.0( 2nOc
)5.0( 2nOs)(nOs
• n: Number of states, M: Multiplications, S: Summations, • C: Comparisons• The differences of considered architecture in terms of power
consumption is not significant.• Improved ML-Map by using a scaling factor within the extrinsic
calculation.
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BCJR/MAP Algorithm
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
b)
k 1k +1k -0 1k n+ - k n+ N
State Trellis Length
Forward Backward recursion
α β
βα
Soft Information
Inputs
Output
• The output of this algorithm (soft output) gives the probability of each received bit of information to be one or zero
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
γ
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
BCJR/MAP Algorithm
∑ −='
1 ),'().'()(m
ttt mmmm γαα
)|(.)|().,'|().'|(),'( ttx
tttttt XYRXYRmmXqmmpmmpd∑=γ
∑∑
−=++
=++
+ =Λ
1),,'(11
1),,'(11
1 )'().().,'(
)'().().,'(ln)(
Xmmttt
Xmmttt
t mmmm
mmmmX
αβγ
αβγ
∑ ++=m
ttt mmmm ),'().()'( 11 γββ
• Too difficult in practice, because of the numerical representation of probabilities,nonlinear functions and mixed multiplications and additions of these values.
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Max-Log-Map Algorithm• work with the logarithms of the values using the following
approximation:
• Multipliers which make the design complex, huge and slow are changed to adders and comparators.
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
ininee γγγ
}...1{max)...ln( 1
∈≈++
KAPN
XY
N
XYmm t
ttttt
pd +++= ln22
),'(ln00
γ
)],'()'([max)(ln 1'mmmm ttmt γαα += −
)],'()'([max)'(ln 11 mmmm ttmt ++ += γββ
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Max-Log-MAP Algorithm
• Using Alpha, Beta and Gamma, Log-Likelihood Ratio (LLR) is computed which provides soft decision.
• Soft Output makes it possible to decide if each received Bit ofinformation is zero or one.
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Log-Likelihood Ratio (LLR)
)],'(ln)(ln),'([lnmax
)],'(ln)(ln),'([lnmaxln
111),',(
111),',(1
mmmmm
mmmmm
tttXmm
tttXmmt
αβγ
αβγ
++−
++=Λ
++−=
++=+
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Previous implementations
Algorithm Speed Area Accuracy
[4] ML-MAP High Medium High
[12] Log-MAP High High High
[8] SL-MAP Low Low High
Prp ML-MAP High
•Speed range about 20MHz~100MHz, needed for iterations
•Minimum area about 7mm2
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
•Disadv. of [8]: Complex Control unit for synchronization of decoding steps•Decreasing the memory size and increasing the accuracy in ML-MAP the lowest-complexity algorithm.•Using the parallel calculation and LUTs, High speed
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Proposed System Specification
• Encoder: Recursive Systematic Convolutional (RSC)• Channel: Additive White Gaussian Noise (AWGN)• Considered Modulation: Binary Phase Shift Keying
(BPSK), which maps 1 to 1 and 0 to –1.• Number Of Memories: 2.• Code Rate: R=1/2 • Block size: Flexible to the block size
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
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Proposed System Design
γCal.γ
Cal.
αCal.α
Cal.
βCal.β
Cal.
SoftOutput
Cal.
SoftOutput
Cal.RAMRAM
RAMRAM
YsYp
APP Soft Output
1. Gamma and Alpha are calculated together and stored in RAM .2. Beta and Landau are also calculated in parallel to give the soft output3. Faster, less memory and reduced area
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
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Proposed Gamma Unit• Logarithm of Gamma
• No sensitivity of Max-Log-MAP algorithm to the variance of the noise • Eight nonzero Gammas but four different values.
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
KAPN
XY
N
XYmm t
ttttt
pd +++= ln22
),'(ln00
γ
)1(ln)(),'(ln
)1(ln)(),'(ln
)1(ln)(),'(ln
)1(ln)(),'(ln
11,
10,
01,
00,
++++=
++−+=
−++−=
−+−−=
tttt
tttt
tttt
tttt
APYYmm
APYYmm
APYYmm
APYYmm
pd
pd
pd
pd
γ
γ
γ
γ
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Proposed Gamma Unit
+
+
+
+
LUTAPP
(Adders)
ln{P(1)}
ln{P(-1)}
Ys
Yp
γ00
γ01
γ10
γ11
--
--
Yd (systematic data) and Ys (Parity data) are added/subtracted.
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
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Alpha Calculation Unit
State 0State 0
γt (00, 01, 10,11)
Alpha 1
Alpha 0
Alpha 3
Alpha 2
Alpha 0
Alpha 1
Alpha 2
Alpha 3
State 1State 1
State 2State 2
State 3State 3
Alpha recursion
To Memory
Alpha 0
Alpha 1
Alpha 2
Alpha 3
•In each Block Alpha is calculated using proper Gamma and previous calculated Alphas.
•Beta Calculation Unit
•Soft outputs
Alpha: t+1Alpha: t
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Proposed quantization
• Quantization of input,Gamma, Alpha,Beta,Output and… • Decreasing the number of bits->Lower accuracy • Increasing->Larger memories for storage• Crucial choosing• Minimum quantization that still gives a reliable BER based
on simulation results[4] .
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
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Proposed quantization• Decoder inputs [-4, 4], 90% covering.• Integer value with one digit precision.
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
1 2 3 4 5 6•APP values between –8 and +8.
Integer mantissa
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Proposed quantization• lnAP(1) and lnAP(-1) are quantized to integer values from –8 to 0.• Also 8bits for γ, α, β and 8bits for output is considered.
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Metric Normalization
• In forward or backward recursions, metric values can easily overflow or underflow.
• subtraction of the maximum or minimum node metrics at a specific time from all of the node metrics at that time
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
RTL Simulation• Verilog•Simvision
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
•Synopsys (Design analyzer)•Modules
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
•Synopsys•I/O wrapper
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Synthesis
•Synopsys•Area: 0.96 mm2
• Speed: 150 MHz•Fastest Implementation: 110MHz
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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
Partitioning and Floorplanning•Encounter
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System DesignSystem Design
RTL SimulationRTL Simulation
SynthesisSynthesis
Scan InsertionScan Insertion
Gate-Level SimulationGate-Level Simulation FloorplanningFloorplanning
PlacementPlacement
Clock Tree GenerationClock Tree Generation
Routing & Timing Verification
Routing & Timing Verification
Physical VerificationPhysical Verification
Future Works
Verilog
Design analyzer
Design analyzer
Verilog
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS
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Thank youThank you