netfpga tutorial - india: may 2008 1 s t a n f o r d u n i v e r s i t y hands-on with the netfpga...
TRANSCRIPT
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NetFPGA tutorial - India: May 2008 1 S T A N F O R D U N I V E R S I T Y
Hands-on with the NetFPGA to build a Gigabit-rate Router at Indian Institute of Science (IISc)
Kuruvilla Varghese(IISc)
Presented by:
Thursday-Friday, May 15-16, 2008 : 9am-5pmhttp://netfpga.org/tutorials/India2008/
Co-sponsored by:
Xilinx University Program (XUP)
John W. Lockwood & Jad Naous(Stanford University)
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NetFPGA tutorial - India: May 2008 2 S T A N F O R D U N I V E R S I T Y
FPGAFPGA
MemoryMemory
1GE1GE
1GE1GE
1GE1GE
1GE1GE
What is the NetFPGA?
PCI
CPUCPU MemoryMemory
NetFPGA Board
PC with NetFPGA
NetworkingSoftwarerunning on a standard PC
A hardware acceleratorbuilt with Field Programmable Gate Arraydriving Gigabit network links
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NetFPGA tutorial - India: May 2008 3 S T A N F O R D U N I V E R S I T Y
NetFPGA Worldwide Tutorial Series
Jiaotong Univ.Beijing, China
NICTA/UNSW:Sydney,Australia
Eurosys:Glasgow,Scotland
CESNETBrno,
Czech Republic
SIGCOMM:Seattle,
Washington
Hot Interconnects& Summer Camp
Stanford, California SIGMETRICS
San Diego,California IISc
Bangalore,India
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NetFPGA tutorial - India: May 2008 4 S T A N F O R D U N I V E R S I T Y
Tutorial Schedule • Thursday, May 15, 2008
– 9am: Welcome • Morning Session 1• Break• Morning Session 2
– Noon: Lunch• Afternoon Session 3• Break• Afternoon Session 4
• Friday, May 16, 2008– Individual exercises
• Hands-on with the NetFPGA Machines
– Questions and Answers
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NetFPGA tutorial - India: May 2008 5 S T A N F O R D U N I V E R S I T Y
Who, How, Why
Who uses the NetFPGA?– Teachers– Students– Researchers
How do they use the NetFPGA?– To run the Router Kit– To build modular reference designs
• IPv4 router• 4-port NIC• Ethernet switch, …
Why do they uses the NetFPGA?– To measurement performance of Internet systems– To prototype new networking systems
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NetFPGA tutorial - India: May 2008 6 S T A N F O R D U N I V E R S I T Y
FPGAFPGA
MemoryMemory
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Running the Router Kit
User-space development, 4x1GE line-rate forwarding
PCI
CPUCPU MemoryMemory
OSPFOSPF BGPBGP
My ProtocolMy Protocoluser
kernelRouting
Table
Usage #1
IPv4RouterIPv4
Router
1GE1GE
1GE1GE
1GE1GE
1GE1GE
FwdingTable
FwdingTable
PacketBuffer
PacketBuffer
“Mirror”
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NetFPGA tutorial - India: May 2008 7 S T A N F O R D U N I V E R S I T Y
FPGAFPGA
MemoryMemory
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Building Modular Router Modules
PCI
CPUCPU MemoryMemory
Usage #2
NetFPGA DriverNetFPGA Driver
Java GUIFront Panel(Extensible)
Java GUIFront Panel(Extensible)
PW-OSPFPW-OSPF
In QMgmtIn Q
Mgmt
IPLookup
IPLookup
L2Parse
L2Parse
L3Parse
L3Parse
Out QMgmtOut QMgmt
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Verilog modules interconnected by FIFO interfaces
MyBlock
MyBlock
VerilogEDA Tools
(Xilinx, Mentor, etc.)
VerilogEDA Tools
(Xilinx, Mentor, etc.)
1. Design2. Simulate3. Synthesize4. Download
1. Design2. Simulate3. Synthesize4. Download
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NetFPGA tutorial - India: May 2008 8 S T A N F O R D U N I V E R S I T Y
FPGAFPGA
MemoryMemory
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Creating new systems
PCI
CPUCPU MemoryMemory
Usage #3
NetFPGA DriverNetFPGA Driver
1GE1GE
1GE1GE
1GE1GE
1GE1GE
My Design
(1GE MAC is soft/replaceable)
My Design
(1GE MAC is soft/replaceable)
VerilogEDA Tools
(Xilinx, Mentor, etc.)
VerilogEDA Tools
(Xilinx, Mentor, etc.)
1. Design2. Simulate3. Synthesize4. Download
1. Design2. Simulate3. Synthesize4. Download
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NetFPGA tutorial - India: May 2008 9 S T A N F O R D U N I V E R S I T Y
Tutorial Outline• Background
– Introduction to IISc (Kuruvilla)– Basics of an IP Router (John)– The NetFPGA Platform (John)
• The Stanford Base Reference Router– Demo1 : Reference Router running on the NetFPGA (Jad)– Inside the NetFPGA hardware (John)– Breakneck introduction to FPGAs and Verilog (Kuruvilla, John)– Exercise 1: Build your own Reference Router (Jad)
• The Enhanced Reference Router– Motivation: Understanding buffer size requirements in a router (John)– Demo 2: Observing and controlling the queue size (Jad)– Exercise 2: Enhancing the Reference Router (Jad)
• The Life of a Packet Through the NetFPGA– Hardware Datapath (Jad)– Interface to software: Exceptions and Host I/O (John) – Exercise 3: Drop 1 in N Packets (Jad)
• Concluding Remarks– Using NetFPGA for research and teaching (John)– Group Discussion (All)– Survey (You)
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NetFPGA tutorial - India: May 2008 10 S T A N F O R D U N I V E R S I T Y
Basic Operation of an IP RouterR3
A
B
C
R1
R2
R4 D
E
FR5
R5F
R3E
R3D
Next HopDestination
D
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NetFPGA tutorial - India: May 2008 11 S T A N F O R D U N I V E R S I T Y
What does a router do?R3
A
B
C
R1
R2
R4 D
E
FR5
R5F
R3E
R3D
Next HopDestination
D
16 3241
Data
Options (if any)
Destination Address
Source Address
Header ChecksumProtocolTTL
Fragment OffsetFlagsFragment ID
Total Packet LengthT.ServiceHLenVer
20
byte
s
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NetFPGA tutorial - India: May 2008 12 S T A N F O R D U N I V E R S I T Y
What does a router do?
A
B
C
R1
R2
R3
R4 D
E
FR5
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NetFPGA tutorial - India: May 2008 13 S T A N F O R D U N I V E R S I T Y
Basic Components of an IP Router
Control Plane
Datapathper-packet processing
SwitchingForwarding
Table
Routing Table
Routing Protocols
Management& CLI
Softw
areH
ardware
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NetFPGA tutorial - India: May 2008 14 S T A N F O R D U N I V E R S I T Y
Per-packet processing in an IP Router
1. Accept packet arriving on an incoming link.
2. Lookup packet destination address in the forwarding table, to identify outgoing port(s).
3. Manipulate IP header: e.g., decrement TTL, update header checksum.
5. Buffer packet in the output queue.
6. Transmit packet onto outgoing link.
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NetFPGA tutorial - India: May 2008 15 S T A N F O R D U N I V E R S I T Y
Generic Datapath Architecture
LookupIP Address
UpdateHeader
Header ProcessingData Hdr Data Hdr
ForwardingTable
ForwardingTable
IP Address Next Hop
QueuePacket
BufferMemoryBuffer
Memory
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NetFPGA tutorial - India: May 2008 16 S T A N F O R D U N I V E R S I T Y
CIDR and Longest Prefix Matches
The IP address space is broken into line segments. Each line segment is described by a prefix. A prefix is of the form x/y where x indicates the prefix of all
addresses in the line segment, and y indicates the length of the segment.
e.g. The prefix 128.9/16 represents the line segment containing addresses in the range: 128.9.0.0 … 128.9.255.255.
0 232-1
128.9/16
128.9.0.0
216
142.12/19
65/8
128.9.16.14
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NetFPGA tutorial - India: May 2008 17 S T A N F O R D U N I V E R S I T Y
Classless Interdomain Routing (CIDR)
0 232-1
128.9/16
128.9.16.14
128.9.16/20128.9.176/20
128.9.19/24
128.9.25/24
Most specific route = “longest matching prefix”
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NetFPGA tutorial - India: May 2008 18 S T A N F O R D U N I V E R S I T Y
Techniques for LPM in hardware• Linear search
– Slow• Direct lookup
– Currently requires too much memory– Updating a prefix leads to many changes
• Tries– Deterministic lookup time– Easily pipelined– But requires multiple memories/references
• TCAM (Ternary CAM)– Simple and widely used– But low-density, high-power– Gradually being replaced by new algorithms
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NetFPGA tutorial - India: May 2008 19 S T A N F O R D U N I V E R S I T Y
An IP Router on NetFPGA
SwitchingForwarding
Table
Routing Table
Routing Protocols
Management& CLI
Softw
areH
ardware
Linux user-levelprocesses
Verilog on NetFPGA PCI board
ExceptionProcessing
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NetFPGA tutorial - India: May 2008 20 S T A N F O R D U N I V E R S I T Y
NetFPGA Router
Function – 4 Gigabit Ethernet ports
Fully programmable– FPGA hardware
Low cost
Open-source FPGA hardware – Verilog base design
Open-souce Software– Drivers in C and C++
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NetFPGA tutorial - India: May 2008 21 S T A N F O R D U N I V E R S I T Y
NetFPGA Platform
Major Components– Interfaces
• 4 Gigabit Ethernet Ports• PCI Host Interface
– Memories• 36Mbits Static RAM• 512Mbits DDR2 Dynamic RAM
– FPGA Resources• Block RAMs• Configurable Logic Block (CLBs)• Memory Mapped Registers
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NetFPGA tutorial - India: May 2008 22 S T A N F O R D U N I V E R S I T Y
NetFPGA System
User Space
Linux Kernel
NIC
GE
PCI-ePCI
Browser& VideoClient
MonitorSoftware
GE
GE
GE
GE
GE
CADTools
NetFPGA RouterHardware
VI
VI
VI
VI
Packet Forwarding Table
(eth1 .. 2)(nf2c0 .. 3)
Web &VideoServer
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NetFPGA tutorial - India: May 2008 23 S T A N F O R D U N I V E R S I T Y
NetFPGA’s Hardware Components
• Xilinx Virtex-2 Pro FPGA for User Logic• Xilinx Spartan for PCI Host Interface • Cypress: 2 * 2.25 MB ZBT SRAM• Micron: 64MB DDR2 DRAM • Broadcom: PHY for 4 Gigabit Ethernet ports
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NetFPGA tutorial - India: May 2008 24 S T A N F O R D U N I V E R S I T Y
NetFPGA System Components• Host Ports
– Dual Gigabit Ethernetports on PCI-express card
• Network Ports– Quad Gigabit Ethernet
ports on NetFPGA PCI card
• Motherboard – Standard Intel or AMD-based
computer with PCI and PCI-express slots
• Processor – Dual or Quad-Core CPU
• Operating System– Linux CentOS 4.4 or 5.1
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NetFPGA tutorial - India: May 2008 25 S T A N F O R D U N I V E R S I T Y
• PCs assembled from parts– Stanford University– Cambridge University
• Pre-built systems available – Accent Technology Inc
• Details are in the Guidehttp://netfpga.org/static/guide.html
NetFPGA Cube Systems
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NetFPGA tutorial - India: May 2008 26 S T A N F O R D U N I V E R S I T Y
Rackmount NetFPGA hosts
NetFPGA inserts in PCI or PCI-X slot
Dell 2950 with PCI-X and PCI-Express Slots
Thanks: Brian Cashman for providing machine
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NetFPGA tutorial - India: May 2008 27 S T A N F O R D U N I V E R S I T Y
NetFPGA Lab Setup
(eth1 .. 2)
Nf2c3 : Connection to Ring on LeftCPU x2 Net-FPGA
Dual NICGE
PC
I-eP
CI
Client
NetFPGAControl SW
GE
GE
GE
GE
GECAD Tools
InternetRouter
Hardware
Eth2 : Server for NeighborServer
Eth1 : Local client & server
Nf2c1 : Connection to Neightbor
Nf2c2 : Local Host
Nf2c0 : Connection to Ring on Right
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NetFPGA tutorial - India: May 2008 28 S T A N F O R D U N I V E R S I T Y
Net-FPGA
NetFPGA Hardware Set for Demo #1
Net-FPGA
GE
GE
GE
GE
InternetRouter
Hardware
CPU x2
Net-FPGA
NICGE
PC
I-eP
CIVideo
Display
GE
GE
GE
GE
GE
CAD Tools
GE
GE
GE
GE
InternetRouter
Hardware
InternetRouter
Hardware
CPU x2
PC
I-eP
CI
VideoServer
NICGE
PC
I-e
GE
…
Server deliversstreaming HD videothrough a chain of NetFPGA Routers
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NetFPGA tutorial - India: May 2008 29 S T A N F O R D U N I V E R S I T Y
Physical Configuration of Testbed
• Qnty 10 (with one spare) of– Host
• Reference PC with specifications in NetFPGA Guide– NetFPGA
• From DigilentInc.com– Ethernet Adapter
• Intel Pro/1000 Dual-port Gigabit PCI-Express x4 NIC ( EXPI9402PT from Buy.com )
– Category 5E Gigabit Ethernet Cables• Loopback (Red, 1’ = 30cm)• Network (Green, 3’ = 1m)• Adjacent Host (Blue, 3’ = 1m)
• Additional Parts– RJ45 Cable connectors, Qnty=2
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NetFPGA tutorial - India: May 2008 30 S T A N F O R D U N I V E R S I T Y
3210
12
nf2c
eth
12
3210
12
nf2c
eth
11
3210
12
nf2c
eth
9
3210
12
nf2c
eth
8
3210
12
nf2c
eth
7
3210
12
nf2c
eth
6
3210
12
nf2c
eth
5
3210
12
nf2c
eth
4
3210
12
nf2c
eth
3
3210
12
nf2c
eth
2
Cable Configuration in the lab• NetFPGA Gigabit Ethernet Interfaces
– nf2c3 : Left neighbor in network (green)– nf2c2 : Local host interface (red)– nf2c1 : Routes for adjacent server (blue)– nf2c0 : Right neighbor in network (green)
• Host Ethernet Interfaces – eth1 : Local host interface (red)– eth2 : Server for neighbor (blue)
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NetFPGA tutorial - India: May 2008 31 S T A N F O R D U N I V E R S I T Y
Demo 1
Reference Router running on the NetFPGA
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NetFPGA tutorial - India: May 2008 32 S T A N F O R D U N I V E R S I T Y
HDDisplay
Topology of NetFPGA Routers
VideoServer
Demo
1
Demo
1
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NetFPGA tutorial - India: May 2008 33 S T A N F O R D U N I V E R S I T Y
Setup for the Reference Router
Each NetFPGA card has four ports
Port 2 connected to Client / Server
Ports 0 and 3 connected to adjacent NetFPGA cards
NetFPGA
Video Client
Demo
1
Demo
1
NetFPGA
NetFPGA
Video Server
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NetFPGA tutorial - India: May 2008 34 S T A N F O R D U N I V E R S I T Y
3210
12
nf2c
eth
12
3210
12
nf2c
eth
11
3210
12
nf2c
eth
9
3210
12
nf2c
eth
8
3210
12
nf2c
eth
7
3210
12
nf2c
eth
6
3210
12
nf2c
eth
5
3210
12
nf2c
eth
4
3210
12
nf2c
eth
3
3210
12
nf2c
eth
2
Cable Configuration for Demo 1• NetFPGA Gigabit Ethernet Interfaces
– nf2c3 : Left neighbor in network (green)– nf2c2 : Local host interface (red)– nf2c0 : Right neighbor in network (green)
• Host Ethernet Interfaces – eth1 : Local host interface (red)
Demo
1
Demo
1
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NetFPGA tutorial - India: May 2008 35 S T A N F O R D U N I V E R S I T Y
Subnet Configuration
.1.1
.1.2.3.1
.30.2
.4.1
.4.2
.6.1.3.2
.7.1
.7.2
.9.1
.6.2
.10.1
.10.2
.12.1
.9.2
.13.1
.13.2
.15.1
.12.2
.16.1
.16.2.15.2
.28.1
.28.2.27.1
.30.1
.25.1
.25.2.24.1
.27.2
.22.1
.22.2.21.1
.24.2
.19.1
.19.2
.17.1
.21.2.18.2
.5.1 .8.1 .11.1 .14.1 .18.1
.20.1
.23.1.26.1
.29.1
.2.1
Video ClientShortest Path
Video Server
Demo
1
Demo
1
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NetFPGA tutorial - India: May 2008 36 S T A N F O R D U N I V E R S I T Y
Working IP Router
• Objectives – Become familiar with
Stanford Reference Router
– Observe PW-OSPF re-routing traffic around a failure
Demo
1
Demo
1
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NetFPGA tutorial - India: May 2008 37 S T A N F O R D U N I V E R S I T Y
Streaming Video through the NetFPGA
• Video server– Source files
/var/www/html/video– Network URL :
http://192.168.Net.Host/video
• Video client– Windows Media Player– Linux mplayer
• Video traffic– MPEG2 HDTV (35 Mbps)– MPEG2 TV (9 Mbps)– DVI (3 Mbps)– WMF (1.7 Mbps)
Demo
1
Demo
1
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NetFPGA tutorial - India: May 2008 38 S T A N F O R D U N I V E R S I T Y
Step 1 – Observe the Routing Tables
The router is already configured and running on your machines
The routing table has converged to the routing decisions with minimum number of hops
Next, break a link …
Demo
1
Demo
1
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NetFPGA tutorial - India: May 2008 39 S T A N F O R D U N I V E R S I T Y
Step 2 - Dynamic Re-routing
Break the link between video server and video client
Routers re-route traffic around the broken link and video continues playing
.1.1
.1.2
.3.1
.30.2
.4.1
.4.2
.6.1.3.2
.7.1
.7.2
.9.1
.6.2
.10.1
.10.2
.12.1
.9.2
.13.1
.13.2
.15.1
.12.2
.16.1
.16.2
.15.2
.28.1
.28.2.27.1
.30.1
.25.1
.25.2.24.1
.27.2
.22.1
.22.2.21.1
.24.2
.19.1
.19.2
.17.1
.21.2
.18.2
.5.1 .8.1 .11.1 .14.1
.18.1
.20.1
.23.1.26.1
.29.1
.2.1
Demo
1
Demo
1
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NetFPGA tutorial - India: May 2008 40 S T A N F O R D U N I V E R S I T Y
Integrated Circuit TechnologyAnd Field Programmable Gate
Arrays (FPGAs)
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NetFPGA tutorial - India: May 2008 41 S T A N F O R D U N I V E R S I T Y
Integrated Circuit Technology
Full-custom Design – Complementary Metal Oxide Semiconductor (CMOS)
Semi-custom ASIC Design – Gate array– Standard cell
Programmable Logic Device– Programmable Array Logic– Field Programmable Gate Arrays
Processors
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NetFPGA tutorial - India: May 2008 42 S T A N F O R D U N I V E R S I T Y
Combinatorial Logic
AB
CD
Z
Look-Up Tables
Combinatorial logic is stored in Look-Up Tables (LUTs) – Also called
Function Generators (FGs)– Capacity is limited only by
number of inputs, not complexity– Delay through the LUT is constant
A B C D Z
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
. . .
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Diagram From: Xilinx, Inc
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NetFPGA tutorial - India: May 2008 43 S T A N F O R D U N I V E R S I T Y
Slice 0
LUT Carry
LUT Carry D QCE
PRE
CLR
DQCE
PRE
CLR
Xilinx CLB Structure
Each slice has four outputs– Two registered outputs,
two non-registered outputs
– Two BUFTs associated with each CLB, accessible by all 16 CLB outputs
Carry logic run vertically – Signals run upwards– Two independent
carry chains per CLB
Diagram From: Xilinx, Inc (Courtesy Jeff Weintraub)
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NetFPGA tutorial - India: May 2008 44 S T A N F O R D U N I V E R S I T Y
Field Programmable Gate Arrays
CLB– Primitive element of FPGA
Routing Module– Global routing– Local interconnect
Macro Blocks– Block Memories– Microprocessor
I/O Block
4 LUT
G4
G3
G2
G1
G
4 LUT
F4
F3
F2
F1
F
3 LUT
H
S
R
D Q
S
R
D Q
H1
Din Clk
YQ
Y
XQ
X
M
M
M
M
CLB
GRMLocal R outing
CLB PIP
...
...
...
... ...
......
3rd Generation LUT-based FPGA
Pad Routing CLB M atrix I/O
M acroBlock(uP,M em)
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NetFPGA tutorial - India: May 2008 45 S T A N F O R D U N I V E R S I T Y
NetFPGA Block Diagram
NetFPGA platform
1GE
M
AC
1GE
M
AC
1GE
M
AC
1GE
M
AC
Your hardware specified in Verilog source code connected to components of the Reference Router circuits and cores.
-
18Mb
SR
AM
1GE
P
HY
1GE
P
HY
1GE
P
HY
1GE
P
HY
V2-Pro50 FPGA w/ infrastructure64M
BD
DR
2S
DR
AM
Linux OS - NetFPGA Kernel driverHostcomputer
User-defined software networking applications
Four G
igabit Ethernet Interfaces
18Mb
SR
AM
FIFOpacketbuffers
Control, PCIInterface
3 Gb
SA
TA
Board- B
oard Interconnect
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NetFPGA tutorial - India: May 2008 46 S T A N F O R D U N I V E R S I T Y
Details of NetFPGA
• Fits into Standard PCI slot– Standard Bus : 32 bits, 33 MHz
• Provides Interfaces for processing network packets– 4 Gigabit Ethernet Ports
• Allows hardware-accelerated processing – Implemented with Field Programmable Gate Array (FPGA) Logic
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NetFPGA tutorial - India: May 2008 47 S T A N F O R D U N I V E R S I T Y
Introduction to the VerilogHardware Description Language
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NetFPGA tutorial - India: May 2008 48 S T A N F O R D U N I V E R S I T Y
Hardware Description Languages
• Concurrent– By Default, Verilog statements
evaluated concurrently
• Express fine grain parallelism– Allows gate-level parallelism
• Provides Precise Description– Eliminates ambiguity about operation
• Synthesizable– Generates hardware from description
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NetFPGA tutorial - India: May 2008 49 S T A N F O R D U N I V E R S I T Y
Verilog Data Types
reg [7:0] A; // 8-bit register, MSB to LSB // (Preferred bit order for NetFPGA)
reg [0:15] B; // 16-bit register, LSB to MSB
B = {A[7:0],A[0:7]}; // Assignment of bits
reg [31:0] Mem [0:1023]; // 1K Word Memory
integer Count; // simple signed 32-bit integerinteger K[1:64]; // an array of 64 integerstime Start, Stop; // Two 64-bit time variables
From: CSCI 320 Computer ArchitectureHandbook on Verilog HDL, by Dr. Daniel C. Hyde :
http://eesun.free.fr/DOC/VERILOG/verilog-manual.html
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NetFPGA tutorial - India: May 2008 50 S T A N F O R D U N I V E R S I T Y
Signal Multiplexers
From: http://eesun.free.fr/DOC/VERILOG/synvlg.html
Two input multiplexer (using if / else) reg y; always @*
if (select) y = a; else y = b;
Two input multiplexer (using ternary operator ?:)
wire t = (select ? a : b);
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NetFPGA tutorial - India: May 2008 51 S T A N F O R D U N I V E R S I T Y
Larger Multiplexers
Three input multiplexer
reg s; always @* begin case (select2)
2'b00: s = a; 2'b01: s = b; default: s = c; endcase end
From: http://eesun.free.fr/DOC/VERILOG/synvlg.html
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NetFPGA tutorial - India: May 2008 52 S T A N F O R D U N I V E R S I T Y
Synchronous Storage Elements• Values change at
times governed by clock
Clock Transition
t=0 t=1 t=20
1Clock
time
Clock Transition
S0Dout
t=0
A B
A B CDin
t=0
Clock
Din DoutQD
– Clock• Input to circuit
– Clock Event• Example: Rising edge
– Flip/Flop• Transfers Value From Din
to Dout on Clock event
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NetFPGA tutorial - India: May 2008 53 S T A N F O R D U N I V E R S I T Y
Finite State Machines
Copyright 2001, John W. Lockwood, All Rights Reserved
Combinational Logic
Inputs (X)
S(t) S(t+1)=(X,S(t))
Outputs (Z)
StateNext
State Storage
...
[Moore](S(t))
[Mealy](X,S(t))
-or-
Q D
Q D
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NetFPGA tutorial - India: May 2008 54 S T A N F O R D U N I V E R S I T Y
Synthesizable Verilog : Delay Flip/Flops
From: http://eesun.free.fr/DOC/VERILOG/synvlg.html
D type flip flop with data enablereg q; always @ (posedge clk)
if (enable) q <= d;
D-type flip flop reg q; always @ (posedge clk)
q <= d;
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NetFPGA tutorial - India: May 2008 55 S T A N F O R D U N I V E R S I T Y
Exercise 1
Build the Reference Router
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NetFPGA Tutorial 56 S T A N F O R D U N I V E R S I T Y
Reference Router Pipeline
• Five stages– Input– Input Arbitration– Routing Decision and
packet modification– Output Queuing– Output
• Packet-based module interface
• Pluggable design
Exerc
ise
1
Exerc
ise
1
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
Input ArbiterInput Arbiter
Output Port LookupOutput Port Lookup
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
Output QueuesOutput Queues
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NetFPGA tutorial - India: May 2008 57 S T A N F O R D U N I V E R S I T Y
Make your own router
Objectives: – Learn how to build hardware– Run the software– Explore router architecture
Execution– Start synthesis– Rerun the GUI with the new hardware– Test connectivity and statistics with pings– Explore pipeline in the details page– Explore detailed statistics in the details page
Exerc
ise
1
Exerc
ise
1
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NetFPGA Tutorial 58 S T A N F O R D U N I V E R S I T Y
Step 1 - Build the hardware
Close all windows
Start terminal, cd to “NF2/projects/tutorial_router/synth”
Run “make clean”
Start synthesis with “make”
Exerc
ise
1
Exerc
ise
1
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NetFPGA tutorial - India: May 2008 59 S T A N F O R D U N I V E R S I T Y
First Break
(while hardware compiles)
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NetFPGA Tutorial 60 S T A N F O R D U N I V E R S I T Y
Step 2 - Run Homemade Router
cd to “NF2/projects/tutorial_router/sw”
Type:
./tut_router_gui.pl --use_bin ../../../bitfiles/tutorial_router.bit
to use the just-built router hardware
To Stream video, run: ./mp 192.168.X.Y where X.Y = 25.1 or 19.1 or 7.1 or any other server as listed on Demo 1 handout
Exerc
ise
1
Exerc
ise
1
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NetFPGA Tutorial 61 S T A N F O R D U N I V E R S I T Y
Step 4 - Connectivity and StatisticsPing any addresses
192.168.x.y where x is from 1-20 and y is 1 or 2
Open the statistics tab in the Quickstart window to see some statistics
Explore more statistics in modules under the details tab
Exerc
ise
1
Exerc
ise
1
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NetFPGA tutorial - India: May 2008 62 S T A N F O R D U N I V E R S I T Y
Step 5 - Explore Router Architecture
Click the Details tab of the Quickstart window
This is the reference router pipeline – a canonical, simple to understand, modular router pipeline
Exerc
ise
1
Exerc
ise
1
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NetFPGA Tutorial 63 S T A N F O R D U N I V E R S I T Y
Step 6 - Explore Output Queues
Click on the Output Queues module in the Details tab
The page gives configuration details
…and statistics
Exerc
ise
1
Exerc
ise
1
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NetFPGA tutorial - India: May 2008 64 S T A N F O R D U N I V E R S I T Y
Understanding Buffer Size Requirements in a Router
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NetFPGA Tutorial 65 S T A N F O R D U N I V E R S I T Y
Buffer Requirements in a Router
Buffer size matters:– Small queues reduce delay– Large buffers are expensive
Theoretical tools predict requirements– Queuing theory– Large deviation theory– Mean field theory
Yet, there is no direct answer.– Flows have a closed-loop nature– Question arises on whether focus should be on
equilibrium state or transient state..
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NetFPGA Tutorial 66 S T A N F O R D U N I V E R S I T Y
• Universally applied rule-of-thumb:– A router needs a buffer size:– 2T is the two-way propagation delay (or just 250ms)– C is capacity of bottleneck link
• Context– Mandated in backbone and edge routers.– Appears in RFPs and IETF architectural guidelines.– Already known by inventors of TCP
• [Van Jacobson, 1988]
– Has major consequences for router design
CTB 2
CRouterSource Destination
2T
Rule-of-thumb
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NetFPGA Tutorial 67 S T A N F O R D U N I V E R S I T Y
The Story So Far
)(logO2
2 )2()1( Wn
CTCT
)(logO
22 )2()1( W
n
CTCT
10,000 20# packetsat 10Gb/s
1,000,000
(1) Assume: Large number of desynchronized flows; 100% utilization(2) Assume: Large number of desynchronized flows; <100% utilization
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NetFPGA Tutorial 68 S T A N F O R D U N I V E R S I T Y
Using NetFPGA to explore buffer size
• Need to reduce buffer size and measure occupancy
• Alas, not possible in commercial routers• So, we will use NetFPGA instead
Objective:– Use NetFPGA to understand how large a buffer
we need for a single TCP flow.
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NetFPGA Tutorial 69 S T A N F O R D U N I V E R S I T Y
Rule for adjusting W– If an ACK is received: W ← W+1/W– If a packet is lost: W ← W/2
Why 2TxC for a single TCP Flow?
Only W packets may be outstanding
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NetFPGA Tutorial 70 S T A N F O R D U N I V E R S I T Y
Time evolution of a single TCP flow through a router. Buffer is < 2T*C
Time Evolution of a Single TCP Flow
Time evolution of a single TCP flow through a router. Buffer is 2T*C
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NetFPGA tutorial - India: May 2008 71 S T A N F O R D U N I V E R S I T Y
NetFPGA Hardware Set for Demo #2
CPU x2P
CI-e
VideoServer
NICGE
PC
I-e
GE
Net-FPGA
CPU x2
NICGE
PC
I-eP
CIVideo
Client
GE
GE
GE
GE
GE
InternetRouter
Hardware
…
Server deliversstreaming HD videoto adjacent client
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NetFPGA tutorial - India: May 2008 72 S T A N F O R D U N I V E R S I T Y
Demo 2
Observing and Controlling the Queue Size
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NetFPGA tutorial - India: May 2008 73 S T A N F O R D U N I V E R S I T Y
Setup for the Demo 2
LocalHost
Demo
2
Demo
2
NetFPGA
AdjacentWeb & Video
Server
eth1
eth2nf2c2
nf2c1
Router
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NetFPGA tutorial - India: May 2008 74 S T A N F O R D U N I V E R S I T Y
3210
12
nf2c
eth
12
3210
12
nf2c
eth
11
3210
12
nf2c
eth
9
3210
12
nf2c
eth
8
3210
12
nf2c
eth
7
3210
12
nf2c
eth
6
3210
12
nf2c
eth
5
3210
12
nf2c
eth
4
3210
12
nf2c
eth
3
3210
12
nf2c
eth
2
Cable Configuration for Demo 2• NetFPGA Gigabit Ethernet Interfaces
– nf2c2 : Local host interface (red)– nf2c1 : Router for adjacent server (blue)
• Host Ethernet Interfaces – eth1 : Local host interface (red)– eth2 : Server for neighbor (blue)
Demo
2
Demo
2
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NetFPGA tutorial - India: May 2008 75 S T A N F O R D U N I V E R S I T Y
Interfaces and Subnets
• eth1 connects your host to your NetFPGA Router • nf2c2 routes to nf2c1 (your adjacent server)• eth2 serves Web and Video traffic to your neighbour• nf2c0 & nf2c3 (the network ring) are unused
.1.1 .1.2
.4.1
.4.2
.7.1
.7.2
.10.1
.10.2
.13.1
.13.2
.16.1
.16.2
.28.1
.28.2
.25.1
.25.2
.22.1
.22.2
.19.1
.19.2
Demo
2
Demo
2
.2.2
.2.1
.5.2
.5.1
.8.2
.8.1
.11.2
.11.1
.14.2
.14.1.17.2
.17.1
.20.2
.20.1
.23.2
.23.1
.26.2
.26.1
.29.2
.29.1
This configuration allows you to modify and test your router without affecting others
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NetFPGA tutorial - India: May 2008 76 S T A N F O R D U N I V E R S I T Y
Enhanced Router
Objectives – Observe router with new modules– New modules: rate limiting, event capture
Execution– Run event capture router– Look at routing tables– Explore details pane– Start tcp transfer, look at queue occupancy– Change rate, look at queue occupancy
Demo
2
Demo
2
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NetFPGA Tutorial 77 S T A N F O R D U N I V E R S I T Y
Step 1 - Run Pre-made Enhanced Router
Start terminal and cd to “NF2/projects/tutorial_router/sw/”
Type “./tut_adv_router_gui.pl”
A familiar GUI should start
Demo
2
Demo
2
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NetFPGA Tutorial 78 S T A N F O R D U N I V E R S I T Y
Step 3 - Explore Enhanced Router
Click on the Details tab
A similar Pipeline to the one seen previously shows with some additions
Demo
2
Demo
2
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NetFPGA Tutorial 79 S T A N F O R D U N I V E R S I T Y
Enhanced Router Pipeline
Two modules added1. Event Capture
to capture output queue events (writes, reads, drops)
2. Rate Limiter to create a bottleneck
Demo
2
Demo
2
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
Input ArbiterInput Arbiter
Output Port LookupOutput Port Lookup
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
Output QueuesOutput Queues
RateLimiter
RateLimiter
Event CaptureEvent Capture
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NetFPGA Tutorial 80 S T A N F O R D U N I V E R S I T Y
Step 4 - Decrease the Link RateTo create bottleneck and
show the TCP “sawtooth”, link-rate is decreased.
In the Details tab click the “Rate Limit” module
Check Enable
Set link rate to 1.953Mbps
Demo
2
Demo
2
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NetFPGA Tutorial 81 S T A N F O R D U N I V E R S I T Y
Step 5 – Decrease Queue Size
Go back to the Details Panel and click on “Output Queues”.
Select the “Output Queue 2” tab.
Change the output queues size in packets slider to 16
Demo
2
Demo
2
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NetFPGA Tutorial 82 S T A N F O R D U N I V E R S I T Y
Step 6 - Start Event Capture
Click on the Event Capture module under the Details tab
This should start the configuration page
Demo
2
Demo
2
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NetFPGA Tutorial 83 S T A N F O R D U N I V E R S I T Y
Step 7 - Configure Event Capture
Check Send to local host to receive events on the local host
Check Monitor Queue 2 to monitor output queue of MAC port1
Check “Enable Capture” to start Event capture
Demo
2
Demo
2
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NetFPGA Tutorial 84 S T A N F O R D U N I V E R S I T Y
Step 8 - Start TCP Transfer
We will use iperf to run a large TCP transfer and look at queue evolution
Start a terminal and cd to“NF2/projects/tutorial_router/sw”
type “iperf.sh”
Demo
2
Demo
2
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NetFPGA Tutorial 85 S T A N F O R D U N I V E R S I T Y
Step 9 - Look at Event Capture Results
Click on the Event Capture module under the details tab.
The sawtooth pattern should now be visible.
Demo
2
Demo
2
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NetFPGA Tutorial 86 S T A N F O R D U N I V E R S I T Y
Queue Occupancy Charts
Leave the control windows open
Observe the TCP/IP sawtooth
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NetFPGA tutorial - India: May 2008 87 S T A N F O R D U N I V E R S I T Y
Exercise 2: Enhancing the Reference Router
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NetFPGA tutorial - India: May 2008 88 S T A N F O R D U N I V E R S I T Y
Enhance Your Router
Objectives – Add new modules to datapath– Synthesize and test router
Execution– Open user_datapath.v, uncomment
delay/rate/event capture modules– Synthesize– After synthesis, test the new system.
Exerc
ise
2
Exerc
ise
2
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NetFPGA tutorial - India: May 2008 89 S T A N F O R D U N I V E R S I T Y
An aside: xemacs TipsWe will modify Verilog source code with xemacs
– To undo a command, type• ctrl+shift+'-'
– To cancel a multi-keystroke command, just type • ctrl+g
– To select lines, • hold shift and press the arrow keys.
– To comment (remove from compilation) selected lines, • type ctrl+c+c
– To uncomment a commented block, • move the cursor inside the commented block • Type ctrl+c+u
– To save type • ctrl+x+s
– To search for a term • type ctrl+s search_pattern
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NetFPGA Tutorial 90 S T A N F O R D U N I V E R S I T Y
Step 1 - Open the Source
We will modify the Verilog source code to add event capture and rate limiter modules
We will simply comment and uncomment existing code
Open terminal
Type xemacs NF2/projects/tutorial_router/src/user_data_path.v
Exerc
ise
2
Exerc
ise
2
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NetFPGA Tutorial 91 S T A N F O R D U N I V E R S I T Y
Step 2 - Add wires
Now we need to add wires to connect the new modules
Search for “new wires” (ctrl+s new wires) then press Enter
Uncomment the wires (ctrl+c+u)
Exerc
ise
2
Exerc
ise
2
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NetFPGA Tutorial 92 S T A N F O R D U N I V E R S I T Y
Step 3a - Connect Event Capture
Search for opl_output (ctrl+s opl_output) then press Enter
Comment the four lines above (up, shift + up + up + up + up, ctrl+c+c)
Uncomment the block below to connect the outputs (ctrl+s opl_out, ctrl+c+u)
Exerc
ise
2
Exerc
ise
2
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NetFPGA Tutorial 93 S T A N F O R D U N I V E R S I T Y
Step 3b - Connect the Output Queue Registers
Search for opl_output (ctrl+s opl_output, Enter)
Comment the 6 lines (select the six lines by using shift+arrow keys, then type ctrl+c+c)
Uncomment the commented block by scrolling down into the block and typing ctrl+c+u
Exerc
ise
2
Exerc
ise
2
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NetFPGA Tutorial 94 S T A N F O R D U N I V E R S I T Y
Step 4 - Add the Event Capture Module
Search for evt_capture_top (ctrl+s evt_capture_top) then press Enter
Uncomment the block (ctrl+c+u)
Exerc
ise
2
Exerc
ise
2
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NetFPGA Tutorial 95 S T A N F O R D U N I V E R S I T Y
Step 5 - Add the Drop Nth Module
Search for drop_nth_packet (ctrl+s drop_nth_packet) then press Enter
Uncomment the block (ctrl+c+u)
Exerc
ise
2
Exerc
ise
2
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NetFPGA Tutorial 96 S T A N F O R D U N I V E R S I T Y
Step 6 - Connect the Output Queue to the Rate Limiter
Search for port_outputs (ctrl+s port_outputs, Enter)
Comment the 4 lines above (select the four lines by using shift+arrow keys, then type ctrl+c+c)
Uncomment the commented block by scrolling down into the block and typing ctrl+c+u
Exerc
ise
2
Exerc
ise
2
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NetFPGA Tutorial 97 S T A N F O R D U N I V E R S I T Y
Step 7 - Connect the Registers
Search for port_outputs (ctrl+s port_outputs, Enter)
Comment the 6 lines (select the six lines by using shift+arrow keys, then type ctrl+c+c)
Uncomment the commented block by scrolling down into the block and typing ctrl+c+u
Exerc
ise
2
Exerc
ise
2
six
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NetFPGA Tutorial 98 S T A N F O R D U N I V E R S I T Y
Step 8 - Add Rate Limiter
Scroll down until you reach the next “Excluded” block
Uncomment the block containing the rate limiter instantiations. (scroll into the block and type ctrl+c+u)
Save (ctrl+x+s)
Exerc
ise
2
Exerc
ise
2
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NetFPGA Tutorial 99 S T A N F O R D U N I V E R S I T Y
Step 9 - Build the hardware
Start terminal, cd to “NF2/projects/tutorial_router/synth”
Run “make clean”
Start synthesis with “make”
Exerc
ise
2
Exerc
ise
2
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NetFPGA tutorial - India: May 2008 100 S T A N F O R D U N I V E R S I T Y
Second Break
(while hardware compiles)
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NetFPGA tutorial - India: May 2008 101 S T A N F O R D U N I V E R S I T Y
Hardware Datapath
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NetFPGA tutorial - India: May 2008 102 S T A N F O R D U N I V E R S I T Y
Full System Components
Software
PCI Bus
NetFPGA
CPURxQCPURxQ
CPUTxQCPUTxQ
nf2_reg_grpnf2_reg_grp
user data pathuser data path
nf2c0nf2c0 nf2c1nf2c1 nf2c2nf2c2 nf2c3nf2c3 ioctlioctl
MACTxQMACTxQ
MACRxQMACRxQ
Ethernet
CPURxQCPURxQ
CPUTxQCPUTxQ
CPURxQCPURxQ
CPUTxQCPUTxQ
CPURxQCPURxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
MACRxQMACRxQ
MACTxQMACTxQ
MACRxQMACRxQ
MACTxQMACTxQ
MACRxQMACRxQ
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NetFPGA tutorial - India: May 2008 103 S T A N F O R D U N I V E R S I T Y
port0 port2192.168.2.y192.168.1.x
Life of a Packet through the hardware
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NetFPGA tutorial - India: May 2008 104 S T A N F O R D U N I V E R S I T Y
Router Stages Again
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
Input ArbiterInput Arbiter
Output Port LookupOutput Port Lookup
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
Output QueuesOutput Queues
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NetFPGA tutorial - India: May 2008 105 S T A N F O R D U N I V E R S I T Y
Inter-module Communication
Using “Module Headers”:
IP Hdr
Eth Hdr
…
0
0
0
Last word of packet0x10
Last Module Hdry
……
Module Hdrx Contain information such as packet length, input port, output port, …
Data Word(64 bits)
Ctrl Word(8 bits)
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NetFPGA tutorial - India: May 2008 106 S T A N F O R D U N I V E R S I T Y
data
Inter-module Communication
ctrlwr
rdy
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NetFPGA tutorial - India: May 2008 107 S T A N F O R D U N I V E R S I T Y
MAC Rx Queue
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NetFPGA tutorial - India: May 2008 108 S T A N F O R D U N I V E R S I T Y
Rx Queue
IP Hdr:IP Dst: 192.168.2.3,
TTL: 64, Csum:0x3ab4
Eth Hdr:Dst MAC = port 0,
Ethertype = IP
Data
0
0
0
Pkt length,input port = 0
0xff
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NetFPGA tutorial - India: May 2008 109 S T A N F O R D U N I V E R S I T Y
Input Arbiter
Pkt
Pkt
Pkt
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NetFPGA tutorial - India: May 2008 110 S T A N F O R D U N I V E R S I T Y
Output Port Lookup
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NetFPGA tutorial - India: May 2008 111 S T A N F O R D U N I V E R S I T Y
IP Hdr:IP Dst: 192.168.2.3,
TTL: 64, Csum:0x3ab4
IP Hdr:IP Dst: 192.168.2.3,
TTL: 63, Csum:0x3ac2
Output Port Lookup
EthHdr: Dst MAC = 0Src MAC = x,
Ethertype = IP
Data
0
0
0
Pkt length,input port = 0
0xff
output port = 40x04
1- Check input port matches
Dst MAC
2- Check TTL, checksum
3- Lookup next hop IP & output port
(LPM)
4- Lookup next hop MAC address (ARP)
5- Add output port module
6- Modify MAC Dst and Src addresses
7-Decrement TTL and update
checksum
EthHdr: Dst MAC = nextHop Src MAC = port 4,
Ethertype = IP
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NetFPGA tutorial - India: May 2008 112 S T A N F O R D U N I V E R S I T Y
Output Queues
OQ0
OQ4
OQ7
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NetFPGA tutorial - India: May 2008 113 S T A N F O R D U N I V E R S I T Y
MAC Tx Queue
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NetFPGA tutorial - India: May 2008 114 S T A N F O R D U N I V E R S I T Y
MAC Tx Queue
IP Hdr:IP Dst: 192.168.2.3,
TTL: 64, Csum:0x3ab4
IP Hdr:IP Dst: 192.168.2.3,
TTL: 63, Csum:0x3ac2
EthHdr: Dst MAC = nextHop Src MAC = port 4,
Ethertype = IP
Data
0
0
0
Pkt length,input port = 0
0xff
output port = 40x04
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NetFPGA tutorial - India: May 2008 115 S T A N F O R D U N I V E R S I T Y
Exception Packet
• Example: TTL = 0 or TTL = 1• Packet has to be sent to the CPU which will
generate an ICMP packet as a response• Difference starts at the Output Port lookup
stage
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NetFPGA tutorial - India: May 2008 116 S T A N F O R D U N I V E R S I T Y
Exception Packet Path
Software
PCI Bus
NetFPGA
CPURxQCPURxQ
CPUTxQCPUTxQ
CPURxQCPURxQ
CPUTxQCPUTxQ
CPURxQCPURxQ
CPUTxQCPUTxQ
CPURxQCPURxQ
CPUTxQCPUTxQ
nf2_reg_grpnf2_reg_grp
user data pathuser data path
nf2c0nf2c0 nf2c1nf2c1 nf2c2nf2c2 nf2c3nf2c3 ioctlioctl
MACTxQMACTxQ
MACRxQMACRxQ
MACTxQMACTxQ
MACRxQMACRxQ
MACTxQMACTxQ
MACRxQMACRxQ
MACTxQMACTxQ
MACRxQMACRxQ
Ethernet
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NetFPGA tutorial - India: May 2008 117 S T A N F O R D U N I V E R S I T Y
IP Hdr:IP Dst: 192.168.2.3,
TTL: 1, Csum:0x3ab4
Output Port Lookup
EthHdr: Dst MAC = 0,Src MAC = x,
Ethertype = IP
Data
0
0
0
Pkt length,input port = 0
0xff
output port = 10x04
1- Check input port matches
Dst MAC
2- Check TTL, checksum – EXCEPTION!
3- Add output port module
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NetFPGA tutorial - India: May 2008 118 S T A N F O R D U N I V E R S I T Y
Output Queues
OQ0
OQ1
OQ2
OQ7
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NetFPGA tutorial - India: May 2008 119 S T A N F O R D U N I V E R S I T Y
CPU Tx Queue
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NetFPGA tutorial - India: May 2008 120 S T A N F O R D U N I V E R S I T Y
CPU Tx Queue
IP Hdr:IP Dst: 192.168.2.3,
TTL: 1, Csum:0x3ab4
EthHdr: Dst MAC = 0, Src MAC = x,
Ethertype = IP
Data
0
0
0
Pkt length,input port = 0
0xff
output port = 10x04
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NetFPGA tutorial - India: May 2008 121 S T A N F O R D U N I V E R S I T Y
ICMP Packet
• For the ICMP packet, the packet arrives at the CPU Rx Queue from the PCI Bus
• Follows the same path as a packet from the MAC until the Output Port Lookup.
• The OPL module seeing the packet is from the CPU Rx Queue 1, sets the output port directly to 0.
• The packet then continues on the same path as the non-exception packet to the Output Queues and then MAC Tx queue 0.
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NetFPGA tutorial - India: May 2008 122 S T A N F O R D U N I V E R S I T Y
ICMP Packet Path
Software
PCI Bus
NetFPGA
CPURxQCPURxQ
CPUTxQCPUTxQ
CPURxQCPURxQ
CPUTxQCPUTxQ
CPURxQCPURxQ
CPUTxQCPUTxQ
CPURxQCPURxQ
CPUTxQCPUTxQ
nf2_reg_grpnf2_reg_grp
user data pathuser data path
nf2c0nf2c0 nf2c1nf2c1 nf2c2nf2c2 nf2c3nf2c3 ioctlioctl
MACTxQMACTxQ
MACRxQMACRxQ
MACTxQMACTxQ
MACRxQMACRxQ
MACTxQMACTxQ
MACRxQMACRxQ
MACTxQMACTxQ
MACRxQMACRxQ
Ethernet
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NetFPGA tutorial - India: May 2008 123 S T A N F O R D U N I V E R S I T Y
NetFPGA-Host Interaction
• Linux driver interfaces with hardware– Packet interface via standard Linux network
stack
– Register reads/writes via ioctl system call with wrapper functions:
• readReg(nf2device *dev, int address, unsigned *rd_data)• writeReg(nf2device *dev, int address, unsigned *wr_data)
eg:readReg(&nf2, OQ_NUM_PKTS_STORED_0, &val);
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NetFPGA tutorial - India: May 2008 124 S T A N F O R D U N I V E R S I T Y
NetFPGA-Host Interaction
NetFPGA to host packet transferNetFPGA to host packet transfer
PC
I Bu
sP
CI B
us
2. Interrupt notifies driver of packet arrival
2. Interrupt notifies driver of packet arrival
3. Driver sets up and initiates DMA transfer
3. Driver sets up and initiates DMA transfer
1. Packet arrives – forwarding table sends to CPU queue
1. Packet arrives – forwarding table sends to CPU queue
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NetFPGA tutorial - India: May 2008 125 S T A N F O R D U N I V E R S I T Y
NetFPGA-Host Interaction
NetFPGA to host packet transfer (cont)NetFPGA to host packet transfer (cont)
PC
I Bu
sP
CI B
us
4. NetFPGA transfers packet via DMA
4. NetFPGA transfers packet via DMA
5. Interrupt signals completion of DMA
5. Interrupt signals completion of DMA
6. Driver passes packet to network stack6. Driver passes packet to network stack
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NetFPGA tutorial - India: May 2008 126 S T A N F O R D U N I V E R S I T Y
NetFPGA-Host Interaction
Host to NetFPGA packet transfersHost to NetFPGA packet transfers
PC
I Bu
sP
CI B
us
3. Interrupt signals completion of DMA
3. Interrupt signals completion of DMA
1. Software sends packet via network sockets. Packet delivered to driver.
1. Software sends packet via network sockets. Packet delivered to driver.
2. Driver sets up and initiates DMA transfer
2. Driver sets up and initiates DMA transfer
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NetFPGA tutorial - India: May 2008 127 S T A N F O R D U N I V E R S I T Y
NetFPGA-Host Interaction
Register accessRegister access
PC
I Bu
sP
CI B
us
1. Software makes ioctl call on network socket. ioctl passed to driver.
1. Software makes ioctl call on network socket. ioctl passed to driver.
2. Driver performs PCI memory read/write
2. Driver performs PCI memory read/write
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NetFPGA tutorial - India: May 2008 128 S T A N F O R D U N I V E R S I T Y
NetFPGA-Host Interaction
• Packet transfers shown using DMA interface
• Alternative: use programmed IO to transfer packets via register reads/writes– slower but eliminates the need to deal with
network sockets
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NetFPGA tutorial - India: May 2008 129 S T A N F O R D U N I V E R S I T Y
Step 10 – Perfect the Router
If interested, go back to “Demo 2: Step 1” after synthesis is done and redo the steps with your own router.
To run your router:1- cd NF2/projects/tutorial_router/sw2- type “./tut_adv_router_gui.pl --use_bin
../../../bitfiles/tutorial_router.bit”
You can change the bandwidth and queue size settings to see how that effects the evolution of queue occupancy
Exerc
ise
2
Exerc
ise
2
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NetFPGA tutorial - India: May 2008 130 S T A N F O R D U N I V E R S I T Y
Drop 1 in N Packets
Objectives – Add counter and FSM to the code– Synthesize and test router
Execution– Open drop_nth_packet.v – Insert counter code – Synthesize– After synthesis, test the new system.
Exerc
ise
3
Exerc
ise
3
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NetFPGA tutorial - India: May 2008 131 S T A N F O R D U N I V E R S I T Y
New Reference Router Pipeline
One module added1. Drop Nth Packet
to drop every Nth packet from the reference router pipeline
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
Input ArbiterInput Arbiter
Output Port LookupOutput Port Lookup
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
Output QueuesOutput Queues
RateLimiter
RateLimiter
Event CaptureEvent Capture
Exerc
ise
3
Exerc
ise
3
Drop Nth PacketDrop Nth Packet
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NetFPGA tutorial - India: May 2008 132 S T A N F O R D U N I V E R S I T Y
Step 1 - Open the Source
We will modify the Verilogsource code to add acounter to the drop_nth_packet module
Open terminalType “xemacs
NF2/projects/tutorial_router/src/drop_nth_packet.v
Exerc
ise
3
Exerc
ise
3
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NetFPGA tutorial - India: May 2008 133 S T A N F O R D U N I V E R S I T Y
Step 2 - Add Counter to Module
Add Counter using the following signals:• counter
–16 bit output signal that you should be increment on each packet pulse
• rst_counter – reset signal (a pulse input)
• inc_counter – increment (a pulse input)
Search for insert counter (ctrl+s insert counter, Enter)
Insert Counter and Save (ctrl+x+s)
Exerc
ise
3
Exerc
ise
3
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NetFPGA tutorial - India: May 2008 134 S T A N F O R D U N I V E R S I T Y
Step 3 - Build the hardware
Start terminal, cd to “NF2/projects/tutorial_router/synth”
Run “make clean”
Start synthesis with “make”
Exerc
ise
3
Exerc
ise
3
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NetFPGA tutorial - India: May 2008 135 S T A N F O R D U N I V E R S I T Y
Using the NetFPGA in the Classroom
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NetFPGA tutorial - India: May 2008 136 S T A N F O R D U N I V E R S I T Y
NetFPGA in the Classroom
• Stanford University– EE109 “Build an Ethernet Switch”
• Undergraduate Course for all EE students• http://www.stanford.edu/class/ee109/
– CS344 “Building an Internet Router”• Quarter-Long Course • Taught Spr’05, Spr’07, Spr’08• http://cs344.stanford.edu
• Rice University– Nework Systems Architecture
• Spr’08• http://comp519.cs.rice.edu/
See: http://netfpga.org/teachers.html
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NetFPGA tutorial - India: May 2008 137 S T A N F O R D U N I V E R S I T Y
Components of NetFPGA Course
• Documentation– System Design– Implementation Plan
• Deliverables– Hardware Circuits– System Software – Milestones
• Testing– Proof of Correctness– Integrated Testing– Interoperabilty
• Post Mortem– Lessons Learned
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NetFPGA tutorial - India: May 2008 138 S T A N F O R D U N I V E R S I T Y
NetFPGA in the Classroom
• Stanford CS344: “Build an Internet Router”– Courseware available on-line– Students work in teams of three
• 1-2 software• 1-2 hardware
– Design and implement router in 8 weeks– Write software for CLI and PW-OSPF– Show interoperability with other groups – Add new features in remaining two weeks
• Firewall, NAT, DRR, Packet capture, Data generator, …
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NetFPGA tutorial - India: May 2008 139 S T A N F O R D U N I V E R S I T Y
softwarehardware
SwitchingForwarding
Table
Routing Table
Routing Protocols
Management& CLI
ExceptionProcessing
InteroperabilityBuild basic router Routing Protocol(PWOSPF)
Integrate with H/W
Emulatedh/w in VNS
Routing Table
Routing Protocols
Management& CLI
ExceptionProcessing
Emulatedh/w in VNS
Routing Table
Routing Protocols
Management& CLI
ExceptionProcessing
Emulatedh/w in VNS
Routing Table
Routing Protocols
Management& CLI
ExceptionProcessing
Command Line Interface
1 2 3 4 5 6
• Innovate and add!• Presentations• Judges
4-port non-learningswitch
4-port learningswitch
IPv4 routerforwarding path
Integrate with S/W Interoperability
SwitchingForwarding
Table
Learning Environment Modular design
Testing
CS344 Milestones
Final Project
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Typical NetFPGA Course PlanWeek Software Hardware Deliver
1 Verify Software Tools Verify CAD Tools Write Design Document
2 Build Software Router Build non-learning switch Run Software Router
3 Cmd. Line Interface Build learning switch Run basic Switch
4 Router Protocols Output Queues Run Learning Switch
5 Implement Protocol Forwarding path Interface SW & HW
6 Control Hardware Hardware Registers HW/SW Test
7 Interoperate Software & Hardware Router Submission
8 Plan new Advanced Feature Project Design Plan
9 Show new Advanced Feature Demonstartion
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CS344 Project Presentations
http://cs344.stanford.edu
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Network Systems Architecture at Rice
http://comp519.cs.rice.edu/
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Networked FPGAs in Research1. RCP: Congestion control
• New module for parsing and overwriting new packet• New software to calculate explicit rates
2. Packet Monitoring (ICSI)• Network Shunt
3. Deep Packet Inspection (FPX)• TCP/IP Flow Reconstruction• Regular Expression Matching• Bloom Filters
4. OpenFlow: Open Switch • New switch (“managed flow-table”) deployed
5. Buffer Sizing• Reduce buffer size and measure effect on network performance.• Need a way to set buffer size, and measure buffer occupancy
For details, see: http://netfpga.org/researchers.html
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CESNET / Liberouter• FPGA cards and accelerated network solutions : www.liberouter.org
– CESNET– Masaryk University– Brno University of Technology
• Hardware cards– Existing 1/10 Gbps family of COMBO cards – Upcoming 10/100 Gbps family of COMBOv2 cards
• NetCOPE platform for rapid development of network applications– PCI Express support, fast DMA transfers, pre-processed input packets– Extensive tool set for data streams manipulation– Cooperation with NetFPGA to create compatible application interface
• Network applications– NetFlow monitoring – collecting network statistics about flows– Payload checking – scanning content of packet payload– Hardware filtration and forwarding
• Commercial spin-off company INVEA-TECH : www.invea-tech.com
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Third Break
(while hardware compiles)
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Step 5 – Test your RouterYou can watch the number of received and sent packets to watch the
module drop every Nth packet. Ping a local machine (i.e. 192.168.7.1) and watch for missing pings.
To run your router:1- cd NF2/projects/tutorial_router/sw2- type “./tut_adv_router_gui.pl --use_bin ../../../bitfiles/tutorial_router.bit”
To set the value of N (which packet to drop)type “regwrite 0x2000704 0xN” – replace N with a number (such as 100)
To enable packet dropping: To disable packet dropping:type “regwrite 0x2000700 0x1” type “regwrite 0x2000700 0x0”
Exerc
ise
3
Exerc
ise
3
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Step 5 – Make measurements
• Determine iperf TCP throughput to neighbor’s server for each of several values of N – Similar to Demo 2, Step 8– Ping 192.168.x.2 (where x is your neighbor’s server)– TCP Throughput with:
• Drop circuit disabled– TCP Throughput = ________ Mbps
• Drop one in N = 1,000 packets– TCP Throughput = ________ Mbps
• Drop one in N = 100 packets– TCP Throughput = ________ Mbps
• Drop one in N = 10 packets– TCP Throughput = ________ Mbps
• Explain why TCP’s throughput is so low given that only a tiny fraction of packets are lost
Exerc
ise
3
Exerc
ise
3
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The NetFPGA.org Community
http://netfpga.org/
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Group Discussion• Your plans for using the NetFPGA
– Teaching– Research– Other
• Resources needed for your class– Source code– Courseware– Examples
• Your plans to contribute– Expertise – Capabilities– Collaboration Opportunities
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Survey
• How did you like this this tutorial?– What did you find useful?– What should be improved?– What should be removed?– What should be added?
• Can we post the video from this event?– If not, please let us know.
• Complete On-line survey– http://netfpga.org/tutorial_survey.html
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AcknowledgementsNetFPGA Team at Stanford University: May 2008
Jianying Luo, Jad Naous, Nick McKeown, Glen Gibb, Gerald Adam Covington, David Erickson, John W. Lockwood, Brandon Heller
Not Shown in photo: Paul Hartke, Neda Beheshti, Sara Bolouki
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Special thanks to:
Previous Tutorial Presented & Hosted By:
SIGMETRICS
Kuruvilla Varghese
Patrick Lysaght, Veena Kumar, Paul Hartke, Anna Acevedo
Xilinx University Program (XUP)
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Acknowledgements
• Support for the NetFPGA project has been provided by the following companies and institutions
Disclaimer: Any opinions, findings, conclusions, or recommendations expressed in this material do not necessarily reflect the views of the National Science Foundation or of any other sponsors supporting this project.
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Reference on the Web
NetFPGA homepage
http://NetFPGA.org
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Additional Slides
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NetFPGA Tutorial held at CEDT @ IISc on Thursday, May 15
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Demo 1 Configuration: CEDT IISc Lab
eth1 of Host PC
192.168.X.Y
5 6
4
10.1
192.168.18.* 192.168.21.*
8
3 2
0
1
7
9
Back of the classroom
Front of classroom
16.1
Key:
NetFPGARouter #
13.1
19.1 22.1 1.1
25.1 28.1
7.1 4.1
Stream traffic through multiple NetFPGA routers
in a ring topology
192.168.24.*
192.168.27.*
192.168.30.*
192.168.3.*
192.168.6.*192.168.9.*192.168.12.*
192.168.15.*
To stream mplayer video from server 4.1, type:./mp 192.168.4.1
Gray/GreenEthernet Cables
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Demo 2 Configuration: CEDT IISc Lab
Eth1: 192.168.X.1
Eth2: 192.168.Y.1
5 6
4
10.18.1
8
3 2
0
1
7
9
Back of the classroom
Front of classroom
16.114.1
Key:
NetFPGARouter #
13.111.1
19.117.1
22.120.1
1.129.1
25.123.1
28.126.1
7.15.1
4.12.1
Stream traffic through your NetFPGA router using neighbor’s eth2
interface
Blue Ethernet Cables