navigating pcb stackup layer assignments for optimized · pdf filearchive # sppdg archive...

Archive #

SPPDG Archive 45373 - 1

Navigating PCB Stackup Layer Assignments

for Optimized SI and PI Performance in High

Speed, High Power Designs

Chad Smutzer

Mayo Clinic

Special Purpose Processor Development Group (SPPDG)

[email protected]

20th IEEE Workshop on

Signal and Power Integrity (SPI)

Turin, Italy

May 8-11, 2016

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Agenda

• Background on High Performance Compute (HPC) systems

• Motivation for addressing Printed Circuit Board (PCB)

stackup layer assignments

• Conflicting Signal- and Power-Integrity (SI/PI) requirements

• SI- and PI-centric stackup constructions considered

• Analysis, modeling and measurement of layer transition via

structures for high-speed signal performance

• Power deliver impedance analysis results

• Design variations and impedance sensitivity

• Concluding remarks and guidance

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Agenda











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Background – High Performance Compute Systems

• Several high-power processing nodes systematically

arranged using high-speed interconnect to solve complex

computational problems

• Components often include: processors, memory, storage,

voltage regulation, passive devices and packaging

• Performance and capability can be limited by poor signal-

and/or power-integrity design

• Signaling rate dependent upon passive channel quality

• Voltage noise dependent upon power distribution design

• Mayo Clinic SPPDG’s role

• Complex analyses, cost-aware, risk-based trade-offs, etc.

• Mitigation techniques produce varying success

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Agenda











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Motivation – PCB Layer Assignment Considerations

• Assuming top-mounted processing devices, upper PCB layers in stack

construction often coveted for both SI and PI performance enhancement

• Short signal via transition length with manageable stub → improved

return loss

• Low-inductance path to power planes → increased effectiveness of

decoupling capacitors

• Highly-debated topic between SI and PI disciplines

• Technology trends pointing toward challenging signal and power

requirements in PCB technology

• 56 Gbps PAM4 (28 Gbaud), 28+ Gbps NRZ, processor core power

exceeding 100 W, power delivery impedance well below 1 mΩ

• How to prioritize top-most layers in PCB stack construction?

• A recent project elevated the need to study this trade-space

• HPC program in PCIe card form factor

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Motivation – Stackup Constructions

• Evaluation of trade-space through qualitative and quantitative analyses –

simulation, modeling, fabrication and test

• Cost-aware consideration and use of modern PCB technologies

• Reliable manufacturability is very important

• SI-centric and PI-centric stackup options

• Program-specific constraints required PCIe thickness compliance and

26 total layers leading to a two-laminate, “stepped-edge” PCB stackup

~ 120 mils total thickness

• Limited opportunity for routing layers with short via stubs

• Customized via geometries in each construction

• Consistent use of dielectric material system

• Isola Tachyon 100G for signal layers → targeted 56 Gbps NRZ*

• Isola Ultra EC 1 mil cores for P/G → low spreading inductance

• Singular difference is in the usage (net assignments) of the top 5 layers

*Industry signaling standards now appear to be settling on 28 Gbaud PAM4 for 56G throughput

COMPARISON OF SIGNAL- AND POWER-INTEGRITY-CENTRIC STACKUP CONSTRUCTS

SI-Centric Stackup Option PI-Centric Stackup Option

L1 – Attach

L2 – Ground

L3 – Signal

L4 – Ground L5 – Power

L6 - Ground

Pre-preg

Core

Pre-preg

Core

Pre-preg

Pre-preg

Core

Pre-preg

Core

Pre-preg

L26 - Attach

L1 – Attach

L2 – PowerL3 – Ground

L4 – Signal

L5 – Ground

L6 - Power

L26 - Attach

2.3 3.34

0.6 4.0

5.24

1.00

4.76

0.6

1.2 1.2

1.2

2.3 3.34

0.6 4.0

5.24

1.00

4.76

0.6

1.2 1.2

1.2

62.0

12

2

60

34.5

62.0

34.5

SI-Centric Via Constructs PI-Centric Via Constructs

L1 – Attach

L2 – Ground

L3 – Signal

L4 – Ground L5 – Power

L6 - Ground

L26 - Attach

L1 – Attach

L2 – PowerL3 – Ground

L4 – Signal

L5 – Ground

L6 - Power

L26 - Attach

46

(S

tub

)

Ø 11

Ø 8

**

Ø 1

0**

Ø 8

**

Ø 1

0**

Ø 8 Ø 6

No

Stub

Ø 14

Ø 6

No Stub

Top Sub-Laminate

Bottom Sub-Laminate

Top Sub-Laminate

Bottom Sub-Laminate

* All dimensions in mils

Ø 6

Ø 6

(a) (b)

(c) (d)

** Mechanically-drilled thru vias

Top Sub-Laminate

Bottom Sub-Laminate

Top Sub-Laminate

Bottom Sub-Laminate

NOV_24 / 2015 / CMS / 45145

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Agenda











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Via Modeling – Signal Route Implementations (1)

• Stub management is the key to designing high-performing

signal vias – optimal return loss

• Back-drilling is typical/common stub management technique

• Not considered here due to complications with multi-

laminate construction and counter-productive effects on

power delivery plane impedance from perforations

• SI-Centric stackup with desired routing on Layer 3 and stub

less than 10 mils

• L1-L3 laser drilled via – practical implementation, modeled

in 3D electromagnetic (EM) simulator and measured in

fabricated test board

• L1-L12 mechanically drilled via – intolerable stub length

(~50 mils), not considered viable for target data rates

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Via Modeling – Signal Route Implementations (2)

• PI-Centric stackup with desired routing on Layer 4 and stub

less than 10 mils

• L1-L4 laser drilled via – not practical in our application

• Excessive diameter to meet preferred 1:1 aspect ratio,

exceeding typical BGA pad size – not considered further

• L1-L2-L3-L4 High Density Interconnect (HDI) stacked via –

modeled in 3D EM simulator

• Costly, emerging technology with unknown reliability

• Also possible using more sub-laminates, longer fab time

• L1-L12 mechanically drilled via – modeled in 3D EM

simulator

• Likely intolerable stub length (~45 mils), but included

here as low-cost alternative to HDI

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Via Modeling – Passive Test Vehicle

• Design, fabricated and measured 140 test structures in Passive Test

Vehicle (PTV) utilizing SI-centric stackup construction

• Implemented and measured L1-L3 laser micro via

• Considerably more detail on PTV performance documented in paper

reference [2] – “56 Gbps PCB Design Strategies for Clean, Low-Skew

Channels”, DesignCon 2016

Archive #


Via Design – Performance Results and Implications • SI-Centric stackup, L1-L3 laser drilled via

• Measurement and model are in close agreement, especially in critical

frequency and magnitude ranges

• Very high-performing via construct with bandwidth expected to easily satisfy 28

Gbps signaling and possibly up to 56 Gbps NRZ signaling

• PI-Centric stackup, L1-L2-L3-L4 HDI stacked laser drilled via

• Excellent performance, very similar to L1-L3 via in SI-centric stackup with

bandwidth possibly up to 56 Gbps NRZ signaling

• PI-Centric stackup, L1-L12 mechanically drilled via

• Modeling results show this via is not viable for data rates exceeding ~18 Gbps

Bandwidth

(GHz)

BRL (dB)*

Configuration At -10dB BRL 10

GHz

14

GHz

28

GHz

SI Centric Stackup

A: L3 Laser Via – Meas. 29.5 -22 -19 -11

B: L3 Laser Via – Sim. 27 -20.5 -18 -9

PI Centric Stackup

C: L4 HDI Via – Sim. 28 -16 -15 -10

D: L4 Via With Stub – Sim. 9 -9.5 -8 -3

*Broadband Return Loss (BRL) defined in paper reference [4]

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Agenda











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Power Delivery – HPC Design Goals

• Low-impedance, passive power distribution network (PDN) is key to

high-performing, high-power processor in typical HPC application

• Frequency Domain Target Impedance Method (FDTIM) has been

preeminent PDN design methodology for many years – paper

references [1] and [2]

• Increasing peak and transient core supply current requirements

trending toward PCB PDN target impedances well below 500 µΩ

• PCB structures (planes, vias, decoupling capacitors, etc.) require

critical design attention to offer low inductance and low resistance

current delivery path from VRM and capacitors to BGA pins

• Via length proportional to inductance → upper layers coveted for

core voltage power delivery

• Decoupling capacitor effectiveness and resonant frequency dictated

by inductance to planes

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Power Delivery – Evaluation Platform and Process

• Developed a generic PCB platform typical of HPC applications to

evaluate impact of stackup construction on PDN impedance

• Topside attach 1 mm pitch, 45mm x 45mm BGA processor and VRM

footprint

• Reasonable quantity of decoupling capacitors symmetrically flanking

topside periphery of load and within pinfield on bottom side of PCB

• Implemented in both SI- and PI-centric stackup constructs

• First power plane = Layer 5 in SI-centric, Layer 2 in PI-centric

• An optimistic representation (lacking signal routing, ideal component

placement, etc.) satisfactory for comparative study of plane location

effect on PDN impedance

• Multiple configurations were simulated using commercial field solver tool

• Analyzed with and without presence of decoupling capacitors

• Extracted 2-port S-parameters and calculated complex self-impedance

versus frequency Z(f)

Top Side West Capacitors

Size Qty. C ESR ESL

0201 40 0.1uF 37mΩ 146pH

0402 25 0.47uF 22mΩ 319pH

0603 10 4.7uF 7mΩ 329pH

0805 5 22uF 4mΩ 390pH

Top Side East Capacitors

Size Qty. C ESR ESL

0201 40 0.1uF 37mΩ 146pH

0402 25 0.47uF 22mΩ 319pH

0603 10 4.7uF 7mΩ 329pH

0805 5 22uF 4mΩ 390pH

Bottom Side Capacitors

Size Qty. C ESR ESL

0201 40 0.1uF 37mΩ 146pH

VRM BGA

45mm x 45mm Load Processor BGA

POWER-INTEGRITY-CENTRIC STACKUP PRINTED CIRCUIT BOARD TEST VEHICLE

( Board Contains Equivalent Top Side Decoupling Capacitors Flanking a

45 mm x 45 mm Processor Load )

NOV_24 / 2015 / CMS / 45147

Imp

ed

an

ce

(O

hm

s)

Frequency (Hz)

POWER DELIVERY IMPEDANCE COMPARISON FOR SIGNAL- AND POWER-INTEGRITY-CENTRIC STACKUP DESIGN

PI Centric: Top Side Capacitors

PI Centric: No Capacitors

SI Centric: Top Side Decoupling

SI Centric: No Capacitors

10-1

10-2

10-3

10-4

104 105 106 107 108

NOV_24 / 2015 / CMS / 45148

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Power Delivery – Metrics and Performance Summary

• For comparative purposes, extracted three relevant PDN performance

metrics [1] from the Z(f) curves for four baseline conditions

• Metrics: Frequency when impedance exceeds 1 mOhm, low frequency

(DC) impedance, effective PCB inductance calculated above 50 MHz

• Baseline conditions: SI- and PI-centric stackups, with and without

topside capacitors (no bottom side caps populated)

• As predicted, notable improvements observed in PI-centric stackup

• E.g., PI-centric design pushes 1 mΩ frequency crossing up by 60%

• Approaching frequency region where die/package can compensate

West Caps East Caps 1mΩ Frequency

Crossing (MHz)

Low Frequency

Impedance (Ω)

Effective

Inductance (pH)

SI Centric Stackup – No Backside Decoupling

1.2 728 µ 59

3.0 728 µ 24

PI Centric Stackup – No Backside Decoupling

3.0 697 µ 32

4.8 697 µ 19

Archive #


Power Delivery – Design Variations and Alternatives

• Variation in via technology available in each stackup, as well as surface

metal usage, can enable many alternative design options that can be

exploited for additional performance benefit (or avoided if detrimental)

• Use of only laser micro vias (as available) for decoupling capacitors

• Enhances signal routing density on layers below power plane

• Use of surface metal for power plane flood fill

• Typically limited due to microstrip routing and assembly features

• Offers additional/parallel current path and reduced impedance

• Addition of backside decoupling capacitors in thick (120 mil) board

• Higher via inductance alters effectiveness

• Larger drill diameter (aspect ratio) creates larger plane perforations

• Addition of inner layer power net assignments

• Requires upper laminate through vias disturbing inner layer routing

• Offers additional/parallel current path and reduced impedance

CROSS-SECTIONAL VIEW OF HIGH-FREQUENCY CURRENT PATHS IN STACKUP

DESIGNS WITH TOP AND BOTTOM SIDE DECOUPLING CAPACITORS

SI-Centric Stackup Topside Decoupling

LOADWEST

CAPS

Top

Ground

Signal

GroundPower

Ground

EAST

CAPSX X

Attach

PI-Centric Stackup Topside Decoupling

LOADWEST

CAPS

Top

Power

Ground

Signal

Ground

Power

EAST

CAPSX X

Attach

PI-Centric Stackup Addition of Backside Decoupling

LOADWEST

CAPSTop

Power

Ground

Signal

Ground

Power

EAST

CAPSX X

Bottom

CAPS

SI-Centric Stackup Addition of Backside Decoupling

LOADWEST

CAPSTop

Ground

Signal

GroundPower

Ground

EAST

CAPSX X

Bottom

CAPS

Ø 8

Ø 6

Ø 8

Ø 6

Ø 6

Ø 10

Ø 8

Ø 6

Ø 10

Ø 8


(a) (b)

(c) (d)NOV_24 / 2015 / CMS / 45146

Archive #


Power Delivery – Design Variation Analysis Results • West caps = 6 mil micro-via

• SI-Centric requires surface metal

• East caps = 8 mil through hole via

• More useful for PDN impedance,

but will impact signal routing

• Backside capacitors were

surprisingly helpful despite the high-

inductance vias

• Using all available options in PI-

Centric stackup, can keep

impedance below 1 mΩ to 19 MHz;

~4x better than comparable

configuration in SI-centric

• As expected, low frequency

impedance most impacted by

number of power layers

L1

Metal

West

Caps

East

Caps

Bottom

Caps

L6

Metal

1mΩ Freq.

(MHz)

Low Freq.

Z (Ω)

Eff. L (pH)

SI Centric Stackup – No Backside Decoupling - Fig. 5 (a)

Pwr Gnd 3.2 366 µ 37

Pwr Gnd 4.0 366 µ 30

Pwr Gnd 4.8 366 µ 19

Gnd 1.2 728 µ 59

Gnd 3.0 728 µ 24

SI Centric Stackup – With Backside Decoupling - Fig. 5 (b)

Pwr Gnd 3.2 331 µ 37

Pwr Gnd 4.0 331 µ 30

Pwr Gnd 5.2 331 µ 18

Pwr Gnd 2.9* 331 µ 18

Pwr Gnd 5.5 331 µ 17

Pwr Gnd 5.0* 331 µ 12

PI Centric Stackup – No Backside Decoupling - Fig. 5 (c)

Gnd Pwr 5.0 406 µ 24

Gnd Pwr 6.6 406 µ 16

Gnd Pwr 7.0 406 µ 12

Pwr 4.8 436 µ 24

Pwr 6.0 436 µ 17

Pwr 6.6 436 µ 13

Gnd 3.0 697 µ 32

Gnd 4.8 697 µ 19

PI Centric Stackup – With Backside Decoupling - Fig. 5 (d)

Gnd Pwr 5.0 369 µ 24

Gnd Pwr 6.6 369 µ 16

Gnd Pwr 6.9 369 µ 12

Gnd Pwr 4.6* 369 µ 15

Gnd Pwr 12.0 375 µ 10

Gnd Pwr 19.0 369 µ 8

*Backside caps resonated at freq. > 10 MHz causing anti-resonance resulting in premature violation of 1 mΩ threshold

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Agenda











Archive #


Concluding Remarks (1)

• Stackup design must occur early in PCB design process

• Considerations include: materials, routing density, signal

bandwidth, BGA pinfield breakout, available via drill

technology, PDN impedance requirement, reliability, risk

assessment, fabricator capability, etc.

• Simultaneously satisfying advancing SI and PI

requirements in a singular stackup is the challenge

• Trade-space analyses useful to reduce cost or risk

• Advanced technology often warranted to mitigate layout

challenges

Archive #


Concluding Remarks (2)

• Consult with fabricators to understand risks/limits of their available PCB

technology offerings

• When stubless signal vias can be economically and reliably

implemented using HDI or multi-laminate construction

• Upper-most PCB layers can be prioritized for optimal, low-

impedance power delivery (PI-centric)

• Cost and manufacturing risk factors apply

• When limited to traditional via and laminate construction

• Upper-most layers, accessible with laser-drill vias, can be prioritized

for signal routing and offer optimal signal integrity performance (SI-

centric)

• Excessive via stub length when signal layers are lower in stackup

may produce inadequate signal bandwidth

• Power requirements accommodated through more or better

capacitor technology and/or additional inner planes

Archive #


THANK YOU!

Navigating PCB Stackup Layer Assignments for Optimized SI and PI

Performance in High Speed, High Power Designs

Chad Smutzer

[email protected]

20th IEEE Workshop on

Signal and Power Integrity (SPI)

May 11, 2016

Archive #


Backup Material

Card Edge Connector

(62 mils thick)

PCIe Card Form Factor - Top View

General Routing/Device

Placement Region

Not Thickness-Constrained

PCIe Card Form Factor –

Side View

62 mils 58 mils

PCIe Card Form Factor –

Side View With Vias

Through-hole via

electrically connecting

top and bottom laminate

HIGH SPEED DIFFERENTIAL TEST VEHICLE VISUALIZATION OF STEPPED-EDGE

PRINTED CIRCUIT BOARD STACKUP

Top laminate

mechanically

drilled via

Bottom laminate

mechanically

drilled via

Laser vias to

outer sub-

laminate layers

MAY_20 / 2015 / CMS / 44908

Name:

Drill Type:

Drill Diameter:

Inner Pad Diameter:

Top Pad Diameter:

Bottom Pad Diameter:

Antipad Style:

Antipad Diameter:

L1 to L3 - DifferentialBV279L1-3_DP_A

Laser Micro

0.279 (11 mil)

0.454 (17.87 mil)

0.454 (17.87 mil)

NA

Oblong

1.711 x 0.711 (67.37 x 28 mil)

HIGH SPEED DIFFERENTIAL TEST VEHICLE NOMINAL VIA DESIGN PARAMETERS

P

N

Name:

Drill Type:

Drill Diameter:

Inner Pad Diameter:

Top Pad Diameter:


Antipad Style:

Antipad Diameter:


Top Lam Thru

0.200 (7.87 mil)

0.454 (17.87 mil)

0.454 (17.87 mil)

0.251 (9.87 mil)

Oblong

1.632 x 0.632 (64.24 x 24.87 mil)

P

N


Bot Lam Thru

0.200 (7.87 mil)

0.454 (17.87 mil)

0.251 (9.87 mil)

0.454 (17.87 mil)

Oblong

1.632 x 0.632 (64.24 x 24.87 mil)

P

N


Laser Micro

0.279 (11 mil)

0.454 (17.87 mil)

NA

0.454 (17.87 mil)

Oblong

1.711 x 0.711 (67.37 x 28 mil)

P

N


Laser Micro

0.279 (11 mil)

0.454 (17.87 mil)

0.454 (17.87 mil)

NA

Oblong

1.711 x 0.711 (67.37 x 28 mil)

P

N


Laser Micro

0.279 (11 mil)

0.454 (17.87 mil)

NA

0.454 (17.87 mil)

Oblong

1.711 x 0.711 (67.37 x 28 mil)

P

N

Name:

Drill Type:

Drill Diameter:

Inner Pad Diameter:

Top Pad Diameter:


Antipad Style:

Antipad Diameter:

L1 to L3 - SE, GND

BV279L1-3_SE_A

Laser Micro

0.279 (11 mil)

0.454 (17.87 mil)

0.454 (17.87 mil)

NA

Circle

0.711 (28 mil)

S

G

L10 to L12 - SE, GND

BV279L10-12_SE_A

Laser Micro

0.279 (11 mil)

0.454 (17.87 mil)

NA

0.454 (17.87 mil)

Circle

0.711 (28 mil)

S

G


BV279L13-15_SE_A

Laser Micro

0.279 (11 mil)

0.454 (17.87 mil)

0.454 (17.87 mil)

NA

Circle

0.711 (28 mil)

S

G


BV279L24-26_SE_A

Laser Micro

0.279 (11 mil)

0.454 (17.87 mil)

NA

0.454 (17.87 mil)

Circle

0.711 (28 mil)

S

G

Name:

Drill Type:

Drill Diameter:

Inner Pad Diameter:

Top Pad Diameter:


Antipad Style:

Antipad Diameter:

L1 to L12 – SE, GNDBV200L1-12_SE_A

Top Lam Thru

0.200 (7.87 mil)

0.454 (17.87 mil)

0.454 (17.87 mil)

0.251 (9.87 mil)

Circle

0.632 (24.87 mil)

S

G

L13 to L26 – SE, GNDBV200L13-26_SE_A

Bot Lam Thru

0.200 (7.87 mil)

0.454 (17.87 mil)

0.251 (9.87 mil)

0.454 (17.87 mil)

Circle

0.632 (24.87 mil)

S

G

L1 to L26 – SE, GNDV250L1-26_SE_A

Thru

0.250 (9.84 mil)

0.504 (19.84 mil)

0.504 (19.84 mil)

0.301 (11.84 mil)

Circle

0.682 (26.84 mil)

S

G

L1 to L26 - DifferentialV250L1-26_DP_A

Thru

0.250 (9.84 mil)

0.504 (19.84 mil)

0.504 (19.84 mil)

0.301 (11.84 mil)

Oblong

1.682 x 0.682 (66.21 x 26.84 mil)

P

N

NOTE: Launch structure, BGA

pad size will supersede Top

Pad Diameter specified in each

nominal via.

MAY_20 / 2015 / CMS / 44906

Option: Layer - Usage Class Drill Ø Pad Ø Void Ø

SI Centric Stackup

A: L3 - Signal Laser Blind 11 18 28

B: L5/6 - Pwr/Gnd Mech. Thru 8 18 25

C: L2 – Gnd Laser Blind 6 13 23

PI Centric Stackup

D: L2 – Pwr Laser Blind 6 13 23

E: L3 – Gnd Laser Blind 8 18 25

F: L4 – Signal HDI Stack 6 13 23

G: L4 - Signal (Unused) Laser Blind 14 21 31

H: L4/5/6 - Sig/Gnd/Pwr Mech. Thru 8 18 25

Table 1. Via Design Geometries


Case

L1

Metal

West

Caps

East

Caps

Bottom

Caps

L6

Metal

1mΩ

Freq.

(MHz)

Low

Freq.

Z (Ω)

Eff.

L

(pH)

SI Centric Stackup – No Backside Decoupling - Fig. 5 (a)

A Pwr Gnd 3.2 366 µ 37

B Pwr Gnd 4.0 366 µ 30

C Pwr Gnd 4.8 366 µ 19

D Gnd 1.2 728 µ 59

E Gnd 3.0 728 µ 24

SI Centric Stackup – With Backside Decoupling - Fig. 5 (b)

F Pwr Gnd 3.2 331 µ 37

G Pwr Gnd 4.0 331 µ 30

H Pwr Gnd 5.2 331 µ 18

I Pwr Gnd 2.9* 331 µ 18

J Pwr Gnd 5.5 331 µ 17

K Pwr Gnd 5.0* 331 µ 12

PI Centric Stackup – No Backside Decoupling - Fig. 5 (c)

L Gnd Pwr 5.0 406 µ 24

M Gnd Pwr 6.6 406 µ 16

N Gnd Pwr 7.0 406 µ 12

O Pwr 4.8 436 µ 24

P Pwr 6.0 436 µ 17

Q Pwr 6.6 436 µ 13

R Gnd 3.0 697 µ 32

S Gnd 4.8 697 µ 19

PI Centric Stackup – With Backside Decoupling - Fig. 5 (d)

T Gnd Pwr 5.0 369 µ 24

U Gnd Pwr 6.6 369 µ 16

V Gnd Pwr 6.9 369 µ 12

W Gnd Pwr 4.6* 369 µ 15

X Gnd Pwr 12.0 375 µ 10

Y Gnd Pwr 19.0 369 µ 8

Table 3. Power Delivery Simulation Results Summary

* The backside capacitors resonated at a frequency > 10 MHz causing an anti-

resonance resulting in a premature violation of the 1 mΩ threshold.

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