narrowing)the)gap)between) packaging)and)system meptec ...meptec.org/resources/4 - li.pdf ·...
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Narrowing the Gap between Packaging and System
Meptec Symposium 2015ASE (US) Inc
Ou LiNov 10th, 2015
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Outline
£ Industry Dynamics £ The Need for System Integrators£ IC/Pkg/System Collaboration£ Summary
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Market Trend
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• IOT, Mobile leading the growth. Internet of Everything• We are in connected world - Big Data, Cloud in future• Diverging Innovation – Market, Application, Technology• Increasing Competition- Performance, Cost, Time to market
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Industry Dynamics
£ Vertical Integration • Hardware OEM establish IC and supply chain ownership• Content and Service provider develop hardware platforms• Moore’s Law slow down. Fab consolidation on advanced node• System company looking for platform Integrators• SiP/SiM and heterogeneous Integration for broad applications
£ Opportunities• Integration solution being key differentiator• OSAT in unique position to realize platform integration• Chip-‐Packaging-‐System Collaboration• Joint Development and Partnership
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Re-defining the Supply Chain – The need for Integrators
5
IC Packaging and Testing SiP/ SiM Development System Integration
Wafer Fab
Assembly TestingIC SubstratePackage Design
Circuit Design
Layout Design
Module ASM
BOM Module test
Semiconductor System OEM Software/Service
User
ASE GroupIC/Pkg/SiP/SiMsolution
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Chip/Pkg/System collaboration
£ System Architecture• Package platform
£ Platform design support • Co-‐Design, Co-‐Simulation
£ Enabling Packaging Technologies
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Platform Architecture - MCM or SiP Module
£ Silicon centric, or Package centric module£ Encapsulation: Exposed die, Selective/irregular mold, Double side mold £ EMI Shielding: Metal lid, Conformal, Compartment shielding£ High density SMT, Embedded technology, Antenna on Package£ Applications: WLAN/WWAN, FEM, BT, PMIC, Transceiver, Mobile TV, etc
MCM
SiP
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£ Thin wafer, double side handling£ Fine pitch bumping and RDL£ TSV Technology£ CoW + Chip Last assembly£ Multiple test insertion on FT and SLT £ Large Pkg warpage control
Platform Architecture – 2.5D
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• Interconnect and Packaging solution to enable platform architecture
£ 2.5D Si interposer HVM for GPU+HBM£ GPU: 1.05Ghz, HBM 1.0Ghz, BW 512 GB/S£ Pkg Size 55x55 mm2
£ Interposer: TSV 11um, die size 36x28 mm2
£ Microbump pitch: 45 um
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Platform Architecture – Wafer level FO
£ Advantage•High density, Form Factor• Substrate-‐less• Short connections between chip and passive
£ Character and Property• Chip first, or Chip last• Embedded chip and passives w/ molding compound• Fine pitch assembly and SMT process
£ Application•Mid-‐ end : BB, RF, PMIC, MEMs•High-‐end : Networking, GPU, APU
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Chip/Pkg/System collaboration
£ System Architecture• Package platform
£ Platform design support • Co-‐Design, Co-‐Simulation
£ Enabling Packaging Technologies
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Package Design – Conventional Model
-Chip I/O and PCB ball map fixed before pkg design start -Pkg not optimized due to limitation -Pkg may not catch the wafer out schedule -Product Performance suffered
IC Design House
OSATSystem PCB
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Co-‐Design, Co-‐ Simulation
-IC/Pkg/PCB early engagement in planning -Layout iterations with SI/PI analysis -Pkg Design Optimized-Schedule in Sync -Product performance met
IC DesignHouse
OSATSystem PCB
Ø Optimized Performance. Cycle time reduction.
Ø Cost reduction. Time to market.
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Design Activities
£ Design EDA • Substrate Layout
£ Simulation• RLC extraction• SI and PI analysis
£ Electrical Characterization• Crosstalk/jitter/skew analysis• Impedance measurement• Eye-diagram measurement• Power integrity measurement
£ Thermal and Mechanical Analysis• Thermal Simulation and characterization
• Stress and Warpage simulation and characterization
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Co-design - IC/PKG/System
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n Co-‐works with customer to solve the dynamic DDR power issue and provide the solution
ü Chip/PKG/System Co-‐simulationü Optimize package design and the decoupling cap on the package
DDR Power
C1
C2
Package Package on PCB
DDR
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n Based on impedance file and current profile to optimize PKG decoupling cap, meet customer ±5% spec finally.
— Original design— Optimize design
0.00 100.00 200.00 300.00 400.00 500.00Time [ns]
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
V(V_die) [V]
Dynamic_IRXY Plot 1 ANSOFT
m1
m2
Curve InfoV(V_die)
NexximTransient
Name X Ym1 86.5687 1.9552m2 89.9993 1.7003
0.00 100.00 200.00 300.00 400.00 500.00Time [ns]
1.74
1.76
1.78
1.80
1.82
1.84
1.86
1.88
1.89
V(V_die) [V]
Dynamic_IR_cap_testXY Plot 1 ANSOFT
m1
m2
Curve InfoV(V_die)
NexximTransient
Name X Ym1 73.2424 1.8765m2 87.9382 1.7481
— Original: P2P = 254mV
— Optimize: P2P = 128mV
Reduce 50%
Co-Design – IC/PKG/System
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n Package information : FC TFBGA 4L 17x17 mmn Application : Tabletn DDR3 data rate : 1066 Mbps
Co-design – IC/PKG/System
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4L PKG model PKG-‐on-‐PCB full model
AP Chip
DRAM1
DRAM2
0.00 25.00 50.00 75.00 100.00 125.00 150.00 175.00 200.00Time [ns]
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
V(asic1v5
) [V]
Circuit1XY Plot 1Curve Info max min pk2pk
V(asic1v5)HSPICETransient 1.5538 1.4157 0.1381P2P = 138mV
DQS jitter : 34.9 ps
DQ skew + jitter : 112.3 ps
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n Cost down version : FC TFBGA 2L 17x17 mmn The electrical performance for 2L substrate is similar with using 4L substraten Optimize design on SI and PI
Co-design – IC/PKG/System
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2L PKG model 4L PKG model
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Simulation to Measurement Correlation
WLCSP Diplexer on substrateInsertion loss
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Package Level High Frequency Measurement - SerDes
Bottom Side
Top Side
Material Property:The S21 and SDD21 simulation results have good correlation with measurement for both magnitude and phase.
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System Level High Frequency Measurement - SerDes
System measurement environment for package on print circuit board (PCB) sample
SDD21 – Magnitude Comparison for PKGonPCB
• A simplified model of signal line on system board with package simulation model has a good prediction.
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SiP Module Analysis
• Low Band/high Band channel analysis and optimization for WiFi SiP module on board to meet the electrical specification
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SiP Module EMI Analysis
• The higher EMI radiation is on bottom side of pkg by using conformal shielding. • Using near field scanner to find the location of main EMI radiation and root cause, then
re-‐design it to meet the specification.
n Conformal shielding applied on QFN:
n WiFi MIMO SiP Module:
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Chip/Pkg/System collaboration
£ System Architecture• Package platform
£ Platform design support • Co-‐Design, Co-‐Simulation
£ Characterization• Simulation to Measurement Correlation
£ Enabling Packaging Technologies
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Enabling Technologies for System in Package
Shielding-‐Board or package level
-‐Compartmental
Antenna-‐Package integration for
2.4G/5G/60GHz
Passives / IPD -‐Integrated Passive
Devices
Wafer Bumping / WLP-‐Leadfree / Cu Pillar-‐Bare die package
Die / Pkg Stacking-‐Die thinning
-‐Die interconnect
SMT -‐Passives
-‐Components-‐Connectors
Embedded Technology-‐Passive component
-‐Active device
Molding-‐MUF
-‐Exposed die-‐Double side
Interconnection-‐Flip chip (MR & TCB)
-‐Wire Bond
Mechanical Assy-‐Laser welding-‐Flex bending
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ASE Confidential
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Summary
£ IOT, Big data, Cloud computing define our future world
£ System integration and miniaturization continue to grow for performance, power, form factor, cost and time to market
£ Vertical integration from system house for SiP/SiM solution
£ OSAT is in best position as value added “Integrators”
£ IC/Pkg/System collaboration are key for product success
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Thank You
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