nanoscale memory cell based on a nanoelectromechanical switched capacitor eecs min hee cho
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Nanoscale memory cell based ona nanoelectromechanical switched
capacitor
EECS
Min Hee Cho
OutlineI Introduction• Agenda• DRAM & Key idea• Capacitor type• Carbon Nanotube
II Mechanical switched capacitor• Fabrication• SEM image
• Operation• Switching characteristics
J. E. Jang, et al. nature nanotechnology 2008 (Samsung Advanced Institute of Technology & U of Cambridge )J. E. Jang, et al. APPLIED PHYSICS LETTERS 2008
III Low voltage drive•Low Gate Voltage•Fabrication•SEM image
IV Summary•Summary : Merits•Summary : remaining obstacles
V References/ Q&A
OutlineI Introduction• Agenda• DRAM & Key idea• Capacitor structure• Carbon Nanotube
II Mechanical switched capacitor• Fabrication• SEM image
• Operation• Switching characteristics
III Low voltage drive•Low Gate Voltage•Fabrication•SEM image
IV Summary•Summary : Merits•Summary : remaining obstacles
V References/ Q&A
Agenda
Conventional DRAM New DRAM
Fabrication Top-Down process Bottom-Up Process (CNT)
Operation Field Effect Transistor
+ Capacitor
Electromechanical switch
+ Capacitor
Nanoscale memory cell = DRAM with Carbon nanotube
DRAM & Key ideaSchematic drawing of original designs of DRAM
patented in 1968.
* Development of DRAM : Cell size is smaller and smaller TR : On/Off ratio ↓(due to Short channel effect) Cap : Area of capacitor is also reduced ( Capacitor should be larger to improve performance)
* Solution TR : Mechanical switched TR Cap: Vertical structure ( increase area of capacitor ) or High K
Gate
Drain Source
Capacitor
Trench type
Capacitor structure
Cylinder type like “HAT”
Dielectric:small area
Gate
Drain Source
Capacitor
Source Drain
Gate
DRAM has several limits as shrinkage* Transistor - low Subthreshold swing (low On/Off ratio) - short channel effect (Off leakage)
New challenge for DRAM with CNT* Transistor - Use Electromechanical property not Field effect On/Off ratio ↑ - Smaller cell area : due to the vertical structure* Additionally, they can use existing silicon technology
Area also reduced
Conventional DRAM structure
New DRAM structureNew DRAM structure
Carbon Nanotube (CNT)
Properties
SingleWalledCarbonNanotube(SWNT)
Multi-Walled Carbon Nanotube
(MWNT)
Comparison
Diameter (nm) 1.2~3 5~100Hair(70~100)×103
Tension (GPa) ~45 <50~300Stainless steel :
0.65~1)
Density(g/cc) 1.33~1.40 - Al ~2.7
Electric resistance(Ω·m)
10×10-6 5.1×10-8 Cu 1.7×10-8
Current density(A/m2)
~109 - Cu 106
Thermal conductivity(W/m·K)
~6000 ~3000Diamond : 2000~40000,Cu: 393.7
CNT formation
They use CNT as electromechanical materials rather than semiconductor material
OutlineI Introduction• Agenda• DRAM & Key idea• Capacitor type• Carbon Nanotube
II Mechanical switched capacitor• Fabrication• SEM image
• Operation• Switching characteristics
III Low voltage drive•Low Gate Voltage•Fabrication•SEM image
IV Summary•Summary : Merits•Summary : remaining obstacles
V References/ Q&A
Fabrication 0. Make Nb catalyst dot on Substrate
I. C2H2 &NH3 gas 600~650oC by PECVD : CNT
II. Si3N4 (dielectric & insulator) by PECVD
III. Cr by sputtering : upper electrode
IV. Si3N4 at Drain removed by wet etching Si3N4 remaining at bottom of MWCNT strengthen the interface enhance working reliability
CNT formation
SEM image
* Total cell: 40,000 ea* MWCNT success rate : 95%* Final cell success rate : 50% (failure due to mainly M/A in litho)
CNT diameter : 70nmGap between CNT : 100nmLength : 3.5umSi3N4 thickness : 40nmFor single capacitance: 1.05fF
SEM images
OutlineI Introduction• Agenda• DRAM & Key idea• Capacitor type• Carbon Nanotube
II Mechanical switched capacitor• Fabrication• SEM image
• Operation• Switching characteristics
III Low voltage drive•Low Gate Voltage•Fabrication•SEM image
IV Summary•Summary : Merits•Summary : remaining obstacles
V References/ Q&A
Write
Operation
The mutual repulsion between the positive charges on the capacitor and the nanotube in cell 1 prevents the nanotube from making contact with the capacitor, so no current flows, unlike the situation in cell 2, where the nanotube does make contactwith the cell.
Read
BL of Cell 1 and apply 0.1V gate voltage to the 15V CNT of Cell 1 begins to bend contacts charges flow from CNT(BL) to capacitor
Potential distribution
* When gate voltage is higher than Vt, Transistor turns on * Vd increase Vt decreases due to electrostatic force
Threshold gate voltage (Vt)
OFF
ON
Very High gate voltage: Usually DRAM operates at ~1.3V (or less than 2.5V)
Switching characteristics
OutlineI Introduction• Agenda• DRAM & Key idea• Capacitor type• Carbon Nanotube
II Mechanical switched capacitor• Fabrication• SEM image
• Operation• Switching characteristics
III Low voltage drive•Low Gate Voltage•Fabrication•SEM image
IV Summary•Summary : Merits•Summary : remaining obstacles
V References/ Q&A
J. E. Jang, et al. APPLIED PHYSICS LETTERS 2008
Low Gate Voltage
Too high operating voltage (15~20V)
APPLIED PHYSICS LETTERS 93, 113105 2008
∵ The simple planar gate structure imparts a very small electrostatic force to the drain electrostatic force ∝ 1/d2
Need high voltage
Vertical gate structure
In this workThey make vertical gateand tie it with drain
14~15V 4~5 V4~5 V
PolyMethyl MethAcrylate (PMMA) : thermoplastic and transparent plastic.
PMMA coating after the CNT growth process. 30 nm SiNx deposition by PECVD
E-beam lithography with substrate tilting
Cr layer deposition
lift-off process (Cr on PMMA removed)
400 nm PMMA coating and ashing process to remove the Thin PMMA on the vertical CNT and gate structure
Fabrication
1> Operating Gate voltage can be reduced 2> Area also reduced
SEM images
OutlineI Introduction• Agenda• DRAM Memory• Basic Operation• Capacitor type• Carbon Nanotube
II Mechanical switched capacitor• Fabrication• SEM image
• Operation• Switching characteristics
III Low voltage drive•Low Gate Voltage•Fabrication•SEM image
IV Summary•Summary : Merits•Summary : remaining obstacles
V References/ Q&A
Summary : Merits
• Excellent ‘ON–OFF’ ratio – Due to the mechanical switching approach
No ultra-shallow n- or p-type junctions No thin-gate dielectrics
• Compatible with existing silicon technology
• Vertical orientation Cell area ↓
• Placing defined numbers of nanotubes at selected locations
Summary : Remaining Obstacles
• High voltage Vertical gate (14V 4V : still high)
• The growth temperature used in this work : 600–650 oC is relatively high for integration with CMOS tec
hnology
• Still larger (~200nm ) : Need demonstration at smaller size is needed
• Randomization of nanotube orientation by thermal fluctuations and gas flows
References• “ Nanoscale memory cell based on a nanoelectromechanical switc
hed capacitor”, J. E. Jang, et al. (Samsung Advanced Institute of Technology & U of Cambridge) Nature 26 Nanotechnology | VOL 3 | JANUARY 2008
• “Nanoelectromechanical switch with low voltage drive” J. E. Jang, et al. APPLIED PHYSICS LETTERS 93, 113105 2008
• Internet search – DRAM / CNT etc.
Thank you very much
See you again!
Q&A