nano s&t 2011 chennai talk

8/2/2019 NANO S&T 2011 Chennai Talk

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Compound Semiconductor Device (CSD) Laboratory


Development of III-V Quantum-Well FET on SiSubstrate for Post CMOS Low-Power Digital

Applications

Prof. Edward Yi Chang

Department of Materials Science and Engineering/ Electronic EngineeringNational Chiao Tung UniversityHsinchu, Taiwan

December 26, 201140 nm III-V QWFET Intel 45 nm HK/MG CMOS


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Undergraduate students 5,604

Graduate students 11,347

Total 16,951

Full-time faculty 694

Current Status

3


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NineColleges

Engineering

Management

Science

Humanities& Social

Sciences HakkaStudies

Photonics

Electrical &Computer

Engineering

BiologicalScience &

Technology

ComputerScience

4


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ResearchResources

National Center forHigh-Performance

Computing

NationalSynchrotron

Radiation ResearchCenter

InstrumentTechnology Research

Center

National ChipImplementation

Center

National

MeasurementLaboratory

National NanoDevice

Laboratories

National SpaceOrganization

5


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Engineering and Computer ScienceStrong in semiconductor, photonics, information and

communication technology, computer science 35th in Computer Science

47th in Engineering(SJTUs Academic Ranking of World Universities,2010)

27th in Computer Science

32nd in Engineering

(Essential Science Indicators (ESI))

ManagementCollege of Management accredited by AACSB (July 2007)

Academic Achievement

6


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65 % of CEOs and General Managers in the Hsinchu Science Park areNCTU Alumni

Dr. Ken KaoFounder

D-Link Corp.

Dr. Stan Shih

Founder

Acer Group

Dr. F.C. Tseng

Vice ChairmanTSMCDr. Robert Tsao

HonoraryChairman UMC

Major Contributor to

Taiwan's Economic Miracle

7


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Top Research Centers

Emerging Nano-Electronics and Systems (ENES) ResearchCenter

Frontier Photonics Center

Intelligent Information Communications Research Center (I2CRC)

Center for Interdisciplinary Science(CIS)

Brain Research Center Bioinformatics Research Center BRC

Biomedical Electronics Translational Research Center

8


8/91Compound Semiconductor Device (CSD) Laboratory

Project 1: Emerging Si-Based Devices and Materials

Low Leakage, Low-Power/Voltage Si-Based Devices andScaling; Si-Substrate Based Heterogeneous Integration;Emerging Non-volatile Semiconductor Memory Research; Non-Classical CMOS

Project 2: Nanostructure Based Meta-Materials and Devices

Semiconductor nano and quantum structures; Theoretical studyof sub-nano structures and atomic scale calculations; Tera Hertzsourses, detectors and their fundamental principles; Thermalelectrical devices and cooling chips; Quantum dot electro-dynamics, single photon sources and spintronics

Project 3: Tera Hz Circuits and Systems

Tera Hz Circuit Design and Simulation Technology; Tera HzPackaging Technologies; Terahertz Measurement Technologies;Tera Hz Image System

Project 4: Green Computing and Storage IC

- -

ENES: Major Research Topics

9



Major Activities

LED and Laser Devices and Fabrication :

New Methods for Reducing LED Efficiency droopfrom 34 to 4%. Room Temperature Electric-Pump GaN Blue VCSELs and Optical-Pump GaN Photonic-Crystal-SELs.

Si-based ferroelectric-like nonvolatile memory and near infrared photo-transistor.

Solar Cell Efficiency Improvement:

Nano-ITO Technologies for Broad-Band Wide-Angle Anti-Reflection.

Low Temperature Thin Film Silicon Solar Cell Device Fabrication .

Radio-Over-Fiber Transmission 32Gb/s 60GHz OFDM-Over-Fiber World Transmission Record.

OFDM Long-Reach PON Research.

Polymer Holographic Materials with World-Record Low Shrinkage Ratio.

Key Patents for Energy-Saving Display

Unique Stencil-FSC algorithm and demonstrated 120Hz operation without color-separation.

Liquid Crystal/Polymer Complexity and Applications on Display and Bio-Photonics.

10

Frontier Photonics Center


10/91Compound Semiconductor Device (CSD) LaboratoryCompound Semiconductor Device (CSD) Laboratory

OutlineIntroduction

Integrate III-V Compound Semiconductors on Si

Fabrication and Evaluation of 80-nm InAs-channel

QWFETs for Low-Power Logic Applications

40-nm InAs-channel HEMTs with fT of 663 GHz

Study of Electrical Properties High- dielectric materials

on InxGa1-xAs Capacitors

The Grand Challenges for III-V FET for Post-Si CMOS

Future Application Beyond CMOS



Evolution of CMOS technology,1960-2020

LG > 90nm

Poly Si

SiO2

Silicon Substrate

22nm < LG < 65nm LG < 22nm

High-k oxideMetalStrained Si

SOI substrate

Metal

High-k oxide

III-V materials

Ge

Engineered Substrate

1960-2003Downscaling of dimensions

2004-2010Decade of Materials

2010-2020convergence of technologies

Continuous shrinking oftransistor dimensions

Almost no change in materials Moores law driven by

lithography improvement

Conventional Si-CMOSreaches physical limits.

Moores law driven byintroduction of new materials& shrinking.

Si-CMOS combined withMEMS compoundsemiconductor, heterosystemintegration, etc.



Recent growing interest : III-V research for logicCMOS



Compound Semiconductor

Silicon in transistor channel is replaced by III-V compound semiconductor,taking materials from adjacent columns of periodic table.Result is much higher electron mobility, meaning significant performance andpower improvements.

Column III

Column V



III-V materials in general have significantly higher electron mobility than Si andcan potentially play a major role along with Si in future high-speed, low-powercomputing.

Higher mobility leads to higher speed at a given bias.Si CMOS technology is becoming ever more compatible with non-Si materials

(D.K. Sadana, IBM, 2005)

Jerry Woodall

III-V vs. Si (Materials Properties)



High Electron Mobility Transistors (HEMTs)

The high electron mobility transistors (HEMTs) is the popular technology

in military and high-frequency wireless applications. The heterojunction created by different band gap materials forms two

dimensional electron gas (2DEG) in the channel with very high electronmobility.

in Quantum Well



Near THz HEMTs

NCTU CSDLAB 2009


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Compound Semiconductor Device (CSD) LaboratoryCompound Semiconductor Device (CSD) Laboratory

Integrate III-V on Silicon Substrate


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Heterogeneous Integration

Advantages of integration of III-V compound

materials with Si platform: High speed

Low power

Mass production capability

300 mmwafer


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Over 4% lattice mismatchLarge number of threading dislocations

Large thermal expansion coefficient differenceDislocations generated during high temperature epitaxial growth

Growth of polar materials on non-polar substratesAnti-phase boundary

Problems of GaAs Growth on Si Substrate

Cross-hatchsurface


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Two Steps SiGe Buffer Layer Method

Controlling of layer compositions to produce stress at theinterfaces to block/bend the dislocations at interfaces 780 oC annealing to reduce dislocation density in eachlayer


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Interface-blocking of dislocations

1m

0.8m

0.8m

2.6m

In situ 750 C annealing for15 min performed on eachindividual layer

( Ge/Si0.05Ge0.95/ Si0.1Ge0.9/Si )

The interface stress at each layer terminates

dislocation effectively!!!


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AFM image of the surface of the top Ge layer

Two steps growth (RMS :32 )

Nocross-hatchpattern!!!!

This smooth surface is useful for the growth of III-V materials

and fabrication of devices


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GaAs epilayer grown on Si substrate

with 60 off orientation


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Antiphase boundaries and Off-Cut Angle Substrate

Ge As Ga

Antiphase boundaries

antiphase boundary


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Use of off-cut substrate to solve antiphase boundary

To control initial nucleation only at the stepsPrevent antiphase boundary formation on the surface


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The Growth of GaAs on Si with Ge Buffer Layer

1m

GaAs epilayer/ Ge / GexSi1-x/ Si

RMS:7.4

No antiphase boundary!!


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The XTEM image of the sample of GaAs on Si withGe/SixGe1-x Buffer Layer

6o off-cut

GaAs

Ge

Epitaxial growth withoutantiphase boundary


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Impurity diffusion of 0 and 6 off-cut substrates

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.510

0

101

102

103

104

105

106

107

108

Si

Ge

Ga

As

As

Ga

Ge

SiSecondaryion

intensity(cts/s)

Depth (microns)

0o

offcut

0.83m

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.510

0

101

102

103

104

105

106

107

108

Ga

As

Si

Ge

As

Ga

Ge

Si

Secondaryion

intensity(cts/s)

Depth (microns)

6o

offcut

0.25m

6 off-cut0 off-cut

6 off-cut substrate also reduces the Ge diffusion into the GaAs layer


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Use of Si+ Pre-ion-implantation on Si substrate toEnhance the Strain Relaxation of the GexSi1-x

Metamorphic Buffer Layer


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Layer structure of the two steps SiGe buffer with Si+ pre-ion-implantation

Ge0.9Si0.1 metamorphic buffer

450oC, 30mTorr

Ge Epi layer

400oC, 30mTorr

750oC, 10min, annealing

Si+pre-ion-implantation at the surface

Ge0.8Si0.2 metamorphic buffer

450oC, 30mTorr

Si (001) substrate

Si+ dosage=5x1015cm-2

Acceleration voltage=50kev


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Buffer layer thickness comparison with and withoutSi+ pre-ion-implantation

0.55m

GexSi1-x buffer1.45m

2m

With Si+ ion implantation Without Si+ ion implantation

The thickness of the GexSi1-x buffer was greatly reduced becauseof the strain relaxation induced by Si+ pre-ion-implantation

0.45m

1m

0.55m

[004]GexSi1-x

Si+ pre-ion-implantation

Ge layer


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Double crystal x-ray diffraction data of GexSi1-xmetamorphic buffer layer on Si (004) substrate with and

without Si+ pre-ion-implantation

-7000 -6000 -5000 -4000 -3000 -2000 -1000 0 1000

1

10

100

1000

10000

100000

Si0.1

Ge0.9

intensity

arcsec

Si

Ge

Si0.2

Ge0.8

5380arcsec

FWHM:134arcsec

-7000 -6000 -5000 -4000 -3000 -2000 -1000 0 1000

1

10

100

1000

10000

100000

Si0.2

Ge0.8

Si0.1

Ge0.9

intensity

arcsec

Si

Ge 5425arcsec

FWHM:141arcsec

(a) With Si+ ion implantation (b) Without Si+ ion implantation


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Surface morphology by AFM measurement andNomarski microscope

10m10m

(a) AFM measurement (b) Nomarski image

Dislocation density is8.3106 cm-2RMS: 0.38nm

This smooth surface is useful for growth of III-V materials and

fabrication of devices


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AlGaSb/InAs HEMT structures on Si substrate withGe/GexSi1-x metamorphic buffer layers


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-15000 -10000 -5000 0 5000 10000

1

10

100

1000

10000

100000

-15000 -10000 -5000 0 5000 10000

1

10

100

1000

10000

100000

0

2

4

6

8

10

arc sec

GaAs

Al0.6Ga0.4Sb

AlSb

GaSb

Al0.5

Ga0.5

Sb

Si

InAs

Cap layer GaSb

Schottky layer Al0.5Ga0.5Sb

Channel layer InAs

Buffer Al0.5Ga0.5Sb

GaSb/AlSb 10 pairs

Al0.5Ga0.5Sb

GaSb/AlSb 10 pairs

Ge/SiGe

GaAs

AlSb

Si sunbstrate

Cap layer GaSb

Schottky layer Al0.5Ga0.5Sb

Channel layer InAs

Buffer Al0.5Ga0.5SbGaSb/AlSb 10 pairs

Al0.5Ga0.5Sb

GaSb/AlSb 10 pairs

GaAs substrate

AlSb

Al0.5Ga0.5 Sb/InAs/ Al0.5Ga0.5 SbMHEMT on Si substrate

Ge/SiGe

4%

Lattice mismatch12%

Structure 1

Structure 2


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Growth of InAs channel HEMT structure onSi substrate

Cap layer GaSb 5nm

Schottky layer Al0.5Ga0.5Sb 10nm

Channel layer InAs 15nm

Buffer Al0.5Ga0.5Sb 50nm

GaSb/AlSb 10 pairs SL

Al0.5Ga0.5Sb 2um


Ge/SiGe

GaAs

AlSb 100nm

Si sunbstrate

UHV/CVD system

MOVPE system

MBE system

560

520 High mobilitychannel


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TEM images of InAs-contained MHEMT on SiSubstrates

Cap layer GaSb 5nm

Schottky layer Al0.5Ga0.5Sb 10nm

Channel layer InAs 15nm

Buffer Al0.5Ga0.5Sb 50nm


Al0.5Ga0.5Sb 2um


Ge/SiGe

GaAs

AlSb

Si sunbstrate

GaAs

Ge

Al0.5Ga0.5Sb

SL

SL

100nm

100nm


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Electron mobility : 27,300cm2/Vs

High resolution TEM image of InAs channel onSi substrate

Threading dislocation wasblocked by Super lattice

GaSb cap 5nm

InAs channel 15nm

Al0.5Ga0.5Sb buffer 50nm

Al0.5Ga0.5Sb schottky 10nm


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Interface characterization by TEM analysis

GaAs

AlGaSb

AlGaSb/SL/AlSb/GaAs/GeSi/Si

Lattice mismatch between AlSb and

GaAs is 9%

100nm AlSb buffer

GaSb/AlSb SL 10 pairs

Ref: Appl. Phys. Lett., Vol. 74, No. 22, 31 May 1999


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Ra:1.07nmRa: 1.2nm

InAs MHEMT / GaAs / Ge /SiGe / Si sub. InAs MHEMT /GaAs sub.

Surface Morphology of Al0.5Ga0.5 Sb / InAs /Al0.5Ga0.5 Sb MHEMT on Si and GaAs Substrates


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Reciprocal Space Map data [004] orientationInAs/AlGaSb on GaAs substrate InAs/AlGaSb on Si substrate

60

off angle toward to [110]

substrate Mobility (cm2/v-s) Carrier Concentration (1/cm2)

Si 27,400 3.04*1012

GaAs 23,014 1.45*1012

Highest mobility ever reported on Si substrate!!!


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InAs on Si by Wafer Bonding Method

A new technology platform and device

concept for the integration of ultrathinlayers of III-V semiconductors directlyon Si substrate.

Ref: Hyunhyub Ko, et al Nature, Vol. 468 2010

I G A Q t W ll T i t Sili


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In0.7Ga0.3As Quantum Well Transistor on SiliconSubstrate using Thin Composite Buffer Architecture

The heterogeneous integration of In0.7Ga0.3Asdevice structure on Si through a novel, thincomposite metamorphic buffer architecture withthe total composite buffer thickness scaled downto 1.3 m, resulting in high-performanceIn0.7Ga0.3As QWFETs on Si for future high-speeddigital applications.

Ref: www.intel.com


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Benefits of QWFETs for Logic Applications(compared with Si MOSFET)

Higher mobility channel

(In0.7GaAs ~ 11,000 cm2/Vs, InAs~ 20,000 cm2/Vs, and

InSb 30,000 cm2/Vs)

Superior intrinsic speed (gate delay)

Low supply voltage (Vcc= 0.5V) low power dissipation


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Why III-V Research For Future Logic Applications

III-V has been used in commercial communication and optoelectronics product for

a long time mature manufacturing technology> 30 electron mobility improvement over Si

Low energy delay product better energy efficiency

Potential for high-speed and low-power logicRef. Robert Chau, Intel


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Structure of NCTU InAs-Channel QWFETs

Short gate length (80nm)

InAs / In0.7Ga0.3As channel

n-InAlAs i-InGaAs n-InAlAs i-InGaAs

I A Ch l QWFET G t F b i ti


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InAs-Channel QWFETs Gate Fabrication

High dosage for the bottom layer to get the desired short foot-print

FEP171200nm

PMGI 450nm

ZEP52080nm

IP

Resist Coating

(Tri-layer)

1st EB exposure

(Low dose for toplayer )

TopFEP) PMGI Dev.

MF622)

2nd EB exposure

High dose forbottom layer)

Bottom ZEP Dev(Xillen

Au/Ti Evaporation

(150nm/10nm)

Lift off

(ZDMAC)

400nm

FEP171200nm

PMGI 450nm

ZEP52080nm

IP

ZEP 520 (200nm)

PMGI (450nm)

ZEP520 (100nm)

InP

Resist Coating

(Tri-layer)

1st EB exposure

(Low dose for toplayer )

Top(ZEP)PMGI Dev.

(MF622)

2nd EB exposure(High dose for

bottom layer)

Bottom ZEP Dev(Xylene

Gate Metal Evaporation

(80/60/180nm)

Metal lift off

(ZDMAC)

nmnme- e-

Nano T-gate without any dielectric film and dry etching.

Width of T-top was 400nm and the Lg= 80nm.


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Au electro-plating: 2.1 umHeight of Air-Bridge: 2.5 um

SEM Images of QWFETs Device

Air-bridge

T-shaped Gate


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DC Performance of the 80 nm InAs QWFETs

0.0 0.1 0.2 0.3 0.4 0.50

200

400

600

800

1000

DrainCurr

ent(mA/mm)

Drain-Source Voltage (V)

InAs QWFETs

Lg = 80 nm

S-D spacing = 2 m

Vg = 0 ~ -0.8 V

Step: -0.2

-1.0 -0.8 -0.6 -0.4 -0.2 0.0-100

0

100

200

300

400

500

600

700

800

900

1000

1100

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

-200

0

200

400

600800

1000

1200

1400

1600

1800

2000

Transconductance(mS/mm)

VDS

= 0.2 ~ 0.5 V

Step : 0.1 V

Lg = 80 nm

S-D spacing = 2m

Draincurrentd

ensity(mA/mm)

Gate-Source Voltage, Vgs (V)

IDS= 1015 mA/mm @VG=0V, VDS=0.5V

gm,max= 1900 mS/mmVT= -0.81 V


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Frequency-domain Small Signal Device

Modeling


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S-parameter Measurement

On-wafer probe system usedfor S-parameter measurement

LRM calibration adopted usingstandard calibration kits, thecalibrated reference plane is at

the tip of the GSG probe. To minimize the possible

measurement error (mainlyshift in phase and additional

reactive parasitic elements),averaging on measured S-parameters is performed.

Source

Pad

Source

Pad

Gate

Drain

R f Pl Di d R l i


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Reference Plane Discrepancy and ResultingParasitic Effects - Illustration

Intrinsic device, active region

Desired reference plane

Probing position, equivalent toreal measurement referenceplane, may vary from eachmeasurement


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Corresponding Circuit Block Diagram

GND

IN OUT

Intrinsic

(Scalable)

SourceParasitic

(Scalable)

Gate

Parasitic

(Scalable)

Drain

Parasitic

(Scalable)

Gate-Source

Parasitic

(Fixed)

Drain-Source

Parasitic

(Fixed)

Zo,q Zo,q

Transmission line to accommodate for possiblephase shift caused by probe positioning variationfrom measurement to measurement


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Small-signal Equivalent Circuit

IN OUT

GND

Source

Parasitic

(Scalable)

Gate

Parasitic

(Scalable)

Gate-Source

Parasitic

(Fixed)

Drain-Source

Parasitic

(Fixed)

Zo,q Zo,q

Drain

Parasitic

(Scalable)

Small Signal Equivalent Circuit


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Small Signal Equivalent Circuit

Intrinsic

Parasitic(mainly fromprobing pads)


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Modeled Results for InAs QWFETs

2x50 um Device @ Vds = 0.7 V, Vgs = -0.5V


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RF Performance of the InAs QWFETs at LowSupply Voltage after Removal the Parasitic Effect

1 10 100 10000

5

10

15

20

25

30

35

40

Lg = 80 nm

Wg = 40m

S-D spacing = 2 m

Vds = 0.4 V

Vgs = -0.45

fmax

= 220 GHzf

T= 340 GHz

Gain(d

B)

Frequency (GHz)

H21

MAG/MSG

1 10 100 10000

5

10

15

20

25

30

35

40

fmax

= 260 GHz

fT

= 393 GHz

Lg = 80 nm

Wg = 40m

S-D spacing = 2 m

VDS

= 0.5 V

Vgs

= -0.45

Gain(d

B)

Frequency (GHz)

H21

MAG/MSG

H21@ 80GHz= 12.4dB

MAG/MSG @ 80GHz= 8.8dB

fT= 340GHz,fmax~ 220GHz

H21@ 80GHz= 14.0dB

MAG/MSG @ 80GHz= 10.2dB

fT= 393GHz,fmax~ 260GHz

V f I I i i


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VDS for Impact Ionization

-1.0 -0.8 -0.6 -0.4 -0.2-0.8

-0.6

-0.4

-0.2

0.0

(b)

InAs/In0.7

Ga0.3

As Channel QWFETs

VDS = 0 - 0.9 VV = 0.1 V

GateLeakag

ecurrentIG(mA/mm

)

Gate Source Voltage, V (V)

0.60 0.65 0.70 0.75 0.80 0.85 0.90

7.6

7.8

8.0

8.2

8.4

8.6

(a)

H21

@8

0GHz(dB)

Drain Source Voltage, VDS

(V)

InAs/In0.7

Ga0.3

As Channel QWFETs

1. It is obvious that H21 has the highest gain at drain voltage 0.8 V anddecreases when the bias voltage increases.2. The dramatic increase in gate leakage current further evidenced the

occurrence of impact ionization for biases higher than 0.8.Ref:B. Y. Ma, IEEE MTT 2006.


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RF Performance of the InAs QWFET after removalthe parasitic effect

1 10 100 10000

10

20

30

40

fmax

= 390 GHz

fT=494 GHz

U

H21

MAG/MSG

Gain(dB)

Frequency (GHz)

Lg

= 80 nm

Wg

= 2 x 50 m

VD

= 0.8 V

VG

= -0.5 V

Before impact ionization, the InAs QWFETs exhibits very high fTof494 GHz andfmax of 390 GHz.

Wh t tt f l i i t i t


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What matters for logic in a transistorTransistor operates as a switch in

logic applications

Interest in :

On-state current

Off-state current

Operating VDS Drain Induced Barrier Lowering

Subthreshold Slope

Gate capacitance

Threshold voltage (VT)

VT dependence on Lg

Device footprintRef: Jesus A. del Alamo, 19th IPRM 2007

0.0 0.1 0.2 0.3 0.4 0.50

100

200

300

400

500

Draincurrentdensity(

mA/mm)

VDS

(V)

40 nm InAs HEMTs

VGS

= -0.3 V

VGS

= -0.175 V

VGS

= -0.05 V

VGS

= 0.075 V

VGS

= 0.2 V

Sub threshold Evaluation Method


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Sub-threshold Evaluation Method

- ION = ID (VGS = VT + VCC, VDS = VCC)

-1.0 -0.5 0.0 0.5

1E-4

1E-3

0.01

0.1

1

10

100

1000

VDS = VCC = 0.5 V

ID[mA/mm]

VGS

[V]

- VT at ID = 1 mA/mm & S = 1/Slope(VGS=VT, VDS=VCC)

- IOFF = ID (VGS = VT VCC, VDS = VCC)

VT

VCC = 0.5 V

IOFF

ION

VCC3

1

VCC3

2

1 mA/mm

VGS

ID[mA/mm]

Ref: Robert. Chau, IEEE T-Nano 2005; D.-H, Kim, IEDM, 2005

- DIBL = [ VT (VDS=VCC)- VT ( VDS=0.05V) ] / (VCC-0.05)3

2

3

1


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Sub-threshold Characteristics of InAs QWFETs

-1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.210

-3

10-2

10-1

100

101

102

103

Ion

Ioff

VT=-0.81V

Log(Ids)mA

/mm

Gate Voltage (V)

InAs QWFETs

VDS

= 0.05 V

VDS

= 0.5 V

NCTU QWFETs:

InAs channel

Lg= 80nm,

InP substrateVCC=VD=0.5VIOFF = 510-2 @ Vgs=-0.98VION = 1.9102 @Vgs=-0.48V

ION/IOFF ratio = 3.8 103

DIBL = 200 mV/V

Sub-threshold slope = 115 mV/dec

Dependency of Logic Parameters on V


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Dependency of Logic Parameters on VT

Useful to explore suitability of novel devices with non-optimized VT

Varying VT definition maps tradeoff between ION/IOFF and CV/I

Methodology of Lundstrom (IEDM, 2004)

-1.0 -0.5 0.0 0.5

1E-4

1E-3

0.01

0.1

1

10

100

1000

VDS

= VCC

= 0.5 V

VGS

[V]

VT

IOFF

ION

VT

VCC3

1

VCC3

2

ID[mA

/mm]

VGS

D l Ti V V


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Delay Time vs. VT VT

0.05 0.10 0.15 0.20 0.250.0

0.2

0.4

0.6

0.8

1.0

1.2

InAs QWFETs

VDS

= 0.5 V

Gatedelay(psec)

VT'-VT

VCC 0.5VVT -0.58

Vgs-OFF -0.75

Vgs-ON -0.25

ION 26.09 mA

Cgs(@ ION) 13.1

Cgd(@ ION) 15.3

Cgs+Cgd 28.4Delay (psec) 0.54

C V

I=

(CGS + CGD) VCC

ION

VCC, ION= 0.54 psec

80 nm InAs QWFETs for High-Speed Low-Power


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Q g pand Logic Applications

100

101

102

103

0.1

1

10

40 nm InAs QWFET

Lg = 80 nm

Si NMOSFETs

VCC

= 1.1 ~ 1.5 V

InSb QWFETs

VCC

= 0.5 V

Gatedelay(psec)

Gate length, Lg (nm)

In0.52

Ga0.48

As QWFETs (VCC

= 0.7 V)

In0.7

Ga0.3

As QWFETs (VCC

= 0.7 V)

InAs/In0.7

GaAs QWFETs without gate sink (VCC

= 0.6 V)

InAs/In0.7

GaAs QWFETs with gate sink (VCC

= 0.6 V)

InAs QWFETs show > 3 gain in speedperformance for the same power compared toSi nMOSFETs, indicating great potential forlow-power and high-speed logic.

The InAs QWFETs exhibit lower gatedelay than the advanced Si MOSFETs.

Benchmarking against Si MOSFETs

10 1000

50

100

150

200

250

300

350

400

450

500

500

Si NMOS, Lg = 80 nm, VDS

= 0.7 V

CutoffFrequency,

fT(GHz)

Power Dissipation (mW/mm)

InAs QWFETs, Lg = 80 nm, VDS

= 0.5 V

InAs QWFETs, Lg = 80 nm, VDS

= 0.4 V

> 3 Speed

D i t t d 40 t t T h d t


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Device structure and 40-nm two-step T-shaped gate

10 15 20 25 30 35 40 45 50

-0.2

0.0

0.2

0.4

0.6

InAs/In0.53

Ga0.47

As composite channel HEMTs

Distance(nm)

Energy(eV)

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.21.4

1.6

1.8

2.0

E

lectronConc.(X1018/cm3)

Channel Materials:In0.53Ga0.47As/InAs/In0.53Ga0.47AsChannel Thickness:2/5/3 nm


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40 nm HEMTs Devices with two step recess process

PR

SiNx

Cap

InP

Scohttky

ICP

Two-step Recess

InGaAs Cap: Wet Etching (CA+SA)InP Etching Stop : Dry etching (Ar ICP)

CA+SA

Channel

Mesa

Ohmic

+

SiNx

E-beam

+

Recess

Gate

Pt/Ti/Pt/AuAnnealing(Pt sink)


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DC Performances of 40-nm InAs-channel HEMTs

-0.8 -0.6 -0.4 -0.2 0.0 0.2-100

0

100

200

300

400500

600

700

800

900

1000

1100-0.8 -0.6 -0.4 -0.2 0.0 0.2

-200

0

200

400

600

800

1000

1200

1400

1600

1800

2000InAs/In

0.53Ga

0.47As HEMTs

Lg = 40 nmTransconduc

tance(mS/mm)

IDS

(mA/mm)

VGS (V)

VDS

= 0.5 V

VDS

= 0.7 V

VDS

= 0.9 V

VDS

= 1.0 V

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0

100

200

300400

500

600

700

800

Draincurrentden

sity(mA/mm)

VGS

(V)

40 nm InAs/In0.53

Ga0.47

As HEMTs

VGS

= 0 to -0.5, step = -0.1 V

gm,max= 1900 mS/mm @ VDS =1.0 V, VT= -0.35 V

IDS= 780 mA/mm @VG=0V, VD=1.2V


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Output Conductance

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0

200

400

600

800

1000

1200

1400

1600

1800

2000

VDS

(V)

Outputconductance(mS/mm)

40 nm InAs/In0.53

Ga0.47

As HEMTs

VGS

= 0 V

VGS

= -0.1 V

VGS

= -0.2 V

VGS

= -0.3 V

VGS

= -0.4 V

VGS

= -0.5 V

The humpy behavior of go curve at certain bias level implied the occurrence ofimpact ionization.

Gate leakage current as a function of gate voltage at


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Gate leakage current as a function of gate voltage atdifferent drain bias

-0.8 -0.6 -0.4 -0.2 0.0

-100

-50

0

GateLeakageCurrentIG(10-6A)

VGS

(V)

VDS

=0 ~1.2V (step = 0.2 V)

1.2V

The rapid increase in total gate current for VDS > 1.0 V together with the existinghump at VGS = 0 V ~ -0.4 V were associated with the impact ionization.


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RF performances of 40-nm InAs-channel HEMTs

0.5 0.6 0.7 0.8 0.9 1.00

100

200

300

400

500

600

700

Freque

ncy(GHz)

Drain-Source Voltage, VDS

(V)

current-gain cutoff frequency fT

maximum oscillation frequency fmax

H21@ 80 GHz= 18.6 dB, Ug @ 80GHz= 13.3dB

fT= 662 GHz,fmax= 345 GHz

Frequency as a function of drain-sourcevoltage

1 10 100 10000

5

10

1520

25

30

35

40

45

50

fMax

= 345 GHz

fT

= 662 GHz

40 nm InAs/In0.53

Ga0.47

As HEMTs

VDS

= 0.9 V

VGS

= 0 V

Ga

in(dB)

Frequency (GHz)

H21

Ug

Extracted parameters of InAs channel HEMTs


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Extracted parameters of InAs-channel HEMTs

0.5 0.6 0.7 0.8 0.9 1.00

10

20

30

40

50

60

Gate-to-Source Capacitance, CGS

RF Gm

Drain Voltage, VDS

Gate-to-SourceCapacitance,C

GS(

fF)

120

150

180

210

240

270

RFGm

(mS)

Gate-to-source capacitance and RF Gm versus drain voltages

This curve explains the reason of the occurrence of fT peak at 0.9V. Peak fT occurs at a minimumCGS near the occurrence of impact ionization. Qualitatively, impact ionization mechanism tendsto introduce hole injection into the channel, and part of the injected holes may flow into gateelectrode as a gate current. This gate current gives rise to an additional capacitance in series withthe gate-to-source capacitance, causing a decrease of CGS.

Noise performances of 40 nm InAs channel HEMTs


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Noise performances of 40-nm InAs-channel HEMTs

0

2

4

6

8

10

12

14

6050403020 70

40 nm InAs/In0.53

Ga0.47

As HEMTs

VDS

=1.0V PDC

= 18.1 mW

VDS

=0.8V PDC

= 14.1 mW

VDS

=0.7V PDC

= 10.2mW

VDS

=0.6V PDC

= 6.8 mW

VDS

=0.5V PDC

= 4.3mW

NF

min

(dB)

Frequency (GHz)

0

2

4

6

8

10

12

14

16

18

20

AssociatedGain(dB)

The measured minimum noise figure (NFmin) at 64 GHz was 2.95 dB with the correspondingassociated gain (Ga) of 8 dB at VDS = 0.8 V. However, the drastic increase of NFmin is exhibitedat VDS of 1.0V. The phenomena are believed to be due to the generation of electron-hole pairsand the recombination of the carrier at high electric field due to impact ionization.


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How about III-V MOSFET?

Improve Al2O3/In0 53Ga0 47As interface quality by


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(a) Native surface

(b) After TMA treatment

(c) Sulfide + TMA treatment

(d) TMA treatment, PDA: 500C in N2

(e) Sulfide + TMA treatment, PDA: 500C in N2

(f) Sulfide + TMA treatment, PDA: 500C in H2

p 2 3 0.53 0.47 q y y

surface treatment and gas annealing

XPS analysisALD

Al2O3 at 300oC

PDA500oC, N2

PDA500oC, N2

PDA

500oC, H2

ALDAl2O3 at 300

oC

TMA treatmentonly

Sulfide + TMAtreatment

Improve Al2O3/In0.53Ga0.47As interface quality by


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Appl. Phys. Lett. 97, 042903 (2010)

18 nm Al2O3/In0.53Ga0.47As

TMA treatment only, N2 PDA Sulfide + TMA treatment N2 PDA Sulfide + TMA treatment, H2 PDA

Dit profile, Poisson simulation

Bump Inversion Strong inversion

True inversion response at high frequency

of 1 MHz

Low Dit < 5e11 by conductance method

and ~ 1e11 eV-1cm-2 by simulation at near

midgap

surface treatment and gas annealing

Al2O3/InAs structures with TMA, HCl + TMA and Sulfide + TMA


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HCl plus TMA treatment (NH4)2S plus TMA treatment

Dit profiles

Simulation: Poisson equation

3

treatments

Dit ~ 1e11 eV-1cm-2 at 0.4

eV and ~ 8e12 eV-1cm-2 at

InAs at midgap

A comparison of electrical properties of Al2O3/InxGa1-xAs


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Structure and parameters

MOS capacitors (x = 0.53> 1) Keys: The increase of In content result in lower band gap, higher electron mobility and intrinsic

carrier density

Surface treatment: HCl + TMA treatmentHCl:H2O (1:10), 1min, In situ 10 TMA/N2 pulses

Post oxide deposition annealing in H2/N2 gas, 30s High frequency C-V behavior

Low frequency C-V behavior

Minority response time

12nm Al2O3

Al2O3/InAs structures with TMA, HCl + TMA and Sulfide + TMA treatments


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TMA

treatment

In situ 10 TMA/N2 pulses

HCl + TMA

treatment

HCl:H2O (1:10), 1min,

In situ 10 TMA/N2 pulses

Sulfide + TMA

treatment

HCl:H2O (1:10), 1min

(NH4)2S 20% : H2O (1:3),

20min In situ 10

TMA/N2 pulses

Purpose: Comparison of different kinds of surface treatments, because it is not studied in

details for InAs case

Observed strong inversion at high frequency

Low frequency dispersion in both accumulation and

inversion regions

HCl + TMA treatment shows smallest C-V stretch out,

smallest frequency dispersion at inversion region

18 nm



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Fermi level movement

Unpinning Fermi level

In0.53Ga0.47As In0.7Ga0.3As InAs

MOS capacitors (x = 0.53> 1)

Conductance maps

Small frequency dispersion

Decrease hysteresis with increase In content



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Leakage currents

Increase with the increase of Indium content

Negative voltage: higher In-content -> higher probability for hole tunneling

Positive voltage: higher In-content -> lower electron effective mass -> more susceptible to

tunneling

MOS capacitors (x = 0.53> 1)

12nm Al2O3

High-Performance Al2O3/In0 7Ga0 3As MOSFETs


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High Performance Al2O3/In0.7Ga0.3As MOSFETs

Schematic view of an inversion-mode n-channel In0.7Ga0.3As(11017/cm3) MOSFET with 5nm ALD Al2O3 as gate dielectric.

Ref: P.D.Ye, et al, IEDM 2009.

InAs-channel MOS-HEMTs with ALD Al2O3 Gate


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Dielectrics

Gate leakage vs voltage for different ALD Al2O3 gate dielectrics

DC characteristics for HEMTswith 30 ALD Al2O3

RF performances for HEMTs with 30 ALD Al2O3

Noise figure and associated gain forHEMTs with 30 ALD Al2O3

The Grand Challenges for III-V FET for Post-Si CMOS


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The Grand Challenges for III V FET for Post Si CMOS

1) Requirement of high-k gate dielectrics need high ION/IOFF ratio to minimize the stand-by power consumption

Need a high quality high-k dielectric/metal gate for QWFETs device or

MOSFET device

Ref: Sadana, IBM

The Grand Challenges for III-V CMOS


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The Grand Challenges for III V CMOS

2) Heterogeneous Integration

3) III-V p-type Devices

Use Ge or strained III-V materials as transistor channel for p-type FET

A rigorous heterogeneous integration of III/V compoundmaterials with Si platform is necessary.


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What if the high diversity integration fail?

A li i d C OS


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Applications Beyond CMOS

SOC Chips Link (As Energy SavingInterconnect)

Core 1 BPF

CPW or MTL

Core 2 BPF

A1cos (2f1t)

A2cos (2f2t)

BPF

BPF

A1cos (2f1t)

A2cos (2f2t)

High-Bandwidth Mixed RFand Digital Circuits

Substrate

THz and Sub millimeter Wave Imaging Applications


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THz and Sub-millimeter Wave Imaging Applications

Conclusion


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Conclusion

The strained InAs channel HEMT grown on Si substrate using two

steps SiGe buffer demonstrated world record mobility of 27,400cm2/V-s.

The gate delay of 80-nm InAs-channel QWFET is around 0.54 psec

and shows > 3 gain in speed performance for the same powercompared to Si nMOSFETs, indicating great, indicating great

potential for low-power and high-speed logic.

High K/ InGaAs, InAs MOS Capacitors with very low Dit can be

achievedusing proper surface treatment.

Acknowledgement


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Acknowledgement

The work is supported by NSC National ResearchProgram for Nanoscience and Technology, Taiwan. This work is in cooperation with Intel Corporation, USA,

and NTT, TIT, Japan.


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Thank you for your attention

nano s&t 2011 chennai talk

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