RAHUL SREEKUMAR Apt 217, 817 N 10th street, San Jose, CA-95112 | +1(510)-565-4489 | rahul.s.r.pillaveedu@gmail.com|

LinkedIn: https://www.linkedin.com/in/rahulsree

OBJECTIVE To obtain a full-time position in an Analog Mixed signal/ RF design and verification based industry, with an atmosphere where team skills and critical thinking are of prime importance. Seeking a platform to exhibit my multi-tasking skills in a high pressure environment. Strongly believe in my leadership and mentoring skills. EDUCATION • 2015-present

MSEE, San Jose State University (specialization in Analog/Mixed/RFIC VLSI) || GPA (up to 3rd semester): 3.75/4.0 • 2010-2014

B. Tech, TKM College of Engineering, Kerala, India || CGPA: 8.24/10 (Passed with First class with Distinction, scored in top 10% of class

RELEVANT COURSEWORK Semiconductor physics, Analog Integrated Circuits, Data conversion in AMS signals (ADC & comparator design), OPAMP architecture, Impedance Matching network design, PLL design, CPW structuring, Circuit Design theory in THz range, microwave amplifier design, Microwave PA gain and stability circle based design, NF design, s parameter analysis (OIP3, 1 dB compression point). SKILLS Programming languages: Verilog/RTL design, C++, python Tools: MATLAB Simulink, Cadence Virtuoso (EDA tool), Cadence Spectre, sp analysis and PVT simulations in Spectre, LVS and DRC extraction in 45nm free PDF technology, Ansys HFSS 3D (EM Tool), HFSS 3D layout extractor, wave port and lumped port analysis in HFSS, Microsoft Visio. Non-technical skills: Strong & well proven leadership, Critical thinking, Team management skills and communicative skills. PROJECTS/ TECHNICAL SEMINAR • 0.95-1.1 GHz PLL based CDR in 45nm CMOS technology.

(Sep’16- Dec’16) § Design and simulation of a PLL based CDR in 45nm CMOS technology. § Architecture features an optimized Fischette Phase Frequency Detector with minimal dead zone, whilst the VCO architecture is

a CMOS based LC VCO, with an active MOS varactor based tuning mechanism. § CDR operates at 1 GB/s NRZ data, with lock- in range of 150 MHz, and lock in time of less than 19ns. § Exhibits a peak-to-peak jitter of 51 ps at 1 GHz and the phase noise is less than -150 dBm at the required operating frequency.

• Low power, cascode stage LNA in 45nm CMOS technology. (Oct’16-Dec’16)

§ Design and simulation of a low power, cascode stage LNA in 45nm CMOS technology. § Features an Inter Modulation Distortion (IMD) technique to improve the linearity of the amplifier. § The achieved results were optimized for operation in Low energy Bluetooth applications & exhibits a power gain |S21| of14.1

dB, the input return loss |S11 | is -18.35 dB, Noise Figure (NF) of1.42 dB and 1dB compression point of -9.87 dBm. § Dc power consumption is 1 .98 mW from a 1V supply

• Design of tuned microwave amplifier at 60 GHz with shiftable center band characteristics. (July’16-present)

§ Design of microwave tuned PA system with a shiftable center band frequency using TSMC 65nm technology. § Design of corresponding matching networks and tunable inductor structures as CPW structures in HFSS EM tool. § Amplifier portrays narrowband characteristics with a shiftable center band frequency for multi-mode operation.

• Low power, low offset 6b Flash A/D converter with 1.5 Gsps in 65 nm TSMC CMOS technology. (July’16-Sep’16)

§ Design and layout of a 6-bit Flash A/D converter in 65 nm CMOS technology. § Introduction of a novel offset cancellation technique and kick back noise reduction mechanism. § Achieved industry stipulated performance with regards to power consumption and allowable input referred offset voltage under

simulation. • Design of double tail comparator for low power applications with resolution of 12-bits

(May’16) § Paper involves the design of a double tail comparator in 45nm technology based on Samaneh Babayan-Mashhadi’s and Reza

Lotfi’s research. § The architecture was able to provide the following performance specification; Vdd= 1V,fs= 2.4 GHz, 3δos= 3.1mV, =100µV, Pdiss(

at 2.4 GHz)= 20.23 µW PROFESSIONAL EXPERIENCE • Teaching Assistant for EE124 (Electronic Design II) lab at San Jose State University. (Aug’16-present) • Volunteering as Research Assistant (RA) in Analog/Mixed Signals Lab under mentorship of Dr. Shahab Ardalan, SJSU. (Mar’16-present) • Student intern with R&D team at KEL (Kerala Electrical Alliance Ltd), operated in the synthesis and development (Jan’14-Mar’14) of in house Permanent Magnet Brushless DC Alternator, with counter-rotating components.

Awards & Acknowledgments • Best volunteer award, IEEE Kerala section, 2011 • Served as IEEE SB TKMCE, Chair, 2014