MULTIVIBRATORS

• Most of the sequential logic circuits ,such as counters ,shift-registers, depend on train of clock pulses for their operation.

• Most of the digital systems need some kind of timing waveform.

• A pulse generator which produces a rectangular –wave output is known as

Multivibrator

Multivibrators can be designed using:

1.Transistors

2. IC-741

3. IC-555

Different type of Multivibrators are :

1.Astable MV: two quasi-stable states and does not require any triggering.

2. Monostable MV: Two states –one stable and one quasi-stable. Triggering is required

3.Bistable MV: Two stable states and can exist indefinitely in any of these states.e.g.Flip Flop.

• One of the most versatile linear integrated circuit is the 555 Timer.• Signetics Corporation first introduced this device as the SE/NE 555 in earlier

1970.• Since then this device has been used in a number of novel and useful

applications• These application includes monostable and astable multivibrator, waveform

generator.• the IC 555 is available as an 8-pin.• it operates in the +5 to +18 supply voltage

internal circuit of the 555 integrated-circuit timer .

555 IC

• Pin1 : ground• Pin 2: trigger• Pin 3: output• Pin 4: reset: the timer can be reset by applying a negative

pulse to this pin. When not used, it is connected to +VCC.• Pin 5: Control voltage: This is used to change the

threshold voltage as well as trigger voltage. When not used, the control pin should be bypassed to ground with 0.01uf capacitor to prevent any noise problem.

• Pin 6: threshold this is the non inverting terminal of the comparator 1.

• Pin 7: discharge: this pin is connected internally to the collector of the transistor. When the output is high, transistor is OFF and acts as a open circuit. When the output is low. the transistor will be in saturation and acts as short circuit.

• Pin 8: +VCC supply is connected w.r.t ground.

• Voltages at VTH and VTL are 2/3VCC and 1/3VCC respectively.

• Comparators produce 0 and 1 for V- > V+ and V- < V+ respectively.

• SR latch works on the following principle

S R Qn+1

0 0 Qn

0 1 0 1 0 1 1 1 NA• Output is available at 3• External triggers is generally applied at 2 no. pin of IC

Astable mode using 555

(a) The 555 timer connected to implement an astable multivibrator. (b) Waveforms of the circuit in (a).

555 for astable

• Initially capacitor is discharged i.e. VC=0. Assuming Q=0 . This will give Q’ as 1.transistor q1 will be ON. This will then connect pin7 to ground resulting capacitor to discharge.

• When supply voltage VCC is connected, V1=2/3 VCC and V2=1/3 VCC .

• This will cause comparator 1 to give logic 0 and comparator 2 to give logic 1

• Due to the above condition S=1 and R=0, which will cause Q to become 1 and hence Q’ to 0.

• When Q’=0 , transistor q1 will cut off

Capacitor charging model in IC 555 TIMER:

EQUIVALENT MODEL FOR ANALYSISSince OPAMP input current is zero so we can have the following model for analysis.

•Capacitor will start charging and will cause the voltage Vx to keep on increasing.

•During this time Q will be 1.

•Once capacitor gets the voltage of 1/3 VCC, comparator 2 will give logic 0, which will give S=0. Since comparator will keep on giving logic 0 so we have the following combination for S and R as 00. this condition will hold the latch output. It means Q=1.

•When the capacitor get the value of 2/3VCC, the comparator 1 will give logic 1. this will cause R=1 and since S=0 already, so this will cause Q=0. After this Q’ will be 1 which will cause transistor to be in ON state. So pin 7 will get connected to ground.

• Once pin 7 connected to ground, we have the following resulting circuit.

Discharging model

• When capacitor starts discharging , comparator 1 will give logic 0 means R=0, since by this time both the value of S and R are 0, this will maintain Q=1.

• When capacitor gets discharged up to 1/3 VCC

and if it tries to discharge more then 1/3VCC, Then comparator 2 will then give logic 1, which will result S=1. Since R=0 and S=1, this will cause Q=1 and hence Q’=0 which will then repeat the charging model. So capacitor will keep on charging and discharging between 2/3VCC and 1/3 VCC.

DERIAVTION OF TON AND TOFF

• TON can be calculated using charging model discussed earlier during square wave generator.

• During charging and discharging we have to use the following expression for calculating time.

• VC(t) = Vss – (Vss – Vinitial ).exp(-t/RC)

• TON is the time duration when capacitor voltage charges from 1/3VCC to 2/3VCC.

• TOFF is the time duration when capacitor voltage discharges from 2/3VCC to 1/3VCC.

• 2/3VCC= VCC – (VCC- 1/3VCC)(exp{-TON/(RA+RB).C})

exp{-TON/(RA+RB).C} = 1/2

TON= ln(2).{(RA+RB).C}

Similarly TOFF can be calculated by using discharging capacitor equation

1/3VCC= 0 – (0 - 2/3VCC)(exp{-TOFF/(RB.C)})

TOFF= ln(2).(RB.C)So total time period

T= TON + TOFF= ln(2).{(RA+2.RB).C}Since ln(2)= 0.693

T= 0.693*{(RA+2.RB).C}

• f = 1/[0.693*{(RA+2.RB).C}]

=1.44/[(RA+2.RB).C]

Duty cycle: DC = TON/ T = (RA+RB)/(RA+2.RB)

It is to be noted that TON is always greater than TOFF.

a) The 555 timer connected to implement a monostable multivibrator. (b) Waveforms of the

circuit in (a).

555 for monostable

• When IC 555 is to be used in Monostable mode, then 6 and 7 shorted together. External capacitor is applied at 6 no terminal

• Resistor R is connected Between (7 or 6) and pin 8

• External trigger( negative going) is applied to Pin 2. negative going means trigger will be consider or effective when initially it’s at logic high and then it becomes logic 0.

• This pulse must be of very short duration

• Initially capacitor is discharged. Since at Pin 2, trigger is initially at logic high. If Q=0 initially, then since S=R=0, this will hold the output Q at 0 and Q’ at 1 which will keep capacitor in discharged mode.

• When negative triggered is applied, pin2 will be getting logic 0 which will result comparator 2 to get logic 1 i.e. S=1. This will cause Q=1 and Q’=0 which will result the following equivalent model

• Capacitor starts charging via R.• Since trigger pulse is of small duration, so this will result

trigger to become logic high soon. This will cause comparator 2 to give low output resulting in S=R=0, which mean maintain output Q of flip flop

• As the value Vx increase and when its less then 2/3VCC, till then S=0 and R=0 will be maintain

• Once the capacitor tries to gets charged beyond 2/3VCC the comparator 1 will give logic 1 i.e. R=1 and S=0 , Which will result in Q=0. This will cause Q’=1. This will then make transistor on resulting in connecting capacitor to ground.

Different wave form

• The time period for the pulse can be obtained as given below

• VC(t) = Vss – (Vss – Vinitial ).exp(-t/RC)

Vc(TON)= 2/3VCC, VSS=VCC, Vinitial= 0

TON= ln(3). RC=1.1*(RC)