Real-time Analysis and Simulation of Multi-string

Grid-connected Photovoltaic inverter using FPGA

Presented by-

Satabdy Jena

MTech (Power & Energy Systems)

Department of Electrical Engineering

NIT Meghalaya

Satabdy Jena, Gayadhar Panda and Rangababu Peesapati

Contents

1. Introduction

2. Proposed System Structure

3. Control Algorithm

4. Field Programmable Gate Array

5. Xilinx System Generator

6. Hardware Co-Simulation

7. Conclusion

8. References

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1.Introduction

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Dearth of energy, trend of rising prices and limited resources.

Abundant availability of solar energy has lead to installation of large-scale Photovoltaic

systems(standalone or grid-connected).

• Grid synchronization

• Grid disturbances

Frequency

Voltage

• Industry design standards

2.Proposed System Structure

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PV2

MPPT1

MPPT2

PWM1

PWM2

SPWM PLL

Modulating

Signal

Generation

CURRENT

CONTROLLER

VOLTAGE

CONTROLLER

PV1

+-

V*dc

Vdc3-ф

3-Level

Central

Inverter

Filter

Inductance

Isolation

Transformer

ia,b,c ua,b,c

iq*

id* idq

udq

Utilty grid

abc

dq

ud* uq*

DC/DC

Boost Converter1

DC/DC

Boost Converter2

LfRf

Cf LtRt

ϴ

ϴ

Reference

Signal

Generation

mdq

FPGA Based Control Circuit

MULTI-STRING PV ARRAY

ipv1

ipv2

vpv1

vpv2

LOAD

Fig.1. Structure of proposed system

Terminology Description Terminology Description

Vpv, Ipv PV voltage and current Lt, Rt Transformer inductance and

resistance

Vdc Capacitor voltage Ls, RS Equivalent inductance and

resistance

ua, ub, uc Grid line voltages Lt, Rt Transformer inductance and

resistance

ia, ib, ic Grid line currents id, iq d and q-axes currents

Lf, Rf Filter inductance and

resistanceud, uq d and q-axes voltages

Lg, Rg Grid inductance and

resistancemdq Modulating signals

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Table 1. System Terminology description

3.Control Algorithm(a) MPP Tracking

• Incremental Conductance (Inc)

-by comparing instantaneous (Ipv

Vpv) and incremental conductance (

dIpv

dVpv), the MPP voltage of the PV

array is obtained.

dPpv

dVpv=

d(VpvIpv)

dVpv= 0 =>

Ipv

Vpv+

dIpv

dVpv= 0. (1)

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Fig.2. P-V characteristics of PV array

(b) Inner and Outer Control loop design for VSI

-Decoupling Technique

• ud∗ = Kpd id

∗ − id + Kid (id∗ − id)dt − ωL𝑠𝑖𝑞 + ud (2)

• uq∗ = Kpq iq

∗ − iq + Kiq (iq∗ − iq)dt + ωL𝑠𝑖𝑑 + uq

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Switching State

Switch configuration

Voltage

+1 1100 Van

0 0110 0

-1 0011 -Van

Fig.3. Outer and Inner Loop Design

Fig.4. Three-level Inverter Structure

Table 2. Switching states for the inverter

(c) Grid Synchronization

-Phase Locked Loop

A feedback system with a PI regulator tracking the phase angle .

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𝐺𝑜𝑙 = (𝐾𝑃1+𝑠𝜏

𝑠𝜏)(

1

1+𝑠𝜏)(𝑉𝑚

𝑠) (3)

-100

-50

0

50

100

Magnitude (

dB

) System: sys1

Frequency (rad/s): 314

Magnitude (dB): 0.0119

100

101

102

103

104

105

-180

-150

-120

-90

System: sys1

Frequency (rad/s): 314

Phase (deg): -108

Phase (

deg)

Bode Diagram

Frequency (rad/s)

-100

-50

0

50

Magnitude (

dB

)

101

102

103

104

105

-180

-135

-90

-45

0

Phase (

deg)

Bode Diagram

Frequency (rad/s)

Fig.5. Block diagram of PLL

Fig.6. Bode plot for Open loop system Fig.7. Bode plot for closed loop system

4.Field Programmable Gate Array

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An FPGA is a programmable breadboard for digital circuits-on-chip.

It consists of:

Programmable Logic Elements

Programmable Interconnects

Custom Circuitry

Fig.8.FPGA Configuration

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Fig.9. Structure of each Logic Element

5.Xilinx System Generator

A DSP-design tool.

Provides users with Xilinx block-set in Matlab/Simulink.

Automatic synthesis and place-and-route.

Bit-accurate and Cycle-accurate.

Handle VHDL, C or m-code.

Handle multiple sampling rates.

Generates a run-time hardware block (JTAG).

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• Precision and sampling time.

• Fixed and Floating-point representation.

• Clock period=40 ns.

• 75 MHz.

• Compatibility between different data-point types.

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6.Implementation in FPGA

Implementation in FPGA (contd.)

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Fig.10. Voltage controller in Xilinx blockset

Fig.11. SPWM in Xilinx blockset

Fig.12. Current controller in Xilinx blockset

Fig.13. PLL in Xilinx blockset

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Fig.14. Reference Signal Generation in Xilinx blockset

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Fig.15. Experimental Set-up

7.Hardware Co-Simulation

System parameters Value System parameters Value

Series connected modules 7(PV1) (PV2) DC Link voltage 750 V

Parallel connected modules 20(PV1) 30 (PV2) Filter inductance and resistance 1 mH, 3 mΩ

MPP Voltage 54.7 V Grid inductance and resistance 16 mH, 0.8929 Ω

MPP Current 5.58 A Transformer inductance and resistance 0.06 mH, 0.002 mΩ

Open-circuit voltage 64.2 V Inverter switching frequency 5 .5 kHz

Short-circuit current 5.96 A Boost switching frequency 5 kHz

Maximum PV power 85.5 kW Grid voltage 22 kV

DC Link capacitor 5000 μF Grid frequency 50 Hz

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Table 2. System Parameters

A test system consisting of a multi-string PV array connected to a 400 V three phase source via

a multilevel inverter has been considered. A local load consuming 10 kW of active power is

connected at the PCC.

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Fig.16. Irradiation Fig.17. Power consumed by load and grid

Fig.18. Power generation by the multi-string PV array

Case 1: Varying irradiance condition

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0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8-200

-150

-100

-50

0

50

100

150

200

X= 1.1846

Y= 77.2305

Time (sec)

i_a

(A)

X= 0.80466

Y= 187.9812

1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5-400

-300

-200

-100

0

100

200

300

400

i_a

/u_

a (

A/V

)

Time (sec)

ia

ua

Fig.19. Grid injected currentFig.20. Grid voltage and current

Fig.21. FrequencyFig.22. THD of grid injected currents

Case 2: Dynamic loading condition

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Fig.23. Grid injected current Fig.24. Load current

Fig.25. Real power exchange

P=10 kW, 1 kVAr to at t=0.8-1.5 s,P=100 kW, Q=15 kVAr

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Fig.26. Reactive power exchange

Fig.27. THD of grid injected currents

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Fig.28. Simulation and hardware results of SPWM Fig.29. Simulation and hardware results of PLL

Fig.30. Simulation and hardware results of d-axis current Fig.31. Simulation and hardware results of q-axis current

Fig.32. Simulation and hardware results of reference signal

Design Slice

Registers

(301440)

Slice

LUTs

(150720)

LUT FF

Pairs

Slices

(37680)

IOBS

(600)

Memory

(58,400)

Critical Path delay ns

PLL 139(1%) 962(1%) 123(12%) 283(1%) 59(10%) 33 (1%) 1.695ns

SPWM 0(0%) 57(1%) 0(0%) 20(1%) 92(15%) 0(0%) 3.220ns

Current

Controller

96(1%) 6410(4%) 62(1%) 1947(5%) 257(42%) 0(0%) 0.559ns

Voltage

Controller

48(1%) 1905(1%) 31(1%) 568(1%) 65(10%) 0(0%) 0.552ns

Reference

Signal

2306(1%) 4765 (3%) 2250 (46%) 1374 (3%) 307 (51%) 25 (1%) 9.484 ns

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Table 4. Resource Utilization

7.Conclusion

The proposed system was thus implemented in Matlab/Simulink and its real-time performance was

validated using FPGA. The performance of the system was analyzed and the correlation with the

theoretical evaluation was established. It is observed that the critical path delay is 9.5 ns.

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8.References[1] TJ Hammons, “Integrating renewable energy sources into Europeangrids,” International Journal of Electrical Power & Energy Systems,vol.

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[3] Mitra Mirhosseini, Josep Pou and Vassilios G. Agelidis,“Single- and Two-Stage Inverter Based Grid Connected Photovoltaic Power Plants

With Ride-Through Capability Under Grid Faults,” IEEE Transcations on Sustainable Energy, vol.6.,No.3.,July 2015.

[4] S.J.Huang and F.S.Pai,“Design and operation of grid connected phototvoltaicsystem with power factor control and active islanding

detection,” IEEE Proceedings on Generation, Transmission, Distribution,vol.48,No.2,2001.

[5] S.J.Huang and F.S.Pai,“Design and operation of grid connected phototvoltaic system with power factor control and active islanding

detection,” IEEE Proceedings on Generation, Transmission, Distribution, vol.48,No.2,2001.

[6] M. Castilla,J.Miret, A.Camacho, Jos´e Matas,De Vicuna and Luis Garc´ıa,“Reduction of current harmonic distortion in three-phase grid-

connected photovoltaic inverters via resonant current control,”IEEE Transactions on Industrial Electronics,VOL.60, No.4, pp.1464-1472,2013.

[7] T.Hornik and Qing-Chang Zhong ,“A Current-Control Strategy for Voltage-Source Inverters in Microgrids Based on and Repetitive

Control,”IEEE Transactions on Power Electronics,vol.26, No.3, pp.943-952,2011.

[8] T Q Zheng ,“Synchronous PI control for three-phase grid-connected photovoltaic inverter,” Proceedings of 2010 Chinese Control and

Decision Conference,2010.

[9] F. Ruza, A. Reyb, J.M. Torreloc, A. Nietob, F.J. Cnovasa,“Real time test benchmark design for photovoltaic grid-connected control systems,”

Electric Power Systems Research, Elseveir, vol.81,no, 4,pp. 907-914,2011.

[10] Mohammed A. Elgendy and Bashar Zahawi,“Assessment of the incremental conductance maximum power point tracking algorithm,” IEEE

Transactions on Sustainable Energy, vol. 4,no. 1, pp. 108-117,2013.

[11] Kaura and V. Blasko,“Operation of a Phase Locked Loop System Under Distorted Utility Conditions,” Eleventh Annual Proceedings of

Applied Power Electronics Conference and Exposition,vol.2,pp.703-708,1996.

[12] L. Hadjidemetriou, E. Kyriakides, and F. Blaabjerg,“A new hybrid PLL for interconnecting Renewable Energy Systems to the grid,” IEEE

Energy Conversion Congress and Exposition,pp.20752082,2012.

[13] Dean Banerjee,“PLL Performance, Simulation and Design,” 4th Edition,Dog Ear Publishing

[14] “System Generator User Guide,”Documentation, XILINX3/5/2016 24

Thank you

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