msp430x5xx _msp430x6xx

MSP430x5xx and MSP430x6xx Family

2 SLAU208M– June 2008– Revised February 2013 Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) ...................... 53
1.1 System Control Module (SYS) Introduction ............................................................................ 54
1.2 System Reset and Initialization .......................................................................................... 54
1.2.1 Device Initial Conditions After System Reset ................................................................. 56
1.3 Interrupts .................................................................................................................... 56
1.3.2 SNMI Timing ...................................................................................................... 58
1.3.3 Maskable Interrupts .............................................................................................. 59
1.3.4 Interrupt Processing .............................................................................................. 59
1.3.5 Interrupt Nesting .................................................................................................. 60
1.3.6 Interrupt Vectors .................................................................................................. 60
1.4 Operating Modes .......................................................................................................... 62
1.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4 ............................................ 65
1.4.2 Entering and Exiting Low-Power Modes LPMx.5 ............................................................. 65
1.4.3 Extended Time in Low-Power Modes .......................................................................... 66
1.5 Principles for Low-Power Applications .................................................................................. 68
1.6 Connection of Unused Pins .............................................................................................. 68
1.7 Reset Pin (RST /NMI) Configuration ..................................................................................... 69
1.8 Configuring JTAG pins .................................................................................................... 69
1.9 Boot Code .................................................................................................................. 69
1.11 Memory Map – Uses and Abilities ...................................................................................... 71
1.11.1 Vacant Memory Space ......................................................................................... 71
1.11.2 JTAG Lock Mechanism via the Electronic Fuse ............................................................. 71
1.12 JTAG Mailbox (JMB) System ............................................................................................ 72
1.12.1 JMB Configuration ............................................................................................... 72
1.12.4 JMB NMI Usage ................................................................................................. 73
1.13 Device Descriptor Table .................................................................................................. 73
1.13.1 Identifying Device Type ......................................................................................... 74
1.13.2 TLV Descriptors ................................................................................................. 75
1.13.4 CRC Computation ............................................................................................... 80
1.13.5 Calibration Values ............................................................................................... 81
1.14 SFR Registers ............................................................................................................. 83
1.14.1 SFRIE1 Register ................................................................................................. 84
1.14.2 SFRIFG1 Register ............................................................................................... 85
1.14.3 SFRRPCR Register ............................................................................................. 87
1.15 SYS Registers ............................................................................................................. 88
1.15.1 SYSCTL Register ................................................................................................ 89
1.15.2 SYSBSLC Register .............................................................................................. 90
1.15.3 SYSJMBC Register ............................................................................................. 91
3SLAU208M– June 2008– Revised February 2013 Contents Submit Documentation Feedback
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2.1 Power Management Module (PMM) Introduction ..................................................................... 99
2.2 PMM Operation ........................................................................................................... 101
2.2.2 Supply Voltage Supervisor and Monitor ..................................................................... 101
2.2.3 Supply Voltage Supervisor and Monitor - Power-Up ....................................................... 107
2.2.4 Increasing VCORE to Support Higher MCLK Frequencies ................................................... 107
2.2.5 Decreasing VCORE for Power Optimization .................................................................... 109
2.2.6 Transition From LPM3 and LPM4 Modes to AM ............................................................ 109
2.2.7 LPM3.5 and LPM4.5 ............................................................................................ 109
2.2.8 Brownout Reset (BOR), Software BOR, Software POR ................................................... 109
2.2.9 SVS and SVM Performance Modes and Wakeup Times .................................................. 110
2.2.10 PMM Interrupts ................................................................................................. 113
2.2.12 Supply Voltage Monitor Output (SVMOUT, Optional) ..................................................... 113
2.3 PMM Registers ........................................................................................................... 114
2.3.1 PMMCTL0 Register ............................................................................................. 115
2.3.2 PMMCTL1 Register ............................................................................................. 116
2.3.3 SVSMHCTL Register ........................................................................................... 117
2.3.4 SVSMLCTL Register ........................................................................................... 118
2.3.5 SVSMIO Register ............................................................................................... 119
2.3.6 PMMIFG Register ............................................................................................... 120
2.3.7 PMMRIE Register ............................................................................................... 122
2.3.8 PM5CTL0 Register ............................................................................................. 123
3.2.1 Battery Backup Switch Control ................................................................................ 126
3.2.2 LPMx.5 and Backup Operation ................................................................................ 127
3.2.3 Resistive Charger ............................................................................................... 127
3.3.1 BAKCTL Register ............................................................................................... 129
3.3.2 BAKCHCTL Register ........................................................................................... 130
4.2 Auxiliary Supply Operation .............................................................................................. 133
4.2.1 Startup ............................................................................................................ 134
4.2.5 Interactions Among fSYS, VCORE, VDSYS, SVMH, and AUXxLVL .............................................. 136
4.2.6 Auxiliary Supply Monitor ....................................................................................... 138
4.2.7 LPMx.5 and Auxiliary Supply Operation ..................................................................... 139
4.2.8 Digital I/Os and Auxiliary Supplies ............................................................................ 140
4.2.9 Measuring the Supplies ........................................................................................ 141
4 Contents SLAU208M– June 2008– Revised February 2013 Submit Documentation Feedback
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4.2.12 Software Flow .................................................................................................. 143
4.3 AUX Registers ............................................................................................................ 147
4.3.1 AUXCTL0 Register ............................................................................................. 148
4.3.2 AUXCTL1 Register ............................................................................................. 149
4.3.3 AUXCTL2 Register ............................................................................................. 150
4.3.4 AUX2CHCTL Register .......................................................................................... 151
4.3.5 AUX3CHCTL Register .......................................................................................... 152
4.3.6 AUXADCCTL Register ......................................................................................... 153
4.3.7 AUXIFG Register ................................................................................................ 154
4.3.8 AUXIE Register .................................................................................................. 155
4.3.9 AUXIV Register .................................................................................................. 156
5.1 Unified Clock System (UCS) Introduction ............................................................................ 158
5.2 UCS Operation ........................................................................................................... 160
5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ............................................... 160
5.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO) ......................................... 161
5.2.4 XT1 Oscillator ................................................................................................... 161
5.2.5 XT2 Oscillator ................................................................................................... 162
5.2.7 Frequency Locked Loop (FLL) ................................................................................ 164
5.2.8 DCO Modulator .................................................................................................. 164
5.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules ............................... 165
5.2.12 UCS Module Fail-Safe Operation ............................................................................ 167
5.2.13 Synchronization of Clock Signals ............................................................................ 170
5.3 Module Oscillator (MODOSC) .......................................................................................... 171
5.3.1 MODOSC Operation ............................................................................................ 171
5.4.1 UCSCTL0 Register ............................................................................................. 173
5.4.2 UCSCTL1 Register ............................................................................................. 174
5.4.3 UCSCTL2 Register ............................................................................................. 175
5.4.4 UCSCTL3 Register ............................................................................................. 176
5.4.5 UCSCTL4 Register ............................................................................................. 177
5.4.6 UCSCTL5 Register ............................................................................................. 178
5.4.7 UCSCTL6 Register ............................................................................................. 180
5.4.8 UCSCTL7 Register ............................................................................................. 182
5.4.9 UCSCTL8 Register ............................................................................................. 183
5.4.10 UCSCTL9 Register ............................................................................................ 184
6.2 Interrupts .................................................................................................................. 188
6.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 192
6.3.5 General-Purpose Registers (R4 –R15) ...................................................................... 193
6.4 Addressing Modes ....................................................................................................... 195
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6.4.7 Immediate Mode ................................................................................................ 210
6.5.1 MSP430 Instructions ............................................................................................ 212
6.6.1 Extended Instruction Binary Descriptions .................................................................... 229
6.6.2 MSP430 Instructions ............................................................................................ 231
6.6.3 Extended Instructions .......................................................................................... 283
6.6.4 Address Instructions ............................................................................................ 326
7.2.1 Segment A ....................................................................................................... 344
7.3.3 Flash Memory Access During Write or Erase ............................................................... 356
7.3.4 Stopping Write or Erase Cycle ................................................................................ 357
7.3.5 Checking Flash Memory ....................................................................................... 357
7.3.6 Configuring and Accessing the Flash Memory Controller ................................................. 358
7.3.7 Flash Memory Controller Interrupts ........................................................................... 358
7.3.8 Programming Flash Memory Devices ........................................................................ 359
7.4 FCTL Registers ........................................................................................................... 360
7.4.1 FCTL1 Register ................................................................................................. 361
7.4.2 FCTL3 Register ................................................................................................. 362
7.4.3 FCTL4 Register ................................................................................................. 363
7.4.4 SFRIE1 Register ................................................................................................ 364
8.1 MID Overview ............................................................................................................ 366
8.3 MID Parity Check Logic ................................................................................................. 367
8.4 Detecting Unprogrammed Memory Accesses ........................................................................ 368
8.5 MID ROM ................................................................................................................. 368
8.6.1 MidEnable() Function ........................................................................................... 369
8.6.2 MidDisable() Function .......................................................................................... 370
8.6.3 MidGetErrAdr() Function ....................................................................................... 370
8.6.4 MidCheckMem() Function ...................................................................................... 371
8.6.5 MidSetRaw() Function .......................................................................................... 371
8.6.6 MidGetParity() Function ........................................................................................ 372
8.6.7 MidCalcVParity() Function ..................................................................................... 372
9 RAM Controller (RAMCTL) ................................................................................................ 373
9.1 RAM Controller (RAMCTL) Introduction .............................................................................. 374
9.2 RAMCTL Operation ...................................................................................................... 374
9.3 RAMCTL Registers ...................................................................................................... 375
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10.2 Battery Backup Registers ............................................................................................... 378
11 Direct Memory Access (DMA) Controller Module ................................................................. 379
11.1 Direct Memory Access (DMA) Introduction ........................................................................... 380
11.2 DMA Operation ........................................................................................................... 382
11.2.4 Halting Executing Instructions for DMA Transfers ......................................................... 388
11.2.5 Stopping DMA Transfers ...................................................................................... 389
11.2.6 DMA Channel Priorities ....................................................................................... 389
11.2.7 DMA Transfer Cycle Time .................................................................................... 390
11.2.8 Using DMA With System Interrupts ......................................................................... 390
11.2.9 DMA Controller Interrupts ..................................................................................... 390
11.2.10 Using the USCI_B I2C Module With the DMA Controller ................................................ 392
11.2.11 Using ADC12 With the DMA Controller ................................................................... 392
11.2.12 Using DAC12 With the DMA Controller ................................................................... 392
11.3 DMA Registers ........................................................................................................... 393
11.3.1 DMACTL0 Register ............................................................................................ 395
11.3.2 DMACTL1 Register ............................................................................................ 396
11.3.3 DMACTL2 Register ............................................................................................ 397
11.3.4 DMACTL3 Register ............................................................................................ 398
11.3.5 DMACTL4 Register ............................................................................................ 399
11.3.6 DMAxCTL Register ............................................................................................ 400
11.3.7 DMAxSA Register .............................................................................................. 402
11.3.8 DMAxDA Register ............................................................................................. 403
11.3.9 DMAxSZ Register .............................................................................................. 404
11.3.10 DMAIV Register .............................................................................................. 405
12.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) ................................................. 408
12.2.5 Output Drive Strength Registers (PxDS) ................................................................... 409
12.2.6 Function Select Registers (PxSEL) .......................................................................... 409
12.2.7 Port Interrupts .................................................................................................. 409
12.3 I/O Configuration and LPMx.5 Low-Power Modes ................................................................... 411
12.4 Digital I/O Registers ..................................................................................................... 413
12.4.1 P1IV Register ................................................................................................... 419
12.4.2 P2IV Register ................................................................................................... 420
12.4.3 P1IES Register ................................................................................................. 421
12.4.4 P1IE Register ................................................................................................... 421
12.4.5 P1IFG Register ................................................................................................. 421
12.4.6 P2IES Register ................................................................................................. 422
12.4.7 P2IE Register ................................................................................................... 422
12.4.8 P2IFG Register ................................................................................................. 422
12.4.9 PxIN Register ................................................................................................... 423
12.4.10 PxOUT Register .............................................................................................. 423
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13.1 Port Mapping Controller Introduction .................................................................................. 426
13.2 Port Mapping Controller Operation .................................................................................... 426
13.2.1 Access ........................................................................................................... 426
13.2.2 Mapping ......................................................................................................... 426
13.3.1 PMAPKEYID Register ......................................................................................... 430
13.3.2 PMAPCTL Register ............................................................................................ 430
13.3.3 PxMAPy Register .............................................................................................. 430
14.1 Cyclic Redundancy Check (CRC) Module Introduction ............................................................. 432
14.2 CRC Standard and Bit Order ........................................................................................... 432
14.3 CRC Checksum Generation ............................................................................................ 433
14.3.1 CRC Implementation .......................................................................................... 433
14.3.2 Assembler Examples .......................................................................................... 434
14.4 CRC Registers ........................................................................................................... 436
14.4.1 CRCDI Register ................................................................................................ 437
14.4.2 CRCDIRB Register ............................................................................................ 437
14.4.3 CRCINIRES Register .......................................................................................... 438
14.4.4 CRCRESR Register ........................................................................................... 438
15 AES Accelerator .............................................................................................................. 439
15.2.1 Encryption ....................................................................................................... 442
15.2.2 Decryption ...................................................................................................... 443
15.2.4 Using the AES Accelerator With Low-Power Modes ...................................................... 445
15.2.5 AES Accelerator Interrupts ................................................................................... 445
15.2.6 Implementing Block Cipher Modes .......................................................................... 445
15.3 AES_ACCEL Registers ................................................................................................. 446
15.3.1 AESACTL0 Register ........................................................................................... 447
15.3.2 AESACTL1 Register ........................................................................................... 448
15.3.3 AESASTAT Register .......................................................................................... 449
15.3.4 AESAKEY Register ............................................................................................ 450
15.3.5 AESADIN Register ............................................................................................. 451
15.3.6 AESADOUT Register .......................................................................................... 451
15.3.7 AESAXDIN Register ........................................................................................... 452
15.3.8 AESAXIN Register ............................................................................................. 452
16.1 WDT_A Introduction ..................................................................................................... 454
16.2 WDT_A Operation ....................................................................................................... 456
16.2.2 Watchdog Mode ................................................................................................ 456
16.2.6 Operation in Low-Power Modes ............................................................................. 457
16.2.7 Software Examples ............................................................................................ 457
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17.2.4 Capture/Compare Blocks ..................................................................................... 467
17.2.5 Output Unit ...................................................................................................... 469
17.2.6 Timer_A Interrupts ............................................................................................. 473
17.3 Timer_A Registers ....................................................................................................... 475
17.3.1 TAxCTL Register ............................................................................................... 476
17.3.2 TAxR Register .................................................................................................. 477
17.3.3 TAxCCTLn Register ........................................................................................... 478
17.3.4 TAxCCRn Register ............................................................................................ 480
17.3.5 TAxIV Register ................................................................................................. 480
17.3.6 TAxEX0 Register ............................................................................................... 481
18.2 Timer_B Operation ....................................................................................................... 485
18.2.5 Output Unit ...................................................................................................... 492
18.2.6 Timer_B Interrupts ............................................................................................. 496
18.3 Timer_B Registers ....................................................................................................... 498
18.3.1 TBxCTL Register ............................................................................................... 499
18.3.2 TBxR Register .................................................................................................. 501
18.3.3 TBxCCTLn Register ........................................................................................... 502
18.3.4 TBxCCRn Register ............................................................................................ 504
18.3.5 TBxIV Register ................................................................................................. 505
18.3.6 TBxEX0 Register ............................................................................................... 506
19.2 Timer_D Operation ...................................................................................................... 511
19.2.2 High-Resolution Generator ................................................................................... 512
19.2.5 PWM Generation ............................................................................................... 518
19.2.7 Compare Mode ................................................................................................. 524
19.2.9 Output Unit ...................................................................................................... 525
19.2.11 Timer_D Interrupts ........................................................................................... 532
19.3 Timer_D Registers ....................................................................................................... 534
19.3.1 TDxCTL0 Register ............................................................................................. 535
19.3.2 TDxCTL1 Register ............................................................................................. 537
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20.2 TEC Operation ........................................................................................................... 549
20.2.4 Module Level Connection Between TEC and Timer_D ................................................... 550
20.2.5 Synchronization Mechanism Between Timer_D Instances ............................................... 552
20.2.6 Timer Event Control Interrupts ............................................................................... 554
20.3 TEC Registers ............................................................................................................ 555
20.3.1 TECxCTL0 Register ........................................................................................... 556
20.3.4 TECxSTA Register ............................................................................................. 561
20.3.5 TECxINT Register ............................................................................................. 562
20.3.6 TECxIV Register ............................................................................................... 563
21.1 RTC Overview ............................................................................................................ 564
22.1 RTC_A Introduction ...................................................................................................... 566
22.2 RTC_A Operation ........................................................................................................ 568
22.2.1 Counter Mode .................................................................................................. 568
22.2.2 Calendar Mode ................................................................................................. 568
22.3 RTC_A Registers ........................................................................................................ 574
22.3.1 RTCCTL0 Register ............................................................................................ 576
22.3.2 RTCCTL1 Register ............................................................................................ 577
22.3.3 RTCCTL2 Register ............................................................................................ 578
22.3.4 RTCCTL3 Register ............................................................................................ 578
22.3.5 RTCNT1 Register .............................................................................................. 579
22.3.6 RTCNT2 Register .............................................................................................. 579
22.3.7 RTCNT3 Register .............................................................................................. 579
22.3.8 RTCNT4 Register .............................................................................................. 579
22.3.15 RTCDOW Register – Calendar Mode ..................................................................... 583
22.3.16 RTCDAY Register – Calendar Mode With Hexadecimal Format ...................................... 583
22.3.17 RTCDAY Register – Calendar Mode With BCD Format ................................................ 583
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22.3.28 RTCADOW Register ......................................................................................... 589
22.3.31 RTCPS0CTL Register ....................................................................................... 590
22.3.33 RT0PS Register .............................................................................................. 592
22.3.34 RT1PS Register .............................................................................................. 592
22.3.35 RTCIV Register ............................................................................................... 592
23.2 RTC_B Operation ........................................................................................................ 596
23.2.2 Real-Time Clock Alarm Function ............................................................................ 596
23.2.3 Reading or Writing Real-Time Clock Registers ............................................................ 597
23.2.4 Real-Time Clock Interrupts ................................................................................... 597
23.2.5 Real-Time Clock Calibration .................................................................................. 599
23.2.6 Real-Time Clock Operation in LPMx.5 Low-Power Mode ................................................ 600
23.3 RTC_B Registers ........................................................................................................ 601
23.3.1 RTCCTL0 Register ............................................................................................ 603
23.3.2 RTCCTL1 Register ............................................................................................ 604
23.3.3 RTCCTL2 Register ............................................................................................ 605
23.3.4 RTCCTL3 Register ............................................................................................ 605
23.3.11 RTCDOW Register ........................................................................................... 609
23.3.22 RTCADOW Register ......................................................................................... 614
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24.2 RTC_C Operation ........................................................................................................ 624
24.2.1 Calendar Mode ................................................................................................. 624
24.2.3 Real-Time Clock Alarm Function ............................................................................ 624
24.2.4 Real-Time Clock Protection .................................................................................. 625
24.2.5 Reading or Writing Real-Time Clock Registers ........................................................... 625
24.2.6 Real-Time Clock Interrupts ................................................................................... 626
24.2.7 Real-Time Clock Calibration for Crystal Offset Error ...................................................... 628
24.2.8 Real-Time Clock Compensation for Crystal Temperature Drift .......................................... 628
24.2.9 Real-Time Clock Operation in LPM3.5 Low-Power Mode ................................................ 631
24.3 RTC_C Operation - Device-Dependent Features ................................................................... 632
24.3.1 Counter Mode .................................................................................................. 632
24.4 RTC_C Registers ........................................................................................................ 635
24.4.1 RTCCTL0_L Register ......................................................................................... 638
24.4.2 RTCCTL0_H Register ......................................................................................... 639
24.4.3 RTCCTL1 Register ............................................................................................ 640
24.4.4 RTCCTL3 Register ............................................................................................ 641
24.4.5 RTCOCAL Register ............................................................................................ 641
24.4.6 RTCTCMP Register ........................................................................................... 642
24.4.7 RTCNT1 Register .............................................................................................. 643
24.4.8 RTCNT2 Register .............................................................................................. 643
24.4.9 RTCNT3 Register .............................................................................................. 643
24.4.10 RTCNT4 Register ............................................................................................ 643
24.4.17 RTCDOW Register – Calendar Mode ..................................................................... 647
24.4.18 RTCDAY Register – Calendar Mode With Hexadecimal Format ...................................... 647
24.4.19 RTCDAY Register – Calendar Mode With BCD Format ................................................ 647
24.4.20 RTCMON Register – Calendar Mode With Hexadecimal Format ...................................... 648
24.4.21 RTCMON Register – Calendar Mode With BCD Format ................................................ 648
24.4.22 RTCYEAR Register – Calendar Mode With Hexadecimal Format ..................................... 649
24.4.23 RTCYEAR Register – Calendar Mode With BCD Format .............................................. 649
24.4.24 RTCAMIN Register – Calendar Mode With Hexadecimal Format ..................................... 650
24.4.25 RTCAMIN Register – Calendar Mode With BCD Format ............................................... 650
24.4.26 RTCAHOUR Register ........................................................................................ 651
24.4.28 RTCADOW Register – Calendar Mode ................................................................... 652
24.4.29 RTCADAY Register – Calendar Mode With Hexadecimal Format ..................................... 652
24.4.30 RTCADAY Register – Calendar Mode With BCD Format .............................................. 652
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24.4.50 RTCTCCTL0 Register ....................................................................................... 665
24.4.51 RTCTCCTL1 Register ....................................................................................... 665
24.4.52 RTCCAPxCTL Register ..................................................................................... 666
25.1 32-Bit Hardware Multiplier (MPY32) Introduction .................................................................... 668
25.2 MPY32 Operation ........................................................................................................ 670
25.2.1 Operand Registers ............................................................................................. 671
25.2.2 Result Registers ................................................................................................ 672
25.2.3 Software Examples ............................................................................................ 673
25.2.4 Fractional Numbers ............................................................................................ 674
25.2.6 Indirect Addressing of Result Registers ..................................................................... 680
25.2.7 Using Interrupts ................................................................................................ 680
25.2.8 Using DMA ...................................................................................................... 681
25.3 MPY32 Registers ........................................................................................................ 682
25.3.1 MPY32CTL0 Register ......................................................................................... 684
26.2.1 Low-Power Operation ......................................................................................... 688
26.3 REF Registers ............................................................................................................ 692
27 ADC10_A ........................................................................................................................ 695
27.2.2 ADC10_A Inputs and Multiplexer ............................................................................ 698
27.2.3 Voltage Reference Generator ................................................................................ 699
27.2.4 Auto Power Down .............................................................................................. 699
27.2.5 Sample and Conversion Timing .............................................................................. 699
27.2.6 Conversion Result ............................................................................................. 701
27.2.8 Window Comparator ........................................................................................... 706
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27.2.11 ADC10_A Interrupts .......................................................................................... 708
27.3 ADC10_A Registers ..................................................................................................... 710
27.3.1 ADC10CTL0 Register ......................................................................................... 711
27.3.2 ADC10CTL1 Register ......................................................................................... 712
27.3.3 ADC10CTL2 Register ......................................................................................... 714
27.3.4 ADC10MEM0 Register ........................................................................................ 715
27.3.6 ADC10MCTL0 Register ....................................................................................... 716
27.3.7 ADC10HI Register ............................................................................................. 717
27.3.9 ADC10LO Register ............................................................................................ 718
27.3.11 ADC10IE Register ............................................................................................ 719
27.3.12 ADC10IFG Register .......................................................................................... 720
27.3.13 ADC10IV Register ............................................................................................ 721
28.2.2 ADC12_A Inputs and Multiplexer ............................................................................ 726
28.2.3 Voltage Reference Generator ................................................................................ 727
28.2.4 Auto Power Down .............................................................................................. 728
28.2.5 Sample and Conversion Timing .............................................................................. 728
28.2.6 Conversion Memory ........................................................................................... 730
28.2.8 Using the Integrated Temperature Sensor ................................................................. 736
28.2.9 ADC12_A Grounding and Noise Considerations .......................................................... 737
28.2.10 ADC12_A Interrupts .......................................................................................... 738
28.3 ADC12_A Registers ..................................................................................................... 740
28.3.1 ADC12CTL0 Register ......................................................................................... 742
28.3.2 ADC12CTL1 Register ......................................................................................... 744
28.3.3 ADC12CTL2 Register ......................................................................................... 745
28.3.4 ADC12MEMx Register ........................................................................................ 746
28.3.5 ADC12MCTLx Register ....................................................................................... 747
28.3.6 ADC12IE Register ............................................................................................. 748
28.3.7 ADC12IFG Register ........................................................................................... 750
28.3.8 ADC12IV Register ............................................................................................. 752
29.2.2 ADC Core ....................................................................................................... 759
29.2.3 Voltage Reference ............................................................................................. 759
29.2.4 Modulator Clock ................................................................................................ 759
29.2.5 Auto Power-Down .............................................................................................. 759
29.2.6 Analog Inputs ................................................................................................... 759
29.2.7 Digital Filter ..................................................................................................... 760
29.2.9 Conversion Modes ............................................................................................. 764
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29.3 SD24_B Registers ....................................................................................................... 770
29.3.1 SD24BCTL0 Register ......................................................................................... 772
29.3.2 SD24BCTL1 Register ......................................................................................... 774
29.3.3 SD24BTRGCTL Register ..................................................................................... 775
29.3.4 SD24BIFG Register ........................................................................................... 776
29.3.5 SD24BIE Register ............................................................................................. 779
29.3.6 SD24BIV Register ............................................................................................. 781
29.3.7 SD24BCCTLx Register ........................................................................................ 782
29.3.8 SD24BINCTLx Register ....................................................................................... 784
29.3.9 SD24BOSRx Register ......................................................................................... 785
29.3.10 SD24BTRGOSR Register ................................................................................... 785
29.3.11 SD24BPREx Register ........................................................................................ 786
29.3.12 SD24BTRGPRE Register ................................................................................... 786
29.3.13 SD24BMEMLx Register ..................................................................................... 787
29.3.14 SD24BMEMHx Register ..................................................................................... 787
30.2.3 DAC12_A Reference .......................................................................................... 792
30.2.5 DAC12_xDAT Data Formats ................................................................................. 793
30.2.6 DAC12_A Output Amplifier Offset Calibration ............................................................. 793
30.2.7 Grouping Multiple DAC12_A Modules ...................................................................... 794
30.2.8 DAC12_A Interrupts ........................................................................................... 795
30.3 DAC Outputs .............................................................................................................. 796
30.4 DAC12_A Registers ..................................................................................................... 797
30.4.1 DAC12_xCTL0 Register ...................................................................................... 798
30.4.2 DAC12_xCTL1 Register ...................................................................................... 800
30.4.3 DAC12_xDAT Register, Unsigned 12-Bit Binary Format, Right Justified .............................. 801
30.4.4 DAC12_xDAT Register, Unsigned 12-Bit Binary Format, Left Justified ................................ 801
30.4.5 DAC12_xDAT Register, 2s-Complement 12-Bit Binary Format, Right Justified ....................... 802
30.4.6 DAC12_xDAT Register, 2s-Complement 12-Bit Binary Format, Left Justified ......................... 802
30.4.7 DAC12_xDAT Register, Unsigned 8-Bit Binary Format, Right Justified ................................ 803
30.4.8 DAC12_xDAT Register, Unsigned 8-Bit Binary Format, Left Justified .................................. 803
30.4.9 DAC12_xDAT Register, 2s-Complement 8-Bit Binary Format, Right Justified ........................ 804
30.4.10 DAC12_xDAT Register, 2s-Complement 8-Bit Binary Format, Left Justified ......................... 804
30.4.11 DAC12_xCALCTL Register ................................................................................. 805
30.4.12 DAC12_xCALDAT Register ................................................................................. 805
30.4.13 DAC12IV Register ............................................................................................ 806
31.2.3 Port Logic ....................................................................................................... 809
31.2.5 Output Filter .................................................................................................... 810
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31.2.8 Comp_B Interrupts ............................................................................................. 812
31.3 Comp_B Registers ....................................................................................................... 814
31.3.1 CBCTL0 Register .............................................................................................. 815
31.3.2 CBCTL1 Register .............................................................................................. 816
31.3.3 CBCTL2 Register .............................................................................................. 818
31.3.4 CBCTL3 Register .............................................................................................. 819
31.3.5 CBINT Register ................................................................................................ 821
31.3.6 CBIV Register .................................................................................................. 822
32 LCD_B Controller ............................................................................................................. 823
32.2.1 LCD Memory ................................................................................................... 826
32.2.4 LCD Blinking .................................................................................................... 827
32.2.6 LCD Outputs .................................................................................................... 830
32.2.7 LCD_B Interrupts .............................................................................................. 830
32.2.8 Static Mode ..................................................................................................... 832
32.2.9 2-Mux Mode .................................................................................................... 835
32.2.10 3-Mux Mode ................................................................................................... 838
32.2.11 4-Mux Mode ................................................................................................... 841
32.3 LCD_B Registers ......................................................................................................... 844
32.3.1 LCDBCTL0 Register ........................................................................................... 847
32.3.2 LCDBCTL1 Register ........................................................................................... 848
32.3.3 LCDBBLKCTL Register ....................................................................................... 849
32.3.4 LCDBMEMCTL Register ...................................................................................... 850
32.3.5 LCDBVCTL Register .......................................................................................... 851
32.3.6 LCDBPCTL0 Register ......................................................................................... 853
32.3.10 LCDBCPCTL Register ....................................................................................... 855
32.3.11 LCDBIV Register ............................................................................................. 856
33 LCD_C Controller ............................................................................................................. 857
33.1 LCD_C Introduction ...................................................................................................... 858
33.2 LCD_C Operation ........................................................................................................ 860
33.2.1 LCD Memory ................................................................................................... 860
33.2.4 LCD Blinking .................................................................................................... 862
33.2.6 LCD Outputs .................................................................................................... 866
33.2.7 LCD Interrupts .................................................................................................. 867
33.2.8 Static Mode ..................................................................................................... 869
33.2.9 2-Mux Mode .................................................................................................... 870
33.2.10 3-Mux Mode ................................................................................................... 871
33.2.11 4-Mux Mode ................................................................................................... 872
33.2.12 6-Mux Mode ................................................................................................... 873
33.2.13 8-Mux Mode ................................................................................................... 874
33.3 LCD_C Registers ........................................................................................................ 876
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34.2 USCI Introduction – UART Mode ...................................................................................... 895
34.3 USCI Operation – UART Mode ........................................................................................ 897
34.3.1 USCI Initialization and Reset ................................................................................. 897
34.3.2 Character Format .............................................................................................. 897
34.3.5 IrDA Encoding and Decoding ................................................................................ 901
34.3.6 Automatic Error Detection .................................................................................... 902
34.3.7 USCI Receive Enable ......................................................................................... 903
34.3.8 USCI Transmit Enable ........................................................................................ 903
34.3.9 UART Baud-Rate Generation ................................................................................ 904
34.3.10 Setting a Baud Rate .......................................................................................... 906
34.3.11 Transmit Bit Timing ........................................................................................... 906
34.3.12 Receive Bit Timing ........................................................................................... 907
34.3.13 Typical Baud Rates and Errors ............................................................................. 908
34.3.14 Using the USCI Module in UART Mode With Low-Power Modes ..................................... 911
34.3.15 USCI Interrupts ............................................................................................... 911
34.4.1 UCAxCTL0 Register ........................................................................................... 914
34.4.3 UCAxBR0 Register ............................................................................................ 916
34.4.4 UCAxBR1 Register ............................................................................................ 916
34.4.5 UCAxMCTL Register .......................................................................................... 916
34.4.6 UCAxSTAT Register ........................................................................................... 917
34.4.7 UCAxRXBUF Register ........................................................................................ 918
34.4.8 UCAxTXBUF Register ......................................................................................... 918
34.4.9 UCAxIRTCTL Register ........................................................................................ 919
34.4.10 UCAxIRRCTL Register ...................................................................................... 919
34.4.11 UCAxABCTL Register ....................................................................................... 920
34.4.12 UCAxIE Register ............................................................................................. 921
34.4.13 UCAxIFG Register ........................................................................................... 921
34.4.14 UCAxIV Register ............................................................................................. 922
35.2 USCI Introduction – SPI Mode ......................................................................................... 925
35.3 USCI Operation – SPI Mode ........................................................................................... 927
35.3.3 Master Mode .................................................................................................... 928
35.3.4 Slave Mode ..................................................................................................... 929
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35.3.7 Using the SPI Mode With Low-Power Modes .............................................................. 930
35.3.8 SPI Interrupts ................................................................................................... 931
35.4.3 UCAxBR0 Register ............................................................................................ 935
35.4.4 UCAxBR1 Register ............................................................................................ 935
35.4.5 UCAxMCTL Register .......................................................................................... 935
35.4.6 UCAxSTAT Register ........................................................................................... 936
35.4.7 UCAxRXBUF Register ........................................................................................ 937
35.4.8 UCAxTXBUF Register ......................................................................................... 937
35.4.9 UCAxIE Register ............................................................................................... 938
35.4.11 UCAxIV Register ............................................................................................. 939
35.5.1 UCBxCTL0 Register ........................................................................................... 941
35.5.3 UCBxBR0 Register ............................................................................................ 943
35.5.4 UCBxBR1 Register ............................................................................................ 943
35.5.5 UCBxMCTL Register .......................................................................................... 943
35.5.6 UCBxSTAT Register ........................................................................................... 944
35.5.7 UCBxRXBUF Register ........................................................................................ 945
35.5.8 UCBxTXBUF Register ......................................................................................... 945
35.5.9 UCBxIE Register ............................................................................................... 946
35.5.10 UCBxIFG Register ........................................................................................... 946
35.5.11 UCBxIV Register ............................................................................................. 947
36.2 USCI Introduction – I2C Mode .......................................................................................... 950
36.3 USCI Operation – I2C Mode ............................................................................................ 951
36.3.2 I2C Serial Data .................................................................................................. 952
36.3.3 I2C Addressing Modes ......................................................................................... 954
36.3.4 I2C Module Operating Modes ................................................................................. 955
36.3.5 I2C Clock Generation and Synchronization ................................................................. 966
36.3.6 Using the USCI Module in I2C Mode With Low-Power Modes ........................................... 967
36.3.7 USCI Interrupts in I2C Mode .................................................................................. 967
36.4 USCI_B I2C Mode Registers ........................................................................................... 970
36.4.3 UCBxBR0 Register ............................................................................................ 973
36.4.4 UCBxBR1 Register ............................................................................................ 973
36.4.5 UCBxSTAT Register ........................................................................................... 974
36.4.6 UCBxRXBUF Register ........................................................................................ 975
36.4.7 UCBxTXBUF Register ......................................................................................... 975
36.4.8 UCBxI2COA Register ......................................................................................... 976
36.4.9 UCBxI2CSA Register .......................................................................................... 976
36.4.10 UCBxIE Register ............................................................................................. 977
36.4.11 UCBxIFG Register ........................................................................................... 978
36.4.12 UCBxIV Register ............................................................................................. 979
37 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode ........................... 980
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37.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview .................................. 981
37.2 eUSCI_A Introduction – UART Mode ................................................................................. 981
37.3 eUSCI_A Operation – UART Mode .................................................................................... 983
37.3.1 eUSCI_A Initialization and Reset ............................................................................ 983
37.3.5 IrDA Encoding and Decoding ................................................................................ 987
37.3.6 Automatic Error Detection .................................................................................... 988
37.3.7 eUSCI_A Receive Enable .................................................................................... 989
37.3.8 eUSCI_A Transmit Enable .................................................................................... 989
37.3.9 UART Baud-Rate Generation ................................................................................ 990
37.3.10 Setting a Baud Rate .......................................................................................... 992
37.3.11 Transmit Bit Timing - Error calculation .................................................................... 993
37.3.12 Receive Bit Timing – Error Calculation .................................................................... 993
37.3.13 Typical Baud Rates and Errors ............................................................................. 994
37.3.14 Using the eUSCI_A Module in UART Mode With Low-Power Modes ................................. 996
37.3.15 eUSCI_A Interrupts .......................................................................................... 996
37.4.1 UCAxCTLW0 Register ........................................................................................ 999
37.4.2 UCAxCTLW1 Register ....................................................................................... 1000
37.4.3 UCAxBRW Register .......................................................................................... 1001
37.4.4 UCAxMCTLW Register ...................................................................................... 1001
37.4.5 UCAxSTATW Register ....................................................................................... 1002
37.4.6 UCAxRXBUF Register ....................................................................................... 1003
37.4.7 UCAxTXBUF Register ....................................................................................... 1003
37.4.8 UCAxABCTL Register ....................................................................................... 1004
37.4.9 UCAxIRCTL Register ........................................................................................ 1005
37.4.10 UCAxIE Register ............................................................................................ 1006
37.4.11 UCAxIFG Register .......................................................................................... 1007
37.4.12 UCAxIV Register ............................................................................................ 1008
38 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode ............................. 1009
38.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview ..................... 1010
38.2 eUSCI Introduction – SPI Mode ...................................................................................... 1010
38.3 eUSCI Operation – SPI Mode ........................................................................................ 1012
38.3.1 eUSCI Initialization and Reset .............................................................................. 1012
38.3.2 Character Format ............................................................................................. 1013
38.3.3 Master Mode .................................................................................................. 1013
38.3.4 Slave Mode .................................................................................................... 1014
38.3.5 SPI Enable .................................................................................................... 1015
38.3.7 Using the SPI Mode With Low-Power Modes ............................................................ 1016
38.3.8 SPI Interrupts ................................................................................................. 1016
38.4.1 UCAxCTLW0 Register ....................................................................................... 1019
38.4.2 UCAxBRW Register .......................................................................................... 1021
38.4.3 UCAxSTATW Register ....................................................................................... 1022
38.4.4 UCAxRXBUF Register ....................................................................................... 1023
38.4.5 UCAxTXBUF Register ....................................................................................... 1024
38.4.6 UCAxIE Register ............................................................................................. 1025
38.4.8 UCAxIV Register ............................................................................................. 1027
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39 Enhanced Universal Serial Communication Interface (eUSCI) – I2C Mode .............................. 1035
39.1 Enhanced Universal Serial Communication Interface B (eUSCI_B) Overview ................................. 1036
39.2 eUSCI_B Introduction – I2C Mode .................................................................................... 1036
39.3 eUSCI_B Operation – I2C Mode ...................................................................................... 1037
39.3.1 eUSCI_B Initialization and Reset ........................................................................... 1038
39.3.2 I2C Serial Data ................................................................................................ 1038
39.3.3 I2C Addressing Modes ....................................................................................... 1039
39.3.4 I2C Quick Setup ............................................................................................... 1040
39.3.5 I2C Module Operating Modes ............................................................................... 1041
39.3.6 Glitch Filtering ................................................................................................. 1051
39.3.8 Byte Counter .................................................................................................. 1052
39.3.9 Multiple Slave Addresses ................................................................................... 1053
39.3.10 Using the eUSCI_B Module in I2C Mode With Low-Power Modes ................................... 1054
39.3.11 eUSCI_B Interrupts in I2C Mode .......................................................................... 1054
39.4 eUSCI_B I2C Registers ................................................................................................ 1057
39.4.1 UCBxCTLW0 Register ....................................................................................... 1058
39.4.2 UCBxCTLW1 Register ....................................

msp430x5xx _msp430x6xx

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