MSc in Digital Systems Engineering

Introduction to Logic Design with VHDL

Laboratory Session 1: Introduction to Modelsim

October 2010

Contents

1 Introduction to Modelsim 11.1 Prerequisites for Lab 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Remarks on VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Starting Modelsim and Creating a New VHDL Project . . . . . . . . . . 21.4 Adding Existing Files to the Project . . . . . . . . . . . . . . . . . . . . 21.5 Implementation and Testbench: Why Two Files? . . . . . . . . . . . . . 41.6 Setting Up and Running a Simulation . . . . . . . . . . . . . . . . . . . 51.7 Exporting Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.8 Adding VHDL Sources of Another Example: D Flip-Flop . . . . . . . . . 81.9 Simulating the New Example: D Flip-Flop . . . . . . . . . . . . . . . . . 91.10 Observations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.11 Bonus Material: Implementing a Custom Logic Gate or Function . . . . . 10

1.11.1 Adding a Template VHDL Module and Testbench . . . . . . . . 101.11.2 Simulating the Customised Example . . . . . . . . . . . . . . . . 10

1.12 What you have learned . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

I

Lab 1

Introduction to Modelsim

Lab1 will provide an introduction to Modelsim, an industry standard VHDL de-sign and simulation environment. The aims of the first lab are to enable you to:

• run Modelsim and create a project including VHDL source files.• include VHDL testbenches for VHDL modules in your project.• setup and run a simulation of given examples of combinational and se-

quential circuits.• use template VHDL files to implement your own custom logic function and

simulate it.

1.1 Prerequisites for Lab 1

If the PC in front of you is running and allows you to login, the hard part of setting up forLab1 is already done. You will be asked for a number of VHDL source files during thisintroduction to Modelsim. You can download a zip archive containing those files from:

http://www-users.york.ac.uk/∼mt540/vhdl labs/Unfortunately, copy paste does not work on this URL because of special characters.

• Use Windows Explorer to browse to drive H:/.• Create a new folder with the name vhdl labs.• Inside the folder vhdl labs, create two additional folders workspace and Lab1 download.• Run your favourite internet browser and enter the URL from above.• You should now see a list of zip-files in your internet browser window.• (Right-)click on the file vhdl lab1.zip and save it to Lab1 download.

1

1.2 Remarks on VHDL

• Go back to Windows Explorer and open the folder Lab1 download.• Right-click on vhdl lab1.zip and select extract.• You should end up with a number of VHDL source files inH:/vhdl labs/Lab1 download/.

With Modelsim you will be working in H:vhdl labs/workspace/. All files inthis folder will be organised using Modelsim. Do not confuse workspace withLab1 download! The files in the latter folder should remain unchanged. Files weare working with will always be copied to workspace.

1.2 Remarks on VHDL

• VHDL is not case sensitive, which makes it hard to follow coding conventionssometimes. So please try to keep a consistent style for a better overview.

• Names and identifiers cannot start with a number nor an underscore.• Under some conditions names do not support dashes in their names, so it is best to

just avoid them.• Those of you who are familiar with hardware design languages (HDLs) will find

that VHDL is a very verbouse language, so have a close look at the example filesin order to get used to the structure of VHDL entities.

1.3 Starting Modelsim and Creating a New VHDL Project

ModelSim is the program used to manage and simulate digital components and circuits(entities) implemented in VHDL. It also features a built-in VHDL editor that allows tochange existing entities and to develop new ones.

Linux> vsim

WindowsStart -> (All) Programs -> Modelsim SE 6.5b -> Modelsim

You should see the ModelSim GUI starting up. If there is an info/welcome window pop-ping up, close it.

The next step is to create a new project, which will later contain the files that containVHDL entities.

File -> New -> Project

This will bring up the Create Project dialogue shown in Figure 1.1.

• Enter a project name, i.e. labcourse.

2

Introduction to Modelsim

• Browse to the project location H:/vhdl labs/workspace/, which you havecreated in Section 1.1.

• Click OK.

Figure 1.1: Create Project dialogue.

1.4 Adding Existing Files to the Project

You will now see the dialogue box from Figure 1.2.

• Click on Create New Folder and create a new folder called Lab1.• Click on Add Existing File.

Figure 1.2: Add items to the project dialogue.

In the now appearing Add file to project dialogue box (Figure 1.3),

• Enter a file name by browsing to the H:/vhdl labs/Lab1 download/ folder that wehave copied in Section 1.1, and selecting the file or.vhdl.

3

1.5 Implementation and Testbench: Why Two Files?

• Select the folder Lab1 from the drop-down box Folder.• Make sure the radio button Copy to project directory is selected.• Click OK.

Figure 1.3: Add file to the project dialogue.

Repeat the Add existing file step for the file or tb.vhdl, which is also in theLab1 download folder from Section 1.1, and hit Close. We are now ready to simulatethe OR gate!

If creating a new project and adding the VHDL code for a logic OR gate was success-full, the Project window on the left should look similar to the one in Figure 1.4

Figure 1.4: Project window.

1.5 Implementation and Testbench: Why Two Files?

One of the two files (or.vhdl) that we have just added to the project contains the actualimplementation of a logic OR gate in VHDL. The second file (or tb.vhdl) provides aso-called VHDL testbench, which is required to test the functionality of the logic OR gatefrom the first file. VHDL entities can be regarded as generic electronic components—justlike, for instance, logic gates, counters, registers—that (should!) contain no informationabout what kind of signal sequence will be applied to their inputs, since they have to besuitable to be inserted at multiple different places within larger circuits.

However, in order to implement and test a VHDL entity, it is required to apply varioussequences of inputs and monitor the outputs. Hence the purpose of the testbench is to

4

Introduction to Modelsim

provide input signals that ideally cover all modes of operation of the entity under test.Input and output signals are usually displayed as waveforms, as shown in Section 1.6.

The main reasons for keeping implementation and testbench in separate files are there-fore:

• It is good design practice to provide a separate testbench for each entity.• Testbenches are helpful when building and testing large systems that consist of a

large number of entities.

In order to get a better idea of how the implementation and the testbench of the logicOR gate work, it is useful to have a look at the VHDL code. Modelsim has got a built-inVHDL editor. You can open and edit any VHDL source file in the project:

• Select the tab Project in the Project window.• Right-click on or.vhdl.• Click on Edit.• Right-click on or tb.vhdl.• Click on Edit.• Examine the two VHDL source files and match them with what you have learned

in the lectures.

This will open the VHDL source files in the window next to the Project in new tabs.

.

You can keep multiple files open at the same time, each on its own tab. Click on thetab of the file you want to look at in order to raise it to the foreground.

1.6 Setting Up and Running a Simulation

It is necessary to compile the VHDL code, before the simulation can be run. Select thefolder Lab1 in the Project window and compile:

Compile -> Compile All

The Transcript window at the bottom shold report something like this, if compilation wassuccessful:

# Compile of or.vhdl was successful.# Compile of or tb.vhdl was successful.# 2 compiles, 0 failed with no errors.

In addition to this the blue questionmarks behind the filenames in the Project window(Figure 1.4) should become green ticks and a new tab Library should appear next toProject

5

1.6 Setting Up and Running a Simulation

.

Note that there are now at least two tabs, namely Project and Library. The Project tabcontains all VHDL source files of your project, while the Library tab only shows yoursuccessfully compiled VHDL modules (under work) alongside some libraries that areprovided by Modelsim and which provide VHDL functions.It is important to note that even if you delete a VHDL source file from disk, which youhave previously compiled into the work library, it will still be there to use and run simula-tions. Take a moment and try to understand how what is shown in the Project and Librarytabs relates to files and file structure in your workspace folder.

• Click on Library.• Click on the little ’+’ sign next to work, in order to see the list of files in that library.• Note that all our files will be compiled into the work library.• Select the entry with the entity or gate tb.• Do a right-click and select Simulate.

This will result in more tabs, as shown below, create an empty waveform window onthe right and automatically take you to the sim tab.

.

Right-click or gate tb -> Add -> To Wave -> All items in region.Do not click any of the other two options for now!

The screen should now look similar to this:

.

• Change the value in the small white box at the top from 100 ns to 400 ns.

6

Introduction to Modelsim

• Simulate -> Run -> Run 100

This will simulate the circuit over a period of 400 ns. Everytime you repeat runningthe simulation, the waveform will be extended by another 400 ns. In case you want torestart the simulation, click

Simulate -> Run -> Restart and Restart.

In case you want to end the simulation session and clear the waveform window, click

Simulate -> End Simulation and OK.

Your waveform window should now look like this:

.

• If you click within the waveform window, a yellow cursor will appear. This facil-itates examining the simulation outcome. The values of all signals at the selectedpoint in time are shown on the left of the waveform.

• Note the control buttons right above the waveform window.

• Play with the magnifying glasses , that allow you to zoom in andout of the waveform.

• Select/Highlight one of the signals, e.g. b tb.

• These two buttons allow to find and jump to the next/previoustransition.

• Use this feature to check whether your OR gate works correctly (which it shoulddo!).

• The marker buttons allow to create a number of markers, which can be usedto measure delays or monitor different points in time.

• You can also add and remove markers with the group of small buttons to the lower

left of the waveform window .

7

1.7 Exporting Waveforms

• Note: you can measure time differences between slopes using two or more markers.• Note: the top left button of the group of small buttons allows you to toggle between

displaying between short and full names of the signals in the waveform window.The short form might provide a better overview, in the case of a large number ofsignals.

Simulate -> End Simulation and Yes.

Terminates the current simulation. The waveform window has to be closed separately, ifdesired. The active simulation has to be terminated before it will be possible to simulateanother module.

1.7 Exporting Waveforms

You might want to save or export your waveform in order to include it in a report or pre-sentation. This can be achieved with

File -> Export -> Image.

So far, the only available format is a bitmap (BMP). Check how the exported waveformlooks like using Windows Explorer. Note that the default directory where exported BMPsend up is H:/vhdl labs/workspace/.

1.8 Adding VHDL Sources of Another Example: D Flip-Flop

For larger designs, it will be necessary to manage a number of different modules withinthe same VHDL project and still simulate them separately. Therefore, the next step willbe to include another set of files that contain another example.

• Repeat the steps from Section 1.4with the files d-flip-flop.vhdl and d-flip-flop tb.vhdl.

• Remember to compile the new VHDL source files:Compile -> Compile All

What happens now is what usually happens when the VHDL source code is compiled forthe first time: there are errors!

The compiler messages from the Transcript window (see below on the left) will helpto find and correct the errors:

• The files that contain errors are highlighted in red.• Double-click on the error to bring up a more detailed error message (see below on

the right).

8

Introduction to Modelsim

• The error report provides the line number, where the error has occurred. In mostcases, this will already be enough to help you correcting the error when you lookat the code.

• This error message says: near ‘‘)’’: expecting: IDENTIFIER.

• What the error message means is that there is something missing or too much rightbefore or after the “)” in line 17 of the VHDL source file d-flip-flop.vhdl.

• Can you spot the error? Remember to right-click and select Edit on thesource file to open it in the editor.

. .

After you have corrected the error, save the file and compile again.

File -> SaveNOTE: Ctrl-S might not always work in Modelsim!Compile -> Compile All.

To spice things up, there is another error in d-flip-flop.vhdl.Can you find and fix it?

1.9 Simulating the New Example: D Flip-Flop

• Make sure you have added and compiled the VHDL source files for the D Flip-Flopto the Modelsim project.

• Terminate all previous simulation sessions:Simulate -> End Simulation and Yes

• Select the Library tab in your Project window.

• Right-click on the entity dff tb and click Simulate.

• Follow the instructions from Section 1.6.

• Note that the d-type flip-flop has more input/output signals than the logic OR gate!

9

1.10 Observations

1.10 Observations

• What is the main difference between the two examples?

• What major effect has this on the structure of the test bench?

• Can you already guess why it is necessary/useful to keep entity and testbench sep-arate?

• In the case of the D-Type Flip-Flop, is there something odd in the waveform?

1.11 Bonus Material: Implementing a Custom Logic Gate orFunction

This section is intended for all who reach this point and still have a good amount of timeleft, or you can do this outside the lab seminar. The idea is to include another set offiles into your Modelsim project. Those files will be different as it will not be possible tocompile them without making any changes. You will find hints in the comments of whathas to be filled in or changed in order to implement your own custom entity in VHDL!

1.11.1 Adding a Template VHDL Module and Testbench

• First, go to the folder that contains the examples that you have extracted in Sec-tion 1.1.

• Create copies of the files template.vhdl and template tb.vhdl. Picksensible names that reflect the function you plan to implement!

• Add the renamed template files to your project.

• Select the Project tab of your Project window and double-click on the VHDL fileyou wish to open in the VHDL editor.

• Also take a look at the working OR Gate and D-Type Flip-Flop examples of Lab1and see how they are done.

• Open the new template files and look for hints in the comments.

• Implement your favourite logic function in VHDL!

• Compile -> Compile Alland check the error messages in the Transcript window.

• Clicking on the error messages should give you more information of what causedthe error.

1.11.2 Simulating the Customised Example

Once your new modules compile without syntactical error, you will be able to simulatethem and check whether the functionality is also correct. Just follow the same procedureas in Section 1.6, using your own files (implementation and testbench) instead.

10

Introduction to Modelsim

1.12 What you have learned

After the first lab session you should:

• have a basic understanding of how Modelsim works.• be able to explain what a VHDL testbench is, how it works and why it is required.• be able to go through the whole Modelsim workflow, from source files to waveform,

on your own using the provided example VHDL source files.• know how to find and correct simple errors using the Modelsim VHDL compiler.• be able to examine the output of an entity using the waveform window and its tools:

markers, zoom, jump to next transition.

Ideally, before lab2, you should have accomplished the bonus Section 1.11. You shouldbe able to find everything you need to do this in your lecture notes and Lab1 script.

11