mrisc32 instruction set manual version 2021- draft · 1.5.1 instruction word elds the eld names...

MRISC32 Instruction Set Manual

Version 2021-draft

Marcus Geelnard, [email protected]

Preface

This document describes the MRISC32 instruction setarchitecture.

This work is licensed under the Creative CommonsAttribution-ShareAlike 4.0 International License.

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Contents

Preface i

1 Introduction 1

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2.1 Size types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2.2 Integer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2.3 Fixed point types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2.4 Floating-point types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Pseudocode syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3.1 Pseudocode scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3.2 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.4 Assembler syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.5 Instruction encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.5.1 Instruction word �elds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.5.2 Format A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.5.3 Format B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.5.4 Format C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.5.5 Format D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.5.6 Format E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.5.7 Future extensions and encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.6 Architecture modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

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2 Base architecture 6

2.1 Scalar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1.1 The Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1.2 The LR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1.3 The VL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1.4 TP, FP and SP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 The program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Vector operation module (VM) 8

3.1 Vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1.1 The VZ register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Vector operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 Vector length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4 Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Packed operation module (PM) 9

4.1 Packed data operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1.1 Word mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1.2 Half-word mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1.3 Byte mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1.4 Packed �oating-point operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Floating-point module (FM) 10

6 Saturating and halving arithmetic module (SM) 11

7 Instructions 12

7.1 Load and store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.1.1 LDB - Load signed byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.1.2 LDH - Load signed half-word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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7.1.3 LDW - Load word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.1.4 LDWPC - Load word PC-relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.1.5 LDUB - Load unsigned byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.1.6 LDUH - Load unsigned half-word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.1.7 LDEA - Load e�ective address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.1.8 STB - Store byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.1.9 STH - Store half-word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.1.10 STW - Store word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.1.11 STWPC - Store word PC-relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.1.12 LDLI - Load low immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.1.13 LDHI - Load high immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.2 Bitwise logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.2.1 AND - Bitwise and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.2.2 OR - Bitwise or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.2.3 XOR - Bitwise exclusive or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.2.4 EBF - Extract bit �eld . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2.5 EBFU - Extract bit �eld unsigned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2.6 MKBF - Make bit �eld . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.2.7 SEL - Bitwise select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.3 Integer arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.3.1 ADD - Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.3.2 SUB - Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.3.3 MUL - Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.3.4 MULHI - Signed multiply high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.3.5 MULHIU - Unsigned multiply high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.3.6 DIV - Signed divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.3.7 DIVU - Unsigned divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.3.8 REM - Signed remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3.9 REMU - Unsigned remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3.10 MIN - Signed minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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7.3.11 MAX - Signed maxiumum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3.12 MINU - Unsigned minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.3.13 MAXU - Unsigned maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.3.14 ADDPCHI - Add PC high immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.4 Integer comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.4.1 SEQ - Set if equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.4.2 SNE - Set if not equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.4.3 SLT - Set if less than . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.4.4 SLTU - Set if less than unsigned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.4.5 SLE - Set if less than or equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.4.6 SLEU - Set if less than or equal unsigned . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.5 Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.5.1 BZ - Branch if zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.5.2 BNZ - Branch if not zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.5.3 BS - Branch if set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.5.4 BNS - Branch if not set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.5.5 BLT - Branch if less than . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.5.6 BGE - Branch if greater than or equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.5.7 BLE - Branch if less than or equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.5.8 BGT - Branch if greater than . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.5.9 J - Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.5.10 JL - Jump and link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.6 Floating-point arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.6.1 FADD - Floating-point add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.6.2 FSUB - Floating-point subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.6.3 FMUL - Floating-point multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.6.4 FDIV - Floating-point divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.6.5 FMIN - Floating-point minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.6.6 FMAX - Floating-point maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.7 Floating-point comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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7.7.1 FSEQ - Floating-point set if equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.7.2 FSNE - Floating-point set if not equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.7.3 FSLT - Floating-point set if less than . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.7.4 FSLE - Floating-point set if less than or equal . . . . . . . . . . . . . . . . . . . . . . . . 31

7.7.5 FSUNORD - Floating-point set if unordered . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.7.6 FSORD - Floating-point set if ordered . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.8 Floating-point conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.8.1 ITOF - Signed integer to �oating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.8.2 UTOF - Unsigned integer to �oating-point . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.8.3 FTOI - Floating-point to signed integer . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.8.4 FTOU - Floating-point to unsigned integer . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.8.5 FTOIR - Floating-point to signed integer with rounding . . . . . . . . . . . . . . . . . . . 34

7.8.6 FTOUR - Floating-point to unsigned integer with rounding . . . . . . . . . . . . . . . . . 34

7.8.7 FPACK - Floating-point pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.8.8 FUNPL - Floating-point unpack low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.8.9 FUNPH - Floating-point unpack high . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.9 Saturating and halving arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.9.1 ADDS - Signed add with saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.9.2 ADDSU - Unsigned add with saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.9.3 ADDH - Signed half add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.9.4 ADDHU - Unsigned half add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.9.5 ADDHR - Signed half add with rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.9.6 ADDHUR - Unsigned half add with rounding . . . . . . . . . . . . . . . . . . . . . . . . 37

7.9.7 SUBS - Signed subtract with saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.9.8 SUBSU - Unsigned subtract with saturation . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.9.9 SUBH - Signed half subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.9.10 SUBHU - Unsigned half subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.9.11 SUBHR - Signed half subtract with rounding . . . . . . . . . . . . . . . . . . . . . . . . 38

7.9.12 SUBHUR - Unsigned half subtract with rounding . . . . . . . . . . . . . . . . . . . . . . 39

7.9.13 MULQ - Multiply Q-numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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7.9.14 MULQR - Multiply Q-numbers with rounding . . . . . . . . . . . . . . . . . . . . . . . . 39

7.9.15 PACKS - Signed pack with saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.9.16 PACKSU - Unsigned pack with saturation . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.9.17 PACKHIR - Signed pack high with rounding . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.9.18 PACKHIUR - Unsigned pack high with rounding . . . . . . . . . . . . . . . . . . . . . . . 40

7.10 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.10.1 CPUID - CPU identi�cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.10.2 SHUF - Shu�e bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.10.3 PACK - Pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.10.4 PACKHI - Pack high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.10.5 REV - Reverse bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.10.6 CLZ - Count leading zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.10.7 POPCNT - Population count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

A Alphabetical list of instructions 44

B Examples 47

B.1 Vector operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

B.1.1 saxpy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

B.1.2 Linear interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

B.1.3 Reverse bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Chapter 1

Introduction

1.1 Overview

MRISC32 is an open and free instruction set architecture(ISA).

It is a RISC style load-store vector architecture that isdesigned to be simple yet highly scalable.

One of the main features of the instruction set archi-tecture is its forward-looking vector functionality thatnot only integrates well with the rest of the ISA, butalso enables implementations to freely select the level ofhardware parallelism. This makes the vector function-ality suitable for low-end systems like embedded micro-controllers as well as for high-performance computing(HPC).

TODO

Add wording about goals.

1.2 Data types

1.2.1 Size types

The following types de�ne a size without mandating anyparticular interpretation of the data:

Name Sizeword 32 bitshalf-word 16 bitsbyte 8 bits

1.2.2 Integer types

Signed integer types are represented in two's comple-ment form.

Name Size Meaningint32 32 Signed 32-bit integeruint32 32 Unsigned 32-bit integerint16 16 Signed 16-bit integeruint16 16 Unsigned 16-bit integerint8 8 Signed 8-bit integeruint8 8 Unsigned 8-bit integer

1.2.3 Fixed point types

For some operations the �xed point Q number format isused, in which the most signi�cant bit is the integer/signbit, and the rest of the bits are the fractional bits.

Q31

Q31 is a 32-bit signed �xed point number with 31 frac-tional bits.

The value of a Q31 number is obtained by interpret-ing the bit vector as a two's complement signed integermultiplied by 2−31.

03031

I F

Q15

Q15 is a 16-bit signed �xed point number with 15 frac-tional bits.

The value of a Q15 number is obtained by interpret-ing the bit vector as a two's complement signed integermultiplied by 2−15.

01415

I F

1

2

Q7

Q7 is an 8-bit signed �xed point number with 7 frac-tional bits.

The value of a Q7 number is obtained by interpretingthe bit vector as a two's complement signed integer mul-tiplied by 2−7.

067

I F

1.2.4 Floating-point types

Name Size Meaning�oat32 32 Single precision binary �oating-

point number�oat16 16 Half precision binary �oating-

point number�oat8 8 Quarter precision binary �oating-

point number

�oat32

The �oat32 type uses one sign bit (S), eight exponentbits (E) and 23 fractional bits (F)1.

The signi�cand has an implicit leading bit (to the leftof the binary point) with value 1, giving 24 e�ectivesigni�cand bits.

The exponent bias is 127.

0233031

S E F

�oat16

The �oat16 type uses one sign bit (S), �ve exponentbits (E) and ten fractional bits (F)2.

The signi�cand has an implicit leading bit (to the leftof the binary point) with value 1, giving eleven e�ectivesigni�cand bits.


1The �oat32 type uses the same format and interpretation asIEEE 754-2008 binary32

2The �oat16 type uses the same format and interpretation asIEEE 754-2008 binary16

0101415

S E F

�oat8

The �oat8 type uses one sign bit (S), four exponent bits(E) and three fractional bits (F).

The signi�cand has an implicit leading bit (to the leftof the binary point) with value 1, giving four e�ectivesigni�cand bits.


0367

S E F

1.3 Pseudocode syntax

The operation that an instruction performs is describedusing pseudocode.

1.3.1 Pseudocode scope

The pseudocode for each instruction shall be regardedas a function that is executed for each chunk of eachelement of the operation.

For a scalar operation, there is only a single element.

For a vector operation, the number of elements is dic-tated by the vector operation.

The number of chunks and the size of each chunk isdictated by the packed operation mode.

TODO

Describe di�erent types that are used in the pseu-

docode, such as "bit vector", "integer", "unsigned

integer" and "�oat"?

Come up with a better name than "chunk"?

1.3.2 Notation

The following notation is used in the pseudocode thatdescribes the operation of an instruction:

3

Notation Meaningx Bit k of bit vector xx Bits k to l of bit vector xMEM[x,N] N consecutive bytes in memory starting

at address x, interpreted as an 8×N -bitvector with little endian storage

a 1st instruction operandb 2nd instruction operandc 3rd instruction operandIM IM �eld of the instruction wordT T �eld of the instruction wordV Vector mode (two bits)bits Chunk size, in bitsscale Scale factor according to the T �eld (1

for format C instructions)i Vector element number← Assignment+ Addition- Subtraction× Multiplication/ Division% Remainder of integer division= Equal̸= Not equal≤ Less than or equal≥ Greater than or equal¬ Logical not∧ Logical or∨ Logical and~ Bitwise not| Bitwise or& Bitwise and^ Bitwise xor>> Zero-�ll right-shift>s Sticky right-shift (�ll with MSB)

4

Operand types (S for scalar, V for vector) for eachoperand positions relates to the V identi�er as follows(note that load/store instructions always interpret thesecond operand - i.e. the base address - as a scalar):

V Default Load/store00 S,S[,S] S,S,S10 V,V[,S] V,S,S11 V,V,V V,S,V01 V,V,fold(V) V,S,fold(V)

The register �elds Ra, Rb and Rc refer to one scalar orvector register each, according to the OP and V �elds.For instance if a register operand refers to a vector reg-ister, and the corresponding R-�eld has the value 21,then the register operand is V21.

The �rst register operand, Ra, can be a source or adestination register depending on the instruction, whileRb and Rc are always source registers.

The T �eld further de�nes the instruction. For mostinstructions it de�nes the packed data type that is tobe used. For load/store instructions it de�nes a scal-ing factor for the register o�set operand (i.e. the thirdoperand):

T Default Load/store00 One 32-bit word *101 Four 8-bit bytes *210 Two 16-bit half-words *411 (reserved) *8

The IM �eld provides an immediate value. The size ofthe IM �eld depends on the instruction format, and theinterpretation of the �eld further depends on the OPand the H �elds.

The H �eld describes how to interpret a 14-bit IM �eld:

When H=0, the IM value is sign-extended to 32bits.

When H=1, the IM value is shifted to the left 18position, and the least signi�cant bit of the IM �eldis duplicated to the 18 least signi�cant bits of the�nal immediate value.

1.5.2 Format A

Format A instructions are used for instructions that re-quire three register operands, and support both vectorand packed operations.

Format A can encode 124 major instructions(OP ∈ [0, 123]).

1.5.3 Format B

Format B instructions are used for instructions that onlyrequire two register operands (for instance unary oper-ations). Both vector and packed operations are sup-ported.

Format B can encode 256 major instructions(OP ∈ [0, 3], FN ∈ [0, 63]).

1.5.4 Format C

Format C instructions are used for instructions that re-quire two register operands and one immediate operand.Vector operations are supported (but not packed oper-ations).

In general each format C instruction has a correspondingformat A encoding with the same value of the OP �eld.For instance, the instruction ADD exists in both formatA and format C encodings.

Format C can encode 47 major instructions(OP ∈ [1, 47]).

1.5.5 Format D

Format D is used for instructions that need to be ableto express large immediate values.

Format D can encode 7 major instructions(OP ∈ [0, 6]).

1.5.6 Format E

Format E is used for conditional branch instructions.

Format E can encode 8 major instructions (OP ∈ [0, 7]).

1.5.7 Future extensions and encodings

The following table lists the actual and maximum num-ber of instructions per instruction format:

5

Format Count Max UsedA 76 124 61%B 5 256 2%C 29 47 62%D 7 7 100%E 8 8 100%

Encodings with the four most signi�cant bits set to 1110or 1111 are reserved for future encoding formats (orfor extending the number of possible instructions forexisting formats).

As can be seen, there is ample room for adding moreinstructions in future versions of the ISA.

1.6 Architecture modules

The MRISC32 instruction set architecture consists of amandatory base architecture, plus the following optionalarchitecture modules:

Vector operation module (VM) Packed operation module (PM) Floating-point module (FM) Saturating and halving arithmetic module (SM)

Chapter 2

Base architecture

The base architecture is present in all implementationsof the MRISC32 ISA. It primarily provides scalar integerand control �ow instructions, and constitutes the mini-mum requirement for an MRISC32 implementation.

2.1 Scalar registers

There are 32 user addressable scalar registers, each 32bits wide.

031

Z (S0)

S1

S2

...

S25

S26

TP (S27)

FP (S28)

SP (S29)

LR (S30)

VL (S31)

2.1.1 The Z register

Z is a read-only register that is always zero. Writing tothe Z register has no e�ect.

2.1.2 The LR register

LR is the link register, which contains the return addressfor subroutines. It can also be used as a general purposeregister.

2.1.3 The VL register

VL is the vector length register, which de�nes the lengthof vector operations. It can also be used as a generalpurpose register when its value is not used by any vectoroperations.

If an implementation does not supprot the Vector Op-eration Module (VM), the VL register acts as a regulargeneral purpose register.

2.1.4 TP, FP and SP

The scalar registers TP, FP and SP are aliases for S27,S28 and S29, respectively. They have no special mean-ing in hardware, but it is recommended that they areused as follows:

Name DescriptionTP Thread pointer (for thread local storage)FP Frame pointerSP Stack pointer

The registers can also be used as general purpose reg-isters.

2.2 The program counter

The program counter (PC) is an internal register thatholds the memory address of the current instruction.

6

7

There are a few instructions that make use of the valueof the program counter, either directly or indirectly, butother instructions can neither read nor alter the programcounter.

2.3 Memory addressing

TBD

2.4 Exceptions

TBD

Chapter 3

Vector operation module (VM)

The vector operation module adds facilities for vectorprocessing. A set of vector registers is added, and mostinstructions are extended to support processing of vectorregisters.

3.1 Vector registers

There are 32 vector registers:

Vector reg. no Name0 VZ1 V12 V23 V34 V4

...30 V3031 V31

Each register, Vk, consists of N 32-bit elements, whereN is implementation de�ned (N must be a power oftwo, and at least 16):

031

Vk[0]

Vk[1]

Vk[2]

Vk[3]

Vk[4]

...

Vk[N − 2]

Vk[N − 1]

3.1.1 The VZ register

VZ is a read-only register with all vector elements setto zero. Writing to the VZ register has no e�ect.

3.2 Vector operation

A vector operation is performed when a source or des-tination operand of an instruction is a vector register.

TODO

Describe how vector operations process elements

of vector registers.

3.3 Vector length

TODO

Describe how VL a�ects vector operations.

Describe how to obtain the maximum vector length

for an implementation.

3.4 Folding

Horizontal vector operations (e.g. sum and min/max)are supported by repeated folding, where the upper halfof one vector source operand is combined with the lowerhalf of another vector source operand.

TODO

Describe how folding works.

8

Chapter 4

Packed operation module (PM)

The packed operation module adds facilities for paralleloperation on packed data types. Most instructions areextended with packed operation modes, and a few in-structions are added that mainly deal with packing andunpacking of data of di�erent sizes.

4.1 Packed data operation

Many instructions are extended with the ability to op-erate on several individual sub-parts of the source anddestination elements. These sub-parts are referred to aschunks.

A single 32-bit element may be split up into one, two orfour chunks, as follows:

08162431

word

half-word half-word H

byte byte byte byte B

When a packed operation is performed, all chunks withina 32-bit word are processed in parallel. It is not possibleto process only a subset of the chunks.

4.1.1 Word mode

In word mode, which is the defult, each element is pro-cessed as a single 32-bit chunk.

4.1.2 Half-word mode

In half-word mode each element is processed as twoindividual 16-bit chunks in parallel.

In assembly language, half-word mode is indicated byappending the su�x .H to the instruction mnemonic.

4.1.3 Byte mode

In byte mode each element is processed as four individ-ual 8-bit chunks in parallel.

In assembly language, byte mode is indicated by ap-pending the su�x .B to the instruction mnemonic.

4.1.4 Packed �oating-point operation

For �oating-point instructions, using packed operatingmodes implies using �oating-point precisions lower thansingle precision:

Mode Precisionword Single precision �oating-pointhalf-word Half precision �oating-pointbyte Quarter precision �oating-point

9

Chapter 5

Floating-point module (FM)

The �oating-point module adds instructions that op-erate on �oating-point numbers. Both scalar registersand vector registers may be used to hold �oating-pointvalues.

The module supports a subset of the 2008 IEEE-754�oating-point standard [1].

TBD

10

Chapter 6

Saturating and halving arithmeticmodule (SM)

The saturating and halving arithmetic module adds in-structions that perform arithmetic operations on �xedpoint numbers.

TBD

11

Chapter 7

Instructions

This chapter describes all the instructions of theMRISC32 instruction set.

Instruction variants with a .B (packed byte) or .H(packed half-word) mnemonic su�x are only availablein architectures that implement the Packed operationmodule (PM).

Instruction variants that include vector register operandsare only available in architectures that implement theVector operation module (VM).

7.1 Load and store

7.1.1 LDB - Load signed byte

Load and sign extend a byte (8 bits).

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 0 0 0 0 1 A

0 0 0 0 0 1 Ra Rb VH IM C

if V = 10 thenadr ← int(b) + int(c) × i × scale

else

adr ← int(b) + int(c) × scalea ← int(MEM[adr ,1])

Fmt V T Assembler

A 00 00 LDB Sa, Sb, Sc

A 00 01 LDB Sa, Sb, Sc*2



A 10 00 LDB Va, Sb, Sc

A 10 01 LDB Va, Sb, Sc*2



A 11 00 LDB Va, Sb, Vc

A 11 01 LDB Va, Sb, Vc*2



C 00 00 LDB Sa, Sb, #ext14(H,IM)

C 10 00 LDB Va, Sb, #ext14(H,IM)

7.1.2 LDH - Load signed half-word

Load and sign extend a half-word (16 bits).

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 0 0 0 1 0 A

0 0 0 0 1 0 Ra Rb VH IM C


else


12

13

Fmt V T Assembler

A 00 00 LDH Sa, Sb, Sc

A 00 01 LDH Sa, Sb, Sc*2



A 10 00 LDH Va, Sb, Sc

A 10 01 LDH Va, Sb, Sc*2



A 11 00 LDH Va, Sb, Vc

A 11 01 LDH Va, Sb, Vc*2



C 00 00 LDH Sa, Sb, #ext14(H,IM)

C 10 00 LDH Va, Sb, #ext14(H,IM)

7.1.3 LDW - Load word

Load a word (32 bits).

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 0 0 0 1 1 A

0 0 0 0 1 1 Ra Rb VH IM C


else


Fmt V T Assembler

A 00 00 LDW Sa, Sb, Sc

A 00 01 LDW Sa, Sb, Sc*2



A 10 00 LDW Va, Sb, Sc

A 10 01 LDW Va, Sb, Sc*2



A 11 00 LDW Va, Sb, Vc

A 11 01 LDW Va, Sb, Vc*2



C 00 00 LDW Sa, Sb, #ext14(H,IM)

C 10 00 LDW Va, Sb, #ext14(H,IM)

7.1.4 LDWPC - Load word PC-relative

Load a word (32 bits) from the address that is formedby adding the 21-bit signed immediate, multiplied byfour, to the current PC.

026 2131

1 1 0 1 0 0 Ra IM D

adr ← PC + int(b) × 4a ← int(MEM[adr ,4])

Assembler

LDWPC Sa, #address@pc

7.1.5 LDUB - Load unsigned byte

Load and zero extend a byte (8 bits).

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 0 0 1 0 1 A

0 0 0 1 0 1 Ra Rb VH IM C


else

adr ← int(b) + int(c) × scalea ← uint(MEM[adr ,1])

Fmt V T Assembler

A 00 00 LDUB Sa , Sb , Sc

A 00 01 LDUB Sa , Sb , Sc*2



A 10 00 LDUB Va , Sb , Sc

A 10 01 LDUB Va , Sb , Sc*2



A 11 00 LDUB Va , Sb , Vc

A 11 01 LDUB Va , Sb , Vc*2



C 00 00 LDUB Sa , Sb , #ext14(H,IM)

C 10 00 LDUB Va , Sb , #ext14(H,IM)

7.1.6 LDUH - Load unsigned half-word

Load and zero extend a half-word (16 bits).

14

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 0 0 1 1 0 A

0 0 0 1 1 0 Ra Rb VH IM C


else

adr ← int(b) + int(c) × scalea ← uint(MEM[adr ,2])

Fmt V T Assembler

A 00 00 LDUH Sa , Sb , Sc

A 00 01 LDUH Sa , Sb , Sc*2



A 10 00 LDUH Va , Sb , Sc

A 10 01 LDUH Va , Sb , Sc*2



A 11 00 LDUH Va , Sb , Vc

A 11 01 LDUH Va , Sb , Vc*2



C 00 00 LDUH Sa , Sb , #ext14(H,IM)

C 10 00 LDUH Va , Sb , #ext14(H,IM)

7.1.7 LDEA - Load e�ective address

Load e�ective address.079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 0 0 1 1 1 A

0 0 0 1 1 1 Ra Rb VH IM C

if V = 10 thena ← int(b) + int(c) × i × scale

else

a ← int(b) + int(c) × scale

Fmt V T Assembler

A 00 00 LDEA Sa , Sb , Sc

A 00 01 LDEA Sa , Sb , Sc*2



A 10 00 LDEA Va , Sb , Sc

A 10 01 LDEA Va , Sb , Sc*2



A 11 00 LDEA Va , Sb , Vc

A 11 01 LDEA Va , Sb , Vc*2



C 00 00 LDEA Sa , Sb , #ext14(H,IM)

C 10 00 LDEA Va , Sb , #ext14(H,IM)

Note

When the target operand is a vector register, LDEAcan be used for constructing strides. For instanceLDEA V1,Z,#3 will assign the vector [0,3,6,9,. . . ]to register V1.

7.1.8 STB - Store byte

Store a byte (8 bits).

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 0 1 0 0 1 A

0 0 1 0 0 1 Ra Rb VH IM C


else

adr ← int(b) + int(c) × scaleMEM[adr ,1] ← a

Fmt V T Assembler

A 00 00 STB Sa, Sb, Sc

A 00 01 STB Sa, Sb, Sc*2



A 10 00 STB Va, Sb, Sc

A 10 01 STB Va, Sb, Sc*2



A 11 00 STB Va, Sb, Vc

A 11 01 STB Va, Sb, Vc*2



C 00 00 STB Sa, Sb, #ext14(H,IM)

C 10 00 STB Va, Sb, #ext14(H,IM)

15

7.1.9 STH - Store half-word

Store a half-word (16 bits).

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 0 1 0 1 0 A

0 0 1 0 1 0 Ra Rb VH IM C


else


Fmt V T Assembler

A 00 00 STH Sa, Sb, Sc

A 00 01 STH Sa, Sb, Sc*2



A 10 00 STH Va, Sb, Sc

A 10 01 STH Va, Sb, Sc*2



A 11 00 STH Va, Sb, Vc

A 11 01 STH Va, Sb, Vc*2



C 00 00 STH Sa, Sb, #ext14(H,IM)

C 10 00 STH Va, Sb, #ext14(H,IM)

7.1.10 STW - Store word

Store a word (32 bits).

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 0 1 0 1 1 A

0 0 1 0 1 1 Ra Rb VH IM C


else


Fmt V T Assembler

A 00 00 STW Sa, Sb, Sc

A 00 01 STW Sa, Sb, Sc*2



A 10 00 STW Va, Sb, Sc

A 10 01 STW Va, Sb, Sc*2



A 11 00 STW Va, Sb, Vc

A 11 01 STW Va, Sb, Vc*2



C 00 00 STW Sa, Sb, #ext14(H,IM)

C 10 00 STW Va, Sb, #ext14(H,IM)

7.1.11 STWPC - Store word PC-relative

Store a word (32 bits) to the address that is formed byadding the 21-bit signed immediate, multiplied by four,to the current PC.

026 2131

1 1 0 1 0 1 Ra IM D

adr ← PC + int(b) × 4MEM[adr ,4] ← a

Assembler

STWPC Sa, #address@pc

7.1.12 LDLI - Load low immediate

Load low immediate value.026 2131

1 1 0 0 1 0 Ra IM D

a ← int(IM)

Assembler

LDLI Sa , #ext21(IM)

Note

With this instruction it is possible to load signedinteger values in the range [-1048576, 1048575].

16

7.1.13 LDHI - Load high immediate

Load high immediate value.

026 2131

1 1 0 0 1 1 Ra IM D

a ← int(IM)

17

7.2 Bitwise logic

7.2.1 AND - Bitwise and

Compute the bitwise and of two integer operands, withoptional negation of the source operands.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 0 0 0 0 A

0 1 0 0 0 0 Ra Rb VH IM C

if T = 00 thena ← b & c

else if T = 01 thena ← b & ~c

else if T = 10 thena ← ~b & c

else if T = 11 thena ← ~b & ~c

Fmt V T Assembler

A 00 00 AND Sa, Sb, Sc

A 00 01 AND.PN Sa , Sb , Sc

A 00 10 AND.NP Sa , Sb , Sc

A 00 11 AND.NN Sa , Sb , Sc

A 10 00 AND Va, Vb, Sc

A 10 01 AND.PN Va , Vb , Sc

A 10 10 AND.NP Va , Vb , Sc

A 10 11 AND.NN Va , Vb , Sc

A 11 00 AND Va, Vb, Vc

A 11 01 AND.PN Va , Vb , Vc

A 11 10 AND.NP Va , Vb , Vc

A 11 11 AND.NN Va , Vb , Vc

A 01 00 AND/F Va, Vb , Vc

A 01 01 AND.PN/F Va , Vb , Vc

A 01 10 AND.NP/F Va , Vb , Vc

A 01 11 AND.NN/F Va , Vb , Vc

C 00 00 AND Sa, Sb, #ext14(H,IM)

C 10 00 AND Va, Vb, #ext14(H,IM)

7.2.2 OR - Bitwise or

Compute the bitwise or of two integer operands, withoptional negation of the source operands.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 0 0 0 1 A

0 1 0 0 0 1 Ra Rb VH IM C

if T = 00 then

a ← b | celse if T = 01 then

a ← b | ~celse if T = 10 then

a ← ~b | celse if T = 11 then

a ← ~b | ~c

Fmt V T Assembler

A 00 00 OR Sa, Sb, Sc

A 00 01 OR.PN Sa , Sb , Sc

A 00 10 OR.NP Sa , Sb , Sc

A 00 11 OR.NN Sa , Sb , Sc

A 10 00 OR Va, Vb, Sc

A 10 01 OR.PN Va , Vb , Sc

A 10 10 OR.NP Va , Vb , Sc

A 10 11 OR.NN Va , Vb , Sc

A 11 00 OR Va, Vb, Vc

A 11 01 OR.PN Va , Vb , Vc

A 11 10 OR.NP Va , Vb , Vc

A 11 11 OR.NN Va , Vb , Vc

A 01 00 OR/F Va, Vb , Vc

A 01 01 OR.PN/F Va, Vb, Vc

A 01 10 OR.NP/F Va, Vb, Vc

A 01 11 OR.NN/F Va, Vb, Vc

C 00 00 OR Sa, Sb, #ext14(H,IM)

C 10 00 OR Va, Vb, #ext14(H,IM)

7.2.3 XOR - Bitwise exclusive or

Compute the bitwise exclusive or of two integeroperands, with optional negation of the sourceoperands.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 0 0 1 0 A

0 1 0 0 1 0 Ra Rb VH IM C

if T = 00 thena ← b ^ c

else if T = 01 thena ← b ^ ~c

else if T = 10 thena ← ~b ^ c

else if T = 11 thena ← ~b ^ ~c

18

Fmt V T Assembler

A 00 00 XOR Sa, Sb, Sc

A 00 01 XOR.PN Sa , Sb , Sc

A 00 10 XOR.NP Sa , Sb , Sc

A 00 11 XOR.NN Sa , Sb , Sc

A 10 00 XOR Va, Vb, Sc

A 10 01 XOR.PN Va , Vb , Sc

A 10 10 XOR.NP Va , Vb , Sc

A 10 11 XOR.NN Va , Vb , Sc

A 11 00 XOR Va, Vb, Vc

A 11 01 XOR.PN Va , Vb , Vc

A 11 10 XOR.NP Va , Vb , Vc

A 11 11 XOR.NN Va , Vb , Vc

A 01 00 XOR/F Va, Vb , Vc

A 01 01 XOR.PN/F Va , Vb , Vc

A 01 10 XOR.NP/F Va , Vb , Vc

A 01 11 XOR.NN/F Va , Vb , Vc

C 00 00 XOR Sa, Sb, #ext14(H,IM)

C 10 00 XOR Va, Vb, #ext14(H,IM)

7.2.4 EBF - Extract bit �eld

Extract a bit �eld from the �rst source operand, sign-extend it, and store it in the destination operand. Thebit �eld is de�ned by the second source operand as fol-lows: the lowest log2(bits) bits describe the o�set (0 tobits-1), and the next log2(bits) describe the width (1 tobits).

If the bit �eld extends beyond the most signi�cant bit,then the most signi�cant bit of the �rst source operandis used as the sign bit and is extended in the destinationoperand.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 0 0 1 1 A

0 1 0 0 1 1 Ra Rb VH IM C

o ← uint(c & (bits -1))w ← uint((c >> log2(bits)) & (bits -1))if w = 0 then

w ← bits// Note: b is sign -extended up to o+w

// bits if o+w > bits.

a ← int(b)

Fmt V T Assembler

A 00 00 EBF Sa, Sb, Sc

A 00 01 EBF.B Sa , Sb , Sc

A 00 10 EBF.H Sa , Sb , Sc

A 10 00 EBF Va, Vb, Sc

A 10 01 EBF.B Va , Vb , Sc

A 10 10 EBF.H Va , Vb , Sc

A 11 00 EBF Va, Vb, Vc

A 11 01 EBF.B Va , Vb , Vc

A 11 10 EBF.H Va , Vb , Vc

A 01 00 EBF/F Va , Vb , Vc

A 01 01 EBF.B/F Va, Vb, Vc

A 01 10 EBF.H/F Va, Vb, Vc

C 00 00 EBF Sa, Sb, #ext14(H,IM)

C 10 00 EBF Va, Vb, #ext14(H,IM)

Note

When the bit �eld width descriptor is all zeros(specifying the full width of the chunk), this in-struction operates as an arithmetic shift right in-struction.

ASR is a valid assembler alias for EBF.

7.2.5 EBFU - Extract bit �eld unsigned

Extract a bit �eld from the �rst source operand, zero-extend it, and store it in the destination operand. Thebit �eld is de�ned by the second source operand as fol-lows: the lowest log2(bits) bits describe the o�set (0 tobits-1), and the next log2(bits) describe the width (1 tobits).

If the bit �eld extends beyond the most signi�cant bit,then the most signi�cant bit of the �rst source operandis used as the sign bit and is extended in the destinationoperand.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 0 1 0 0 A

0 1 0 1 0 0 Ra Rb VH IM C


w ← bits// Note: b is zero -extended up to o+w

// bits if o+w > bits.

a ← uint(b)

19

Fmt V T Assembler

A 00 00 EBFU Sa , Sb , Sc

A 00 01 EBFU.B Sa, Sb, Sc

A 00 10 EBFU.H Sa, Sb, Sc

A 10 00 EBFU Va , Vb , Sc

A 10 01 EBFU.B Va, Vb, Sc

A 10 10 EBFU.H Va, Vb, Sc

A 11 00 EBFU Va , Vb , Vc

A 11 01 EBFU.B Va, Vb, Vc

A 11 10 EBFU.H Va, Vb, Vc

A 01 00 EBFU/F Va, Vb, Vc

A 01 01 EBFU.B/F Va, Vb, Vc

A 01 10 EBFU.H/F Va, Vb, Vc

C 00 00 EBFU Sa , Sb , #ext14(H,IM)

C 10 00 EBFU Va , Vb , #ext14(H,IM)

Note

When the bit �eld width descriptor is all zeros(specifying the full width of the chunk), this in-struction operates as a logic shift right instruction.

LSR is a valid assembler alias for EBFU.

7.2.6 MKBF - Make bit �eld

Extract a bit �eld from the �rst source operand, zero-extend it, shift it to the left, and store it in the destina-tion operand.

The bit �eld is de�ned by the second source operand asfollows: the lowest log2(bits) bits describe the o�set (0to bits-1), and the next log2(bits) describe the width (1to bits).

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 0 1 0 1 A

0 1 0 1 0 1 Ra Rb VH IM C


w ← bitsa ← (b & ones(w))

20

Fmt V T Assembler

A 00 00 SEL Sa, Sb, Sc

A 00 01 SEL .132 Sa, Sb, Sc

A 00 10 SEL .213 Sa, Sb, Sc

A 00 11 SEL .231 Sa, Sb, Sc

A 10 00 SEL Va, Vb, Sc

A 10 01 SEL .132 Va, Vb, Sc

A 10 10 SEL .213 Va, Vb, Sc

A 10 11 SEL .231 Va, Vb, Sc

A 11 00 SEL Va, Vb, Vc

A 11 01 SEL .132 Va, Vb, Vc

A 11 10 SEL .213 Va, Vb, Vc

A 11 11 SEL .231 Va, Vb, Vc

A 01 00 SEL/F Va, Vb , Vc

A 01 01 SEL .132/F Va, Vb , Vc

A 01 10 SEL .213/F Va, Vb , Vc

A 01 11 SEL .231/F Va, Vb , Vc

C 00 00 SEL Sa, Sb, #ext14(H,IM)

C 10 00 SEL Va, Vb, #ext14(H,IM)

21

7.3 Integer arithmetic

7.3.1 ADD - Add

Compute the sum of two integer operands.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 0 1 1 0 A

0 1 0 1 1 0 Ra Rb VH IM C

a ← int(b) + int(c)

Fmt V T Assembler

A 00 00 ADD Sa, Sb, Sc

A 00 01 ADD.B Sa, Sb , Sc

A 00 10 ADD.H Sa, Sb , Sc

A 10 00 ADD Va, Vb, Sc

A 10 01 ADD.B Va, Vb , Sc

A 10 10 ADD.H Va, Vb , Sc

A 11 00 ADD Va, Vb, Vc

A 11 01 ADD.B Va, Vb , Vc

A 11 10 ADD.H Va, Vb , Vc

A 01 00 ADD/F Va, Vb , Vc

A 01 01 ADD.B/F Va, Vb, Vc

A 01 10 ADD.H/F Va, Vb, Vc

C 00 00 ADD Sa, Sb, #ext14(H,IM)

C 10 00 ADD Va, Vb, #ext14(H,IM)

7.3.2 SUB - Subtract

Compute the di�erence of two integer operands.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 0 1 1 1 A

0 1 0 1 1 1 Ra Rb VH IM C

a ← int(c) - int(b)

Fmt V T Assembler

A 00 00 SUB Sa, Sc, Sb

A 00 01 SUB.B Sa , Sc , Sb

A 00 10 SUB.H Sa , Sc , Sb

A 10 00 SUB Va, Sc, Vb

A 10 01 SUB.B Va , Sc , Vb

A 10 10 SUB.H Va , Sc , Vb

A 11 00 SUB Va, Vc, Vb

A 11 01 SUB.B Va , Vc , Vb

A 11 10 SUB.H Va , Vc , Vb

A 01 00 SUB/F Va , Vc , Vb

A 01 01 SUB.B/F Va, Vc, Vb

A 01 10 SUB.H/F Va, Vc, Vb

C 00 00 SUB Sa, #ext14(H,IM), Sb

C 10 00 SUB Va, #ext14(H,IM), Vb

Note

The instruction actually subtracts the �rst sourceoperand from the second source operand. How-ever, in the assembler syntax the order of thesource operands is reversed compared to how theoperands are encoded in the instruction word, inorder to make the assembler syntax more natural.

The advantage is that it is possible to subtracta register operand from an immediate operand(subtracting an immediate operand from a regis-ter operand can be implemented with the ADDinstruction, using a negated immediate operand).

7.3.3 MUL - Multiply

Compute the product of two integer operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 0 1 1 0 1 0 0 A

a ← int(b) × int(c)

22

V T Assembler

00 00 MUL Sa, Sb, Sc

00 01 MUL.B Sa , Sb , Sc

00 10 MUL.H Sa , Sb , Sc

10 00 MUL Va, Vb, Sc

10 01 MUL.B Va , Vb , Sc

10 10 MUL.H Va , Vb , Sc

11 00 MUL Va, Vb, Vc

11 01 MUL.B Va , Vb , Vc

11 10 MUL.H Va , Vb , Vc

01 00 MUL/F Va , Vb , Vc

01 01 MUL.B/F Va, Vb, Vc

01 10 MUL.H/F Va, Vb, Vc

7.3.4 MULHI - Signed multiply high

Compute the upper part of the product of two signedinteger operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 0 1 1 0 1 0 1 A

a ← (int(b) × int(c)) >> bits

V T Assembler

00 00 MULHI Sa, Sb, Sc

00 01 MULHI.B Sa , Sb , Sc

00 10 MULHI.H Sa , Sb , Sc

10 00 MULHI Va, Vb, Sc

10 01 MULHI.B Va , Vb , Sc

10 10 MULHI.H Va , Vb , Sc

11 00 MULHI Va, Vb, Vc

11 01 MULHI.B Va , Vb , Vc

11 10 MULHI.H Va , Vb , Vc

01 00 MULHI/F Va , Vb , Vc

01 01 MULHI.B/F Va, Vb, Vc

01 10 MULHI.H/F Va, Vb, Vc

7.3.5 MULHIU - Unsigned multiply high

Compute the upper part of the product of two unsignedinteger operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 0 1 1 0 1 1 0 A

a ← (uint(b) × uint(c)) >> bits

V T Assembler

00 00 MULHIU Sa, Sb, Sc

00 01 MULHIU.B Sa, Sb, Sc

00 10 MULHIU.H Sa, Sb, Sc

10 00 MULHIU Va, Vb, Sc

10 01 MULHIU.B Va, Vb, Sc

10 10 MULHIU.H Va, Vb, Sc

11 00 MULHIU Va, Vb, Vc

11 01 MULHIU.B Va, Vb, Vc

11 10 MULHIU.H Va, Vb, Vc

01 00 MULHIU/F Va, Vb, Vc

01 01 MULHIU.B/F Va , Vb, Vc

01 10 MULHIU.H/F Va , Vb, Vc

7.3.6 DIV - Signed divide

Compute the quotient of two signed integer operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 0 1 1 0 0 0 0 A

a ← int(b) / int(c)

V T Assembler

00 00 DIV Sa, Sb, Sc

00 01 DIV.B Sa , Sb , Sc

00 10 DIV.H Sa , Sb , Sc

10 00 DIV Va, Vb, Sc

10 01 DIV.B Va , Vb , Sc

10 10 DIV.H Va , Vb , Sc

11 00 DIV Va, Vb, Vc

11 01 DIV.B Va , Vb , Vc

11 10 DIV.H Va , Vb , Vc

01 00 DIV/F Va , Vb , Vc

01 01 DIV.B/F Va, Vb, Vc

01 10 DIV.H/F Va, Vb, Vc

7.3.7 DIVU - Unsigned divide

Compute the quotient of two unsigned integer operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 0 1 1 0 0 0 1 A

a ← uint(b) / uint(c)

23

V T Assembler

00 00 DIVU Sa , Sb , Sc

00 01 DIVU.B Sa, Sb, Sc

00 10 DIVU.H Sa, Sb, Sc

10 00 DIVU Va , Vb , Sc

10 01 DIVU.B Va, Vb, Sc

10 10 DIVU.H Va, Vb, Sc

11 00 DIVU Va , Vb , Vc

11 01 DIVU.B Va, Vb, Vc

11 10 DIVU.H Va, Vb, Vc

01 00 DIVU/F Va, Vb, Vc

01 01 DIVU.B/F Va, Vb, Vc

01 10 DIVU.H/F Va, Vb, Vc

7.3.8 REM - Signed remainder

Compute the modulo of two signed integer operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 0 1 1 0 0 1 0 A

a ← int(b) % int(c)

V T Assembler

00 00 REM Sa, Sb, Sc

00 01 REM.B Sa , Sb , Sc

00 10 REM.H Sa , Sb , Sc

10 00 REM Va, Vb, Sc

10 01 REM.B Va , Vb , Sc

10 10 REM.H Va , Vb , Sc

11 00 REM Va, Vb, Vc

11 01 REM.B Va , Vb , Vc

11 10 REM.H Va , Vb , Vc

01 00 REM/F Va , Vb , Vc

01 01 REM.B/F Va, Vb, Vc

01 10 REM.H/F Va, Vb, Vc

7.3.9 REMU - Unsigned remainder

Compute the modulo of two unsigned integer operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 0 1 1 0 0 1 1 A

a ← uint(b) % uint(c)

V T Assembler

00 00 REMU Sa , Sb , Sc

00 01 REMU.B Sa, Sb, Sc

00 10 REMU.H Sa, Sb, Sc

10 00 REMU Va , Vb , Sc

10 01 REMU.B Va, Vb, Sc

10 10 REMU.H Va, Vb, Sc

11 00 REMU Va , Vb , Vc

11 01 REMU.B Va, Vb, Vc

11 10 REMU.H Va, Vb, Vc

01 00 REMU/F Va, Vb, Vc

01 01 REMU.B/F Va, Vb, Vc

01 10 REMU.H/F Va, Vb, Vc

7.3.10 MIN - Signed minimum

Return the minimum value of two signed integeroperands.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 1 0 0 0 A

0 1 1 0 0 0 Ra Rb VH IM C

a ← min(int(b), int(c))

Fmt V T Assembler

A 00 00 MIN Sa, Sb, Sc

A 00 01 MIN.B Sa , Sb , Sc

A 00 10 MIN.H Sa , Sb , Sc

A 10 00 MIN Va, Vb, Sc

A 10 01 MIN.B Va , Vb , Sc

A 10 10 MIN.H Va , Vb , Sc

A 11 00 MIN Va, Vb, Vc

A 11 01 MIN.B Va , Vb , Vc

A 11 10 MIN.H Va , Vb , Vc

A 01 00 MIN/F Va , Vb , Vc

A 01 01 MIN.B/F Va, Vb, Vc

A 01 10 MIN.H/F Va, Vb, Vc

C 00 00 MIN Sa, Sb, #ext14(H,IM)

C 10 00 MIN Va, Vb, #ext14(H,IM)

7.3.11 MAX - Signed maxiumum

Return the maximum value of two signed integeroperands.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 1 0 0 1 A

0 1 1 0 0 1 Ra Rb VH IM C

24

a ← max(int(b), int(c))

Fmt V T Assembler

A 00 00 MAX Sa, Sb, Sc

A 00 01 MAX.B Sa, Sb , Sc

A 00 10 MAX.H Sa, Sb , Sc

A 10 00 MAX Va, Vb, Sc

A 10 01 MAX.B Va, Vb , Sc

A 10 10 MAX.H Va, Vb , Sc

A 11 00 MAX Va, Vb, Vc

A 11 01 MAX.B Va, Vb , Vc

A 11 10 MAX.H Va, Vb , Vc

A 01 00 MAX/F Va, Vb , Vc

A 01 01 MAX.B/F Va, Vb, Vc

A 01 10 MAX.H/F Va, Vb, Vc

C 00 00 MAX Sa, Sb, #ext14(H,IM)

C 10 00 MAX Va, Vb, #ext14(H,IM)

7.3.12 MINU - Unsigned minimum

Return the minimum value of two unsigned integeroperands.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 1 0 1 0 A

0 1 1 0 1 0 Ra Rb VH IM C

a ← min(uint(b), uint(c))

Fmt V T Assembler

A 00 00 MINU Sa , Sb , Sc

A 00 01 MINU.B Sa, Sb, Sc

A 00 10 MINU.H Sa, Sb, Sc

A 10 00 MINU Va , Vb , Sc

A 10 01 MINU.B Va, Vb, Sc

A 10 10 MINU.H Va, Vb, Sc

A 11 00 MINU Va , Vb , Vc

A 11 01 MINU.B Va, Vb, Vc

A 11 10 MINU.H Va, Vb, Vc

A 01 00 MINU/F Va, Vb, Vc

A 01 01 MINU.B/F Va, Vb, Vc

A 01 10 MINU.H/F Va, Vb, Vc

C 00 00 MINU Sa , Sb , #ext14(H,IM)

C 10 00 MINU Va , Vb , #ext14(H,IM)

7.3.13 MAXU - Unsigned maximum

Return the maximum value of two unsigned integeroperands.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 1 0 1 1 A

0 1 1 0 1 1 Ra Rb VH IM C

a ← max(uint(b), uint(c))

Fmt V T Assembler

A 00 00 MAXU Sa , Sb , Sc

A 00 01 MAXU.B Sa, Sb, Sc

A 00 10 MAXU.H Sa, Sb, Sc

A 10 00 MAXU Va , Vb , Sc

A 10 01 MAXU.B Va, Vb, Sc

A 10 10 MAXU.H Va, Vb, Sc

A 11 00 MAXU Va , Vb , Vc

A 11 01 MAXU.B Va, Vb, Vc

A 11 10 MAXU.H Va, Vb, Vc

A 01 00 MAXU/F Va, Vb, Vc

A 01 01 MAXU.B/F Va, Vb, Vc

A 01 10 MAXU.H/F Va, Vb, Vc

C 00 00 MAXU Sa , Sb , #ext14(H,IM)

C 10 00 MAXU Va , Vb , #ext14(H,IM)

7.3.14 ADDPCHI - Add PC high imme-diate

Compute the sum of the current PC and and immediateoperand that is shifted to the left 11 steps before theaddition.

026 2131

1 1 0 1 1 0 Ra IM D

a ← int(PC) + (int(IM)

25

7.4 Integer comparison

7.4.1 SEQ - Set if equal

Compare two integer operands, and set all bits of theresult to 1 if the operands are equal, otherwise set allbits of the result to 0.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 1 1 1 0 A

0 1 1 1 1 0 Ra Rb VH IM C

if b = c thena ← ones(bits)

else

a ← zeros(bits)

Fmt V T Assembler

A 00 00 SEQ Sa, Sb, Sc

A 00 01 SEQ.B Sa, Sb , Sc

A 00 10 SEQ.H Sa, Sb , Sc

A 10 00 SEQ Va, Vb, Sc

A 10 01 SEQ.B Va, Vb , Sc

A 10 10 SEQ.H Va, Vb , Sc

A 11 00 SEQ Va, Vb, Vc

A 11 01 SEQ.B Va, Vb , Vc

A 11 10 SEQ.H Va, Vb , Vc

A 01 00 SEQ/F Va, Vb , Vc

A 01 01 SEQ.B/F Va, Vb, Vc

A 01 10 SEQ.H/F Va, Vb, Vc

C 00 00 SEQ Sa, Sb, #ext14(H,IM)

C 10 00 SEQ Va, Vb, #ext14(H,IM)

7.4.2 SNE - Set if not equal

Compare two integer operands, and set all bits of theresult to 1 if the operands are not equal, otherwise setall bits of the result to 0.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 0 1 1 1 1 1 A

0 1 1 1 1 1 Ra Rb VH IM C

if b ̸= c thena ← ones(bits)

else

a ← zeros(bits)

Fmt V T Assembler

A 00 00 SNE Sa, Sb, Sc

A 00 01 SNE.B Sa , Sb , Sc

A 00 10 SNE.H Sa , Sb , Sc

A 10 00 SNE Va, Vb, Sc

A 10 01 SNE.B Va , Vb , Sc

A 10 10 SNE.H Va , Vb , Sc

A 11 00 SNE Va, Vb, Vc

A 11 01 SNE.B Va , Vb , Vc

A 11 10 SNE.H Va , Vb , Vc

A 01 00 SNE/F Va , Vb , Vc

A 01 01 SNE.B/F Va, Vb, Vc

A 01 10 SNE.H/F Va, Vb, Vc

C 00 00 SNE Sa, Sb, #ext14(H,IM)

C 10 00 SNE Va, Vb, #ext14(H,IM)

7.4.3 SLT - Set if less than

Compare two signed integer operands, and set all bitsof the result to 1 if the �rst operand is less than thesecond operand, otherwise set all bits of the result to 0.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 1 0 0 0 0 0 A

1 0 0 0 0 0 Ra Rb VH IM C

if int(b) < int(c) then

a ← ones(bits)else

a ← zeros(bits)

Fmt V T Assembler

A 00 00 SLT Sa, Sb, Sc

A 00 01 SLT.B Sa , Sb , Sc

A 00 10 SLT.H Sa , Sb , Sc

A 10 00 SLT Va, Vb, Sc

A 10 01 SLT.B Va , Vb , Sc

A 10 10 SLT.H Va , Vb , Sc

A 11 00 SLT Va, Vb, Vc

A 11 01 SLT.B Va , Vb , Vc

A 11 10 SLT.H Va , Vb , Vc

A 01 00 SLT/F Va , Vb , Vc

A 01 01 SLT.B/F Va, Vb, Vc

A 01 10 SLT.H/F Va, Vb, Vc

C 00 00 SLT Sa, Sb, #ext14(H,IM)

C 10 00 SLT Va, Vb, #ext14(H,IM)

26

7.4.4 SLTU - Set if less than unsigned

Compare two unsigned integer operands, and set all bitsof the result to 1 if the �rst operand is less than thesecond operand, otherwise set all bits of the result to 0.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 1 0 0 0 0 1 A

1 0 0 0 0 1 Ra Rb VH IM C

if uint(b) < uint(c) then


a ← zeros(bits)

Fmt V T Assembler

A 00 00 SLTU Sa , Sb , Sc

A 00 01 SLTU.B Sa, Sb, Sc

A 00 10 SLTU.H Sa, Sb, Sc

A 10 00 SLTU Va , Vb , Sc

A 10 01 SLTU.B Va, Vb, Sc

A 10 10 SLTU.H Va, Vb, Sc

A 11 00 SLTU Va , Vb , Vc

A 11 01 SLTU.B Va, Vb, Vc

A 11 10 SLTU.H Va, Vb, Vc

A 01 00 SLTU/F Va, Vb, Vc

A 01 01 SLTU.B/F Va, Vb, Vc

A 01 10 SLTU.H/F Va, Vb, Vc

C 00 00 SLTU Sa , Sb , #ext14(H,IM)

C 10 00 SLTU Va , Vb , #ext14(H,IM)

7.4.5 SLE - Set if less than or equal

Compare two signed integer operands, and set all bits ofthe result to 1 if the �rst operand is less than or equal tothe second operand, otherwise set all bits of the resultto 0.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 1 0 0 0 1 0 A

1 0 0 0 1 0 Ra Rb VH IM C

if int(b) ≤ int(c) thena ← ones(bits)

else

a ← zeros(bits)

Fmt V T Assembler

A 00 00 SLE Sa, Sb, Sc

A 00 01 SLE.B Sa , Sb , Sc

A 00 10 SLE.H Sa , Sb , Sc

A 10 00 SLE Va, Vb, Sc

A 10 01 SLE.B Va , Vb , Sc

A 10 10 SLE.H Va , Vb , Sc

A 11 00 SLE Va, Vb, Vc

A 11 01 SLE.B Va , Vb , Vc

A 11 10 SLE.H Va , Vb , Vc

A 01 00 SLE/F Va , Vb , Vc

A 01 01 SLE.B/F Va, Vb, Vc

A 01 10 SLE.H/F Va, Vb, Vc

C 00 00 SLE Sa, Sb, #ext14(H,IM)

C 10 00 SLE Va, Vb, #ext14(H,IM)

7.4.6 SLEU - Set if less than or equalunsigned

Compare two unsigned integer operands, and set all bitsof the result to 1 if the �rst operand is less than or equalto the second operand, otherwise set all bits of the resultto 0.

079141516212631

0 0 0 0 0 0 Ra Rb V Rc T 0 1 0 0 0 1 1 A

1 0 0 0 1 1 Ra Rb VH IM C

if uint(b) ≤ uint(c) thena ← ones(bits)

else

a ← zeros(bits)

Fmt V T Assembler

A 00 00 SLEU Sa , Sb , Sc

A 00 01 SLEU.B Sa, Sb, Sc

A 00 10 SLEU.H Sa, Sb, Sc

A 10 00 SLEU Va , Vb , Sc

A 10 01 SLEU.B Va, Vb, Sc

A 10 10 SLEU.H Va, Vb, Sc

A 11 00 SLEU Va , Vb , Vc

A 11 01 SLEU.B Va, Vb, Vc

A 11 10 SLEU.H Va, Vb, Vc

A 01 00 SLEU/F Va, Vb, Vc

A 01 01 SLEU.B/F Va, Vb, Vc

A 01 10 SLEU.H/F Va, Vb, Vc

C 00 00 SLEU Sa , Sb , #ext14(H,IM)

C 10 00 SLEU Va , Vb , #ext14(H,IM)

27

7.5 Branch

7.5.1 BZ - Branch if zero

Branch to the PC-relative target if all bits of the �rstsource operand are zero.

018212631

1 1 0 1 1 1 Ra 0 0 0 IM E

if a = zeros (32) thenPC ← PC + int(IM)×4

Assembler

BZ Sa, #target

7.5.2 BNZ - Branch if not zero

Branch to the PC-relative target if at least one of thebits of the �rst source operand is non-zero.

018212631

1 1 0 1 1 1 Ra 0 0 1 IM E

if a ̸= zeros (32) thenPC ← PC + int(IM)×4

Assembler

BNZ Sa, #target

7.5.3 BS - Branch if set

Branch to the PC-relative target if all bits of the �rstsource operand are non-zero.

018212631

1 1 0 1 1 1 Ra 0 1 0 IM E

if a = ones (32) thenPC ← PC + int(IM)×4

Assembler

BS Sa, #target

7.5.4 BNS - Branch if not set

Branch to the PC-relative target if at least one of thebits of the �rst source operand is zero.

018212631

1 1 0 1 1 1 Ra 0 1 1 IM E

if a ̸= ones (32) thenPC ← PC + int(IM)×4

Assembler

BNS Sa, #target

7.5.5 BLT - Branch if less than

Branch to the PC-relative target if the �rst sourceoperand is a signed integer value that is less than zero.

018212631

1 1 0 1 1 1 Ra 1 0 0 IM E

if int(a) < 0 then

PC ← PC + int(IM)×4

Assembler

BLT Sa, #target

7.5.6 BGE - Branch if greater than orequal

Branch to the PC-relative target if the �rst sourceoperand is a signed integer value that is greater thanor equal to zero.

018212631

1 1 0 1 1 1 Ra 1 0 1 IM E

if int(a) ≥ 0 thenPC ← PC + int(IM)×4

Assembler

BGE Sa, #target

7.5.7 BLE - Branch if less than or equal

Branch to the PC-relative target if the �rst sourceoperand is a signed integer value that is less than orequal to zero.

018212631

1 1 0 1 1 1 Ra 1 1 0 IM E

28

if int(a) ≤ 0 thenPC ← PC + int(IM)×4

Assembler

BLE Sa, #target

7.5.8 BGT - Branch if greater than

Branch to the PC-relative target if the �rst sourceoperand is a signed integer value that is greater thanzero.

018212631

1 1 0 1 1 1 Ra 1 1 1 IM E

if int(a) > 0 then

PC ← PC + int(IM)×4

Assembler

BGT Sa, #target

7.5.9 J - Jump

Jump to the target address that is formed by computingthe sum of the register operand and the sign-extendedimmediate value multiplied by four.

As a special case, the register operand can be the pro-gram counter (PC), which is encoded as register num-ber 31. This also means that the VL register can notbe used as the register operand.

026 2131

1 1 0 0 0 0 Ra IM D

PC ← int(a) + int(IM)×4

Assembler

J Sa, #target

Note

If the register operand is PC, a PC-relative branchwith an e�ective range of ±4MiB is performed. Toextend the range to the full address space, use Jin combination with a preceding ADDPCHI.

If the register operand is Z, an absolute branchis performed. Possible target addresses are0x00000000 to 0x003FFFFC and 0xFFC00000 to

0xFFFFFFFC. To extend the range to the full ad-dress space, use J in combination with a precedingLDHI.

If the register operand is LR and the immediatevalue is zero, the operation will return the program�ow to the caller (RET is an alias for J LR, #0).

7.5.10 JL - Jump and link

Jump and link. The current value of PC plus four isstored in the LR register, and the new PC is set to thetarget address that is formed by computing the sum ofthe register operand and the sign-extended immediatevalue multiplied by four.

As a special case, the register operand can be the pro-gram counter (PC), which is encoded as register num-ber 31. This also means that the VL register can notbe used as the register operand.

026 2131

1 1 0 0 0 1 Ra IM D

adr ← int(a) + int(IM)×4LR ← int(PC) + 4PC ← adr

Assembler

JL Sa, #target

Note

If the register operand is PC, a PC-relative branchwith an e�ective range of ±4MiB is performed. Toextend the range to the full address space, use JLin combination with a preceding ADDPCHI.

If the register operand is Z, an absolute branchis performed. Possible target addresses are0x00000000 to 0x003FFFFC and 0xFFC00000 to0xFFFFFFFC. To extend the range to the full ad-dress space, use JL in combination with a precedingLDHI.

29

7.6 Floating-point arithmetic

7.6.1 FADD - Floating-point add

Requires: FM

Compute the sum of two �oating-point operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 1 0 0 0 0 A

a ← float(b) + float(c)

V T Assembler

00 00 FADD Sa , Sb , Sc

00 01 FADD.B Sa, Sb, Sc

00 10 FADD.H Sa, Sb, Sc

10 00 FADD Va , Vb , Sc

10 01 FADD.B Va, Vb, Sc

10 10 FADD.H Va, Vb, Sc

11 00 FADD Va , Vb , Vc

11 01 FADD.B Va, Vb, Vc

11 10 FADD.H Va, Vb, Vc

01 00 FADD/F Va, Vb, Vc

01 01 FADD.B/F Va, Vb, Vc

01 10 FADD.H/F Va, Vb, Vc

7.6.2 FSUB - Floating-point subtract

Requires: FM

Compute the di�erence of two �oating-point operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 1 0 0 0 1 A

a ← float(b) - float(c)

V T Assembler

00 00 FSUB Sa , Sb , Sc

00 01 FSUB.B Sa, Sb, Sc

00 10 FSUB.H Sa, Sb, Sc

10 00 FSUB Va , Vb , Sc

10 01 FSUB.B Va, Vb, Sc

10 10 FSUB.H Va, Vb, Sc

11 00 FSUB Va , Vb , Vc

11 01 FSUB.B Va, Vb, Vc

11 10 FSUB.H Va, Vb, Vc

01 00 FSUB/F Va, Vb, Vc

01 01 FSUB.B/F Va, Vb, Vc

01 10 FSUB.H/F Va, Vb, Vc

7.6.3 FMUL - Floating-point multiply

Requires: FM

Compute the product of two �oating-point operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 1 0 0 1 0 A

a ← float(b) × float(c)

V T Assembler

00 00 FMUL Sa , Sb , Sc

00 01 FMUL.B Sa, Sb, Sc

00 10 FMUL.H Sa, Sb, Sc

10 00 FMUL Va , Vb , Sc

10 01 FMUL.B Va, Vb, Sc

10 10 FMUL.H Va, Vb, Sc

11 00 FMUL Va , Vb , Vc

11 01 FMUL.B Va, Vb, Vc

11 10 FMUL.H Va, Vb, Vc

01 00 FMUL/F Va, Vb, Vc

01 01 FMUL.B/F Va, Vb, Vc

01 10 FMUL.H/F Va, Vb, Vc

7.6.4 FDIV - Floating-point divide

Requires: FM

Compute the quotient of two �oating-point operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 1 0 0 1 1 A

a ← float(b) / float(c)

V T Assembler

00 00 FDIV Sa , Sb , Sc

00 01 FDIV.B Sa, Sb, Sc

00 10 FDIV.H Sa, Sb, Sc

10 00 FDIV Va , Vb , Sc

10 01 FDIV.B Va, Vb, Sc

10 10 FDIV.H Va, Vb, Sc

11 00 FDIV Va , Vb , Vc

11 01 FDIV.B Va, Vb, Vc

11 10 FDIV.H Va, Vb, Vc

01 00 FDIV/F Va, Vb, Vc

01 01 FDIV.B/F Va, Vb, Vc

01 10 FDIV.H/F Va, Vb, Vc

30

7.6.5 FMIN - Floating-point minimum

Requires: FM

Return the minimum value of two �oating-pointoperands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 0 0 0 0 A

a ← min(float(b), float(c))

V T Assembler

00 00 FMIN Sa , Sb , Sc

00 01 FMIN.B Sa, Sb, Sc

00 10 FMIN.H Sa, Sb, Sc

10 00 FMIN Va , Vb , Sc

10 01 FMIN.B Va, Vb, Sc

10 10 FMIN.H Va, Vb, Sc

11 00 FMIN Va , Vb , Vc

11 01 FMIN.B Va, Vb, Vc

11 10 FMIN.H Va, Vb, Vc

01 00 FMIN/F Va, Vb, Vc

01 01 FMIN.B/F Va, Vb, Vc

01 10 FMIN.H/F Va, Vb, Vc

7.6.6 FMAX - Floating-point maximum

Requires: FM

Return the maximum value of two �oating-pointoperands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 0 0 0 1 A

a ← max(float(b), float(c))

V T Assembler

00 00 FMAX Sa , Sb , Sc

00 01 FMAX.B Sa, Sb, Sc

00 10 FMAX.H Sa, Sb, Sc

10 00 FMAX Va , Vb , Sc

10 01 FMAX.B Va, Vb, Sc

10 10 FMAX.H Va, Vb, Sc

11 00 FMAX Va , Vb , Vc

11 01 FMAX.B Va, Vb, Vc

11 10 FMAX.H Va, Vb, Vc

01 00 FMAX/F Va, Vb, Vc

01 01 FMAX.B/F Va, Vb, Vc

01 10 FMAX.H/F Va, Vb, Vc

31

7.7 Floating-point comparison

7.7.1 FSEQ - Floating-point set if equal

Requires: FM

Compare two �oating-point operands, and set all bits ofthe result to 1 if the �rst operand is equal to the secondoperand, otherwise set all bits of the result to 0.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 0 0 1 0 A

if float(b) = float(c) thena ← ones(bits)

else

a ← zeros(bits)

V T Assembler

00 00 FSEQ Sa , Sb , Sc

00 01 FSEQ.B Sa, Sb, Sc

00 10 FSEQ.H Sa, Sb, Sc

10 00 FSEQ Va , Vb , Sc

10 01 FSEQ.B Va, Vb, Sc

10 10 FSEQ.H Va, Vb, Sc

11 00 FSEQ Va , Vb , Vc

11 01 FSEQ.B Va, Vb, Vc

11 10 FSEQ.H Va, Vb, Vc

01 00 FSEQ/F Va, Vb, Vc

01 01 FSEQ.B/F Va, Vb, Vc

01 10 FSEQ.H/F Va, Vb, Vc

7.7.2 FSNE - Floating-point set if notequal

Requires: FM

Compare two �oating-point operands, and set all bits ofthe result to 1 if the �rst operand is not equal to thesecond operand, otherwise set all bits of the result to 0.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 0 0 1 1 A

if float(b) ̸= float(c) thena ← ones(bits)

else

a ← zeros(bits)

V T Assembler

00 00 FSNE Sa , Sb , Sc

00 01 FSNE.B Sa, Sb, Sc

00 10 FSNE.H Sa, Sb, Sc

10 00 FSNE Va , Vb , Sc

10 01 FSNE.B Va, Vb, Sc

10 10 FSNE.H Va, Vb, Sc

11 00 FSNE Va , Vb , Vc

11 01 FSNE.B Va, Vb, Vc

11 10 FSNE.H Va, Vb, Vc

01 00 FSNE/F Va, Vb, Vc

01 01 FSNE.B/F Va, Vb, Vc

01 10 FSNE.H/F Va, Vb, Vc

7.7.3 FSLT - Floating-point set if lessthan

Requires: FM

Compare two �oating-point operands, and set all bitsof the result to 1 if the �rst operand is less than thesecond operand, otherwise set all bits of the result to 0.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 0 1 0 0 A

if float(b) < float(c) then


a ← zeros(bits)

V T Assembler

00 00 FSLT Sa , Sb , Sc

00 01 FSLT.B Sa, Sb, Sc

00 10 FSLT.H Sa, Sb, Sc

10 00 FSLT Va , Vb , Sc

10 01 FSLT.B Va, Vb, Sc

10 10 FSLT.H Va, Vb, Sc

11 00 FSLT Va , Vb , Vc

11 01 FSLT.B Va, Vb, Vc

11 10 FSLT.H Va, Vb, Vc

01 00 FSLT/F Va, Vb, Vc

01 01 FSLT.B/F Va, Vb, Vc

01 10 FSLT.H/F Va, Vb, Vc

7.7.4 FSLE - Floating-point set if lessthan or equal

Requires: FM

32

Compare two �oating-point operands, and set all bits ofthe result to 1 if the �rst operand is less than or equal tothe second operand, otherwise set all bits of the resultto 0.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 0 1 0 1 A

if float(b) ≤ float(c) thena ← ones(bits)

else

a ← zeros(bits)

V T Assembler

00 00 FSLE Sa , Sb , Sc

00 01 FSLE.B Sa, Sb, Sc

00 10 FSLE.H Sa, Sb, Sc

10 00 FSLE Va , Vb , Sc

10 01 FSLE.B Va, Vb, Sc

10 10 FSLE.H Va, Vb, Sc

11 00 FSLE Va , Vb , Vc

11 01 FSLE.B Va, Vb, Vc

11 10 FSLE.H Va, Vb, Vc

01 00 FSLE/F Va, Vb, Vc

01 01 FSLE.B/F Va, Vb, Vc

01 10 FSLE.H/F Va, Vb, Vc

7.7.5 FSUNORD - Floating-point set ifunordered

Requires: FM

Set all bits of the result to 1 if any of the source operandsare undordered (i.e. NaN), otherwise set all bits of theresult to 0.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 0 1 1 0 A

if isnan(b) ∧ isnan(c) thena ← ones(bits)

else

a ← zeros(bits)

V T Assembler

00 00 FSUNORD Sa, Sb, Sc

00 01 FSUNORD.B Sa , Sb, Sc

00 10 FSUNORD.H Sa , Sb, Sc

10 00 FSUNORD Va, Vb, Sc

10 01 FSUNORD.B Va , Vb, Sc

10 10 FSUNORD.H Va , Vb, Sc

11 00 FSUNORD Va, Vb, Vc

11 01 FSUNORD.B Va , Vb, Vc

11 10 FSUNORD.H Va , Vb, Vc

01 00 FSUNORD/F Va , Vb, Vc

01 01 FSUNORD.B/F Va, Vb, Vc

01 10 FSUNORD.H/F Va, Vb, Vc

7.7.6 FSORD - Floating-point set if or-dered

Requires: FM

Set all bits of the result to 1 if both of the sourceoperands are ordered (i.e. non-NaN), otherwise set allbits of the result to 0.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 0 1 1 1 A

if ¬isnan(b) ∨ ¬isnan(c) thena ← ones(bits)

else

a ← zeros(bits)

V T Assembler

00 00 FSORD Sa, Sb , Sc

00 01 FSORD.B Sa , Sb, Sc

00 10 FSORD.H Sa , Sb, Sc

10 00 FSORD Va, Vb , Sc

10 01 FSORD.B Va , Vb, Sc

10 10 FSORD.H Va , Vb, Sc

11 00 FSORD Va, Vb , Vc

11 01 FSORD.B Va , Vb, Vc

11 10 FSORD.H Va , Vb, Vc

01 00 FSORD/F Va , Vb, Vc

01 01 FSORD.B/F Va, Vb, Vc

01 10 FSORD.H/F Va, Vb, Vc

33

7.8 Floating-point conversion

7.8.1 ITOF - Signed integer to �oating-point

Requires: FM

Convert a signed integer value to a �oating-point value.The exponent of the resulting �oating-point value issubtracted by the integer o�set provided by the secondsource operand before storing the �nal �oating-pointvalue in the destination operand.

TODO

De�ne pseudocode.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 1 0 0 0 A

V T Assembler

00 00 ITOF Sa , Sb , Sc

00 01 ITOF.B Sa, Sb, Sc

00 10 ITOF.H Sa, Sb, Sc

10 00 ITOF Va , Vb , Sc

10 01 ITOF.B Va, Vb, Sc

10 10 ITOF.H Va, Vb, Sc

11 00 ITOF Va , Vb , Vc

11 01 ITOF.B Va, Vb, Vc

11 10 ITOF.H Va, Vb, Vc

01 00 ITOF/F Va, Vb, Vc

01 01 ITOF.B/F Va, Vb, Vc

01 10 ITOF.H/F Va, Vb, Vc

7.8.2 UTOF - Unsigned integer to�oating-point

Requires: FM

Convert an unsigned integer value to a �oating-pointvalue. The exponent of the resulting �oating-pointvalue is subtracted by the integer o�set provided by thesecond source operand before storing the �nal �oating-point value in the destination operand.

TODO

De�ne pseudocode.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 1 0 0 1 A

V T Assembler

00 00 UTOF Sa , Sb , Sc

00 01 UTOF.B Sa, Sb, Sc

00 10 UTOF.H Sa, Sb, Sc

10 00 UTOF Va , Vb , Sc

10 01 UTOF.B Va, Vb, Sc

10 10 UTOF.H Va, Vb, Sc

11 00 UTOF Va , Vb , Vc

11 01 UTOF.B Va, Vb, Vc

11 10 UTOF.H Va, Vb, Vc

01 00 UTOF/F Va, Vb, Vc

01 01 UTOF.B/F Va, Vb, Vc

01 10 UTOF.H/F Va, Vb, Vc

7.8.3 FTOI - Floating-point to signedinteger

Requires: FM

Convert a �oating-point value to a signed integer value,without rounding. The integer o�set provided by thesecond source operand is added to the �oating-pointexponent before the conversion.

TODO

De�ne pseudocode.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 1 0 1 0 A

V T Assembler

00 00 FTOI Sa , Sb , Sc

00 01 FTOI.B Sa, Sb, Sc

00 10 FTOI.H Sa, Sb, Sc

10 00 FTOI Va , Vb , Sc

10 01 FTOI.B Va, Vb, Sc

10 10 FTOI.H Va, Vb, Sc

11 00 FTOI Va , Vb , Vc

11 01 FTOI.B Va, Vb, Vc

11 10 FTOI.H Va, Vb, Vc

01 00 FTOI/F Va, Vb, Vc

01 01 FTOI.B/F Va, Vb, Vc

01 10 FTOI.H/F Va, Vb, Vc

34

7.8.4 FTOU - Floating-point to un-signed integer

Requires: FM

Convert a �oating-point value to an unsigned integervalue, without rounding. The integer o�set provided bythe second source operand is added to the �oating-pointexponent before the conversion.

TODO

De�ne pseudocode.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 1 0 1 1 A

V T Assembler

00 00 FTOU Sa , Sb , Sc

00 01 FTOU.B Sa, Sb, Sc

00 10 FTOU.H Sa, Sb, Sc

10 00 FTOU Va , Vb , Sc

10 01 FTOU.B Va, Vb, Sc

10 10 FTOU.H Va, Vb, Sc

11 00 FTOU Va , Vb , Vc

11 01 FTOU.B Va, Vb, Vc

11 10 FTOU.H Va, Vb, Vc

01 00 FTOU/F Va, Vb, Vc

01 01 FTOU.B/F Va, Vb, Vc

01 10 FTOU.H/F Va, Vb, Vc

7.8.5 FTOIR - Floating-point to signedinteger with rounding

Requires: FM

Convert a �oating-point value to a signed integer value,with rounding. The integer o�set provided by the sec-ond source operand is added to the �oating-point expo-nent before the conversion.

TODO

De�ne pseudocode.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 1 1 0 0 A

V T Assembler

00 00 FTOIR Sa, Sb , Sc

00 01 FTOIR.B Sa , Sb, Sc

00 10 FTOIR.H Sa , Sb, Sc

10 00 FTOIR Va, Vb , Sc

10 01 FTOIR.B Va , Vb, Sc

10 10 FTOIR.H Va , Vb, Sc

11 00 FTOIR Va, Vb , Vc

11 01 FTOIR.B Va , Vb, Vc

11 10 FTOIR.H Va , Vb, Vc

01 00 FTOIR/F Va , Vb, Vc

01 01 FTOIR.B/F Va, Vb, Vc

01 10 FTOIR.H/F Va, Vb, Vc

7.8.6 FTOUR - Floating-point to un-signed integer with rounding

Requires: FM

Convert a �oating-point value to an unsigned integervalue, with rounding. The integer o�set provided bythe second source operand is added to the �oating-pointexponent before the conversion.

TODO

De�ne pseudocode.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 1 1 0 1 A

V T Assembler

00 00 FTOUR Sa, Sb , Sc

00 01 FTOUR.B Sa , Sb, Sc

00 10 FTOUR.H Sa , Sb, Sc

10 00 FTOUR Va, Vb , Sc

10 01 FTOUR.B Va , Vb, Sc

10 10 FTOUR.H Va , Vb, Sc

11 00 FTOUR Va, Vb , Vc

11 01 FTOUR.B Va , Vb, Vc

11 10 FTOUR.H Va , Vb, Vc

01 00 FTOUR/F Va , Vb, Vc

01 01 FTOUR.B/F Va, Vb, Vc

01 10 FTOUR.H/F Va, Vb, Vc

7.8.7 FPACK - Floating-point pack

Requires: FM, PM

35

Convert and pack two �oating-point operands into asingle operand.

The precision of the two source operands are halved.The �rst source operand is packed and stored in theupper half of the destination operand, and the secondsource operand is packed and stored in the lower half ofthe destination operand.

TODO

De�ne pseudocode.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 0 0 1 1 1 0 A

V T Assembler

00 00 FPACK Sa, Sb, Sc

00 10 FPACK.H Sa , Sb , Sc

10 00 FPACK Va, Vb, Sc

10 10 FPACK.H Va , Vb , Sc

11 00 FPACK Va, Vb, Vc

11 10 FPACK.H Va , Vb , Vc

01 00 FPACK/F Va , Vb , Vc

01 10 FPACK.H/F Va, Vb, Vc

7.8.8 FUNPL - Floating-point unpacklow

Requires: FM, PM

Unpack the low half of a packed �oating-point pair. Thepreicison of the unpacked source �oating-point value isdoubled and stored in the destination operand.

TODO

De�ne pseudocode.

0791516212631

0 0 0 0 0 0 Ra Rb V 0 0 0 0 0 0 T 1 1 1 1 1 0 1 B

V T Assembler

00 00 FUNPL Sa, Sb

00 10 FUNPL.H Sa , Sb

10 00 FUNPL Va, Vb

10 10 FUNPL.H Va , Vb

7.8.9 FUNPH - Floating-point unpackhigh

Requires: FM, PM

Unpack the high half of a packed �oating-point pair.The preicison of the unpacked source �oating-pointvalue is doubled and stored in the destination operand.

TODO

De�ne pseudocode.

0791516212631

0 0 0 0 0 0 Ra Rb V 0 0 0 0 0 1 T 1 1 1 1 1 0 1 B

V T Assembler

00 00 FUNPH Sa, Sb

00 10 FUNPH.H Sa , Sb

10 00 FUNPH Va, Vb

10 10 FUNPH.H Va , Vb

36

7.9 Saturating and halving

arithmetic

7.9.1 ADDS - Signed add with satura-tion

Requires: SM

Compute the saturated sum of two signed integeroperands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 0 0 0 0 A

a ← sat(int(b) + int(c), bits)

V T Assembler

00 00 ADDS Sa , Sb , Sc

00 01 ADDS.B Sa, Sb, Sc

00 10 ADDS.H Sa, Sb, Sc

10 00 ADDS Va , Vb , Sc

10 01 ADDS.B Va, Vb, Sc

10 10 ADDS.H Va, Vb, Sc

11 00 ADDS Va , Vb , Vc

11 01 ADDS.B Va, Vb, Vc

11 10 ADDS.H Va, Vb, Vc

01 00 ADDS/F Va, Vb, Vc

01 01 ADDS.B/F Va, Vb, Vc

01 10 ADDS.H/F Va, Vb, Vc

7.9.2 ADDSU - Unsigned add with sat-uration

Requires: SM

Compute the saturated sum of two unsigned integeroperands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 0 0 0 1 A

a ← satu(uint(b) + uint(c), bits)

V T Assembler

00 00 ADDSU Sa, Sb , Sc

00 01 ADDSU.B Sa , Sb, Sc

00 10 ADDSU.H Sa , Sb, Sc

10 00 ADDSU Va, Vb , Sc

10 01 ADDSU.B Va , Vb, Sc

10 10 ADDSU.H Va , Vb, Sc

11 00 ADDSU Va, Vb , Vc

11 01 ADDSU.B Va , Vb, Vc

11 10 ADDSU.H Va , Vb, Vc

01 00 ADDSU/F Va , Vb, Vc

01 01 ADDSU.B/F Va, Vb, Vc

01 10 ADDSU.H/F Va, Vb, Vc

7.9.3 ADDH - Signed half add

Requires: SM

Compute the half sum of two signed integer operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 0 0 1 0 A

a ← (int(b) + int(c)) >>s 1

V T Assembler

00 00 ADDH Sa , Sb , Sc

00 01 ADDH.B Sa, Sb, Sc

00 10 ADDH.H Sa, Sb, Sc

10 00 ADDH Va , Vb , Sc

10 01 ADDH.B Va, Vb, Sc

10 10 ADDH.H Va, Vb, Sc

11 00 ADDH Va , Vb , Vc

11 01 ADDH.B Va, Vb, Vc

11 10 ADDH.H Va, Vb, Vc

01 00 ADDH/F Va, Vb, Vc

01 01 ADDH.B/F Va, Vb, Vc

01 10 ADDH.H/F Va, Vb, Vc

7.9.4 ADDHU - Unsigned half add

Requires: SM

Compute the half sum of two unsigned integer operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 0 0 1 1 A

a ← (uint(b) + uint(c)) >> 1

37

V T Assembler

00 00 ADDHU Sa, Sb, Sc

00 01 ADDHU.B Sa , Sb , Sc

00 10 ADDHU.H Sa , Sb , Sc

10 00 ADDHU Va, Vb, Sc

10 01 ADDHU.B Va , Vb , Sc

10 10 ADDHU.H Va , Vb , Sc

11 00 ADDHU Va, Vb, Vc

11 01 ADDHU.B Va , Vb , Vc

11 10 ADDHU.H Va , Vb , Vc

01 00 ADDHU/F Va , Vb , Vc

01 01 ADDHU.B/F Va, Vb, Vc

01 10 ADDHU.H/F Va, Vb, Vc

7.9.5 ADDHR - Signed half add withrounding

Requires: SM

Compute the rounded half sum of two signed integeroperands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 0 1 0 0 A

a ← (int(b) + int(c) + 1) >>s 1

V T Assembler

00 00 ADDHR Sa, Sb, Sc

00 01 ADDHR.B Sa , Sb , Sc

00 10 ADDHR.H Sa , Sb , Sc

10 00 ADDHR Va, Vb, Sc

10 01 ADDHR.B Va , Vb , Sc

10 10 ADDHR.H Va , Vb , Sc

11 00 ADDHR Va, Vb, Vc

11 01 ADDHR.B Va , Vb , Vc

11 10 ADDHR.H Va , Vb , Vc

01 00 ADDHR/F Va , Vb , Vc

01 01 ADDHR.B/F Va, Vb, Vc

01 10 ADDHR.H/F Va, Vb, Vc

7.9.6 ADDHUR - Unsigned half addwith rounding

Requires: SM

Compute the runded half sum of two unsigned integeroperands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 0 1 0 1 A

a ← (uint(b) + uint(c) + 1) >> 1

V T Assembler

00 00 ADDHUR Sa, Sb, Sc

00 01 ADDHUR.B Sa, Sb, Sc

00 10 ADDHUR.H Sa, Sb, Sc

10 00 ADDHUR Va, Vb, Sc

10 01 ADDHUR.B Va, Vb, Sc

10 10 ADDHUR.H Va, Vb, Sc

11 00 ADDHUR Va, Vb, Vc

11 01 ADDHUR.B Va, Vb, Vc

11 10 ADDHUR.H Va, Vb, Vc

01 00 ADDHUR/F Va, Vb, Vc

01 01 ADDHUR.B/F Va , Vb, Vc

01 10 ADDHUR.H/F Va , Vb, Vc

7.9.7 SUBS - Signed subtract with sat-uration

Requires: SM

Compute the saturated di�erence of two signed integeroperands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 0 1 1 0 A

a ← sat(int(b) - int(c), bits)

V T Assembler

00 00 SUBS Sa , Sb , Sc

00 01 SUBS.B Sa, Sb, Sc

00 10 SUBS.H Sa, Sb, Sc

10 00 SUBS Va , Vb , Sc

10 01 SUBS.B Va, Vb, Sc

10 10 SUBS.H Va, Vb, Sc

11 00 SUBS Va , Vb , Vc

11 01 SUBS.B Va, Vb, Vc

11 10 SUBS.H Va, Vb, Vc

01 00 SUBS/F Va, Vb, Vc

01 01 SUBS.B/F Va, Vb, Vc

01 10 SUBS.H/F Va, Vb, Vc

7.9.8 SUBSU - Unsigned subtract withsaturation

Requires: SM

38

Compute the saturated di�erence of two unsigned inte-ger operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 0 1 1 1 A

a ← satu(uint(b) - uint(c), bits)

V T Assembler

00 00 SUBSU Sa, Sb, Sc

00 01 SUBSU.B Sa , Sb , Sc

00 10 SUBSU.H Sa , Sb , Sc

10 00 SUBSU Va, Vb, Sc

10 01 SUBSU.B Va , Vb , Sc

10 10 SUBSU.H Va , Vb , Sc

11 00 SUBSU Va, Vb, Vc

11 01 SUBSU.B Va , Vb , Vc

11 10 SUBSU.H Va , Vb , Vc

01 00 SUBSU/F Va , Vb , Vc

01 01 SUBSU.B/F Va, Vb, Vc

01 10 SUBSU.H/F Va, Vb, Vc

7.9.9 SUBH - Signed half subtract

Requires: SM

Compute the half di�erence of two signed integeroperands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 1 0 0 0 A

a ← (int(b) - int(c)) >>s 1

V T Assembler

00 00 SUBH Sa , Sb , Sc

00 01 SUBH.B Sa, Sb, Sc

00 10 SUBH.H Sa, Sb, Sc

10 00 SUBH Va , Vb , Sc

10 01 SUBH.B Va, Vb, Sc

10 10 SUBH.H Va, Vb, Sc

11 00 SUBH Va , Vb , Vc

11 01 SUBH.B Va, Vb, Vc

11 10 SUBH.H Va, Vb, Vc

01 00 SUBH/F Va, Vb, Vc

01 01 SUBH.B/F Va, Vb, Vc

01 10 SUBH.H/F Va, Vb, Vc

7.9.10 SUBHU - Unsigned half subtract

Requires: SM

Compute the half di�erence of two unsigned integeroperands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 1 0 0 1 A

a ← (uint(b) - uint(c)) >> 1

V T Assembler

00 00 SUBHU Sa, Sb , Sc

00 01 SUBHU.B Sa , Sb, Sc

00 10 SUBHU.H Sa , Sb, Sc

10 00 SUBHU Va, Vb , Sc

10 01 SUBHU.B Va , Vb, Sc

10 10 SUBHU.H Va , Vb, Sc

11 00 SUBHU Va, Vb , Vc

11 01 SUBHU.B Va , Vb, Vc

11 10 SUBHU.H Va , Vb, Vc

01 00 SUBHU/F Va , Vb, Vc

01 01 SUBHU.B/F Va, Vb, Vc

01 10 SUBHU.H/F Va, Vb, Vc

7.9.11 SUBHR - Signed half subtractwith rounding

Requires: SM

Compute the rounded half di�erence of two signed in-teger operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 1 0 1 0 A

a ← (int(b) - int(c) + 1) >>s 1

39

V T Assembler

00 00 SUBHR Sa, Sb, Sc

00 01 SUBHR.B Sa , Sb , Sc

00 10 SUBHR.H Sa , Sb , Sc

10 00 SUBHR Va, Vb, Sc

10 01 SUBHR.B Va , Vb , Sc

10 10 SUBHR.H Va , Vb , Sc

11 00 SUBHR Va, Vb, Vc

11 01 SUBHR.B Va , Vb , Vc

11 10 SUBHR.H Va , Vb , Vc

01 00 SUBHR/F Va , Vb , Vc

01 01 SUBHR.B/F Va, Vb, Vc

01 10 SUBHR.H/F Va, Vb, Vc

7.9.12 SUBHUR - Unsigned half sub-tract with rounding

Requires: SM

Compute the rounded half di�erence of two unsignedinteger operands.

0791416212631

0 0 0 0 0 0 Ra Rb V Rc T 1 1 0 1 0 1 1 A

a ← (uint(b) - uint(c) + 1) >> 1

V T Assembler

00 00 SUBHUR Sa, Sb, Sc

00 01 SUBHUR.B Sa, Sb, Sc

00 10 SUBHUR.H Sa, Sb, Sc

10 00 SUBHUR Va, Vb, Sc

10 01 SUBH

mrisc32 instruction set manual version 2021- draft · 1.5.1 instruction word elds the eld names...

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