Part I: Periodic Interrupt Timer, MPC555 Interrupt Systems

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Periodic Interrupt TimerTimer has many uses

To implement a clockTo check user input periodicallyTo monitor environment changesTo switch between programs

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Periodic Interrupt Timer

count register

Adder

-1

mux

count

reset

clock zero? timer expires

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How does a timer work?

A timer is basically a counter of clock cycles.

Periodic Interrupt TimerTime Period

= (count + 1) × clock cycle time= (count + 1) / clock frequency

EX: The clock frequency is 5MHz.The needed time period is 10ms.What is the count value?

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Periodic Interrupt TimerEX: The clock frequency is 5MHz.

The needed time period is 1 second.The count register is 16-bit.

What is the count value, and how to make it work?

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Periodic Interrupt TimerHow to program a timer?

Set up count valueCheck if the timer expiresConfigure interrupt, if interrupt is to be usedRead leftover value, if the can be supported

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MPC555 PIT ProgrammingPTE

ClockDisable

PIF

16-bitModuluscounter

PITC

PS

PIE

PIT Interrupt

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PTE: PIT enable PIF: PIT freezePITC: PIT count value PS: PIT statusPIE: PIT interrupt enable PITR: leftover value in the counter

MPC555 PIT ProgrammingMPC555 PIT programming interface

1. PISCR: Periodic Interrupt Status & Control Register

2. PITC: PIT Counter

3. PITR: Periodic Interrupt Timer Register

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MPC555 PIT Programming

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PIT Enable0: disable decrement counter1: enable decrement counter

PInterrupt Enable0: disable interrupt1: enable interrupt

PIT Freeze0: no effect1: disable decrement counter if internal signal FREEZE is asserted

PIT Status0: no PIT int asserted1: PIT int asserted

0x002FC240

PS PIE PITF PTE

0 1 2 3 4 5 6 7

8 9 10 11 12 13 14 15

PIRQ

Interrupt levelfor PIT

PISCR: Periodic Interrupt Status & Control Register

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0

PITC

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PITC: PIT counter

PIT Time-out period = (PITC+1)/(PIT Frequency);assume 1MHZ oscillatorPIT Period = 1/(1MHz) = 1 microsecondPut 33000 in PITC to get 33 milliseconds interrupt period.

0x2F C244

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16Reserved

31

PIT: Leftover (current) count in PIT counter

Writes to PITR have no effect: read only.

If you want to read the current PIT count to estimate time to next PIT interrupt?

0x2F C248

PIT150

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.equ USIU_BASE_UPPER 0x2f

.equ PICSR_OFFSET 0xc240

.equ PITC_OFFSET 0xc244

.equ PITR_OFFSET 0xc248

; r4 base address of SIU regslis r4, USIU_BASE_UPPER

; set PICSR bits: PIRQ=08, PS=PS, PIE=1, PITF=0, PTE=0; so OS flag is cleared, interrupt is enabled, timer is; enabled, interrupt level is assigned, and device disabled

li r0,0x0800 sth r0,PICSR_OFFSET(r4)

;PITC = 33000 = 0x80e8 and store it in PITC li r5, 0x80e8

sth r5, PITC_OFFSET(r4)

;now enable PIT: PTE = 1 lhz r0, PICSR_OFFET(r4) ori r0, r0, 0x1 sth r0, PICSR_OFFSET(r4)

MPC555 Exception Processing

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ExternalInterrupt ESR

Interrupt controller

device 1 device 2 device n…

CPU

External interrupt exception

External Interrupts

Other ESR Other ESR

ISR 1 ISR 2 ISR n…

MPC555 Exception ProcessingGeneral Procedure of External Interrupt ESR1. Save machine context 2. Make execution recoverable and

enable external interrupt3. Save user registers4. Determine interrupt source5. Branch to ISR6. Restore user register contents7. Restore machine context8. Return to program execution

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MPC555 Exception ProcessingWhat registers should be saved by CPU upon

an exception?Should all registers be saved ALWAYS?Modern processors: Software saves almost all

registers

But who should save the PC, CPU or software?

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MPC555 Exception ProcessingAnother register: MSR (Machine State

Register)

User and supervisor modes: An ESR runs in the supervisor mode:Corresponding to the administrator privilegeMay access and change protected registers and

memory areas

How does the CPU switch to the supervisor mode?

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MPC555 Exception Processing

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Machine State Register (MSR)LE

LE=0Big-endian

RI

RI=1: recoverable

00DRIRIP0

IP=0: exceptionVector tableStarts at 0x000else 0xfff

PREE0

PR=0: supervisor =1: user

EE=ext. interrupt enable =0: disable =1:enable

MPC555 Exception ProcessingUpon an exception, the CPU

1. Puts the ESR address into PC (forces a jump to the ESR)

2. Change MSR bitsPR ← 0: Switches to supervisor mode

(0: supervisor, 1: user)EE ← 0: Disables further external interruptsRI ← 0: Indicates “not recoverable”

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MPC555 Exception ProcessingKey point: ALL register values, if changed,

must be saved and restored Include r0-r31, CR, LR, XER, PC, MSR and

others

ESR should save those register contents Can use stack But the CPU has changed the contents of PC

and MSR!

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MPC555 Exception ProcessingSRR0/SRR1: To save PC and MSRSolution: Use special registers to help save

themSRRx: Machine status Save/Restore RegistersSRR0 saves PC, SRR1 saves the changed bits

in MSR

How it works:1. The CPU saves PC to SRR0, MSR to SRR1*

2. The ESR saves SRR0/SRR1 into stack20

MPC555 Exception ProcessingProgramming methods for saving SRR0/SRR1:Example:mfspr srr0, r3 ; copy srr0 to r3 stw r3, 24(sp) ; save srr0 value…lwz r3, 24(sp) ; get srr0 value in r3mtspr srr0, r3 ; copy it to srr0

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Nested InterruptsIf the interrupt ESR or an ISR is running, can

the CPU accept another interrupt?

Is it desirable to accept another interrupt?

When cannot the CPU accept another exception?

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Nested InterruptsEE bit: Tell the CPU not to accept another

interrupt External interrupt Enable bit Reset to zero: The external interrupt

exception is ignored; the CPU keeps running

The CPU automatically resets the EE bit upon an exception

But the ESR may re-enable the EE bit

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Recoverable ExceptionsOther exceptions may happen during an

interrupt processingScenario: Stack overflow during the interrupt

processing

Interrupt processing is not always recoverableScenario: The stack overflow happens before

saving SRR0/SRR1Solution: Use the RI bit

The CPU automatically resets the RI bit The ESR may re-enable it

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