mp 8253,54 timer slides

8/3/2019 MP 8253,54 Timer Slides

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Engr 4862 Microprocessors

8253 / 8254 Timer

A PIT (programmable Interval Timer), used tobring down the frequency to the desired level

Three counters inside 8253/8254. Each worksindependently and is programmed separately to

divide the input frequency by a number from 1to 65536

There are 4 port address needed for a single8253/8254, given by A0, A1, and CS

CS A1 A0 Select0 0 0 Counter 0

0 0 1 Counter 1

0 1 0 Counter 20 1 1 Control Reg.


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8253 / 8254 Timer


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8253 / 8254 Timer


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8253 / 8254 Timer

Each of the three counter has 3 pins associatedCLK: input clock frequency

A square wave of 33% duty cycle

8253: 0 ~ 2 MHz, 8254: 0 ~ 8 MHz

OUT: can be square wave, or one shot

GATE: Enable (high) or disable (low) the counter

Data Pins: (D0 ~ D7)

Allow the CPU to access various registers inside the

8253/54 for both read and write operations. RD and

WR are connected to IOR and IOW of control bus.


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8253 / 8254 Timer

Each of the three counters must be programmedseparately

Control byte must be first written into the

control register. The 8253/54 must be initializedbefore use

The programmer can not only write the value of

the divisor into the 8253/54, but read the contentof the counter at any given time as well

All counters are down counters.


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8253 / 8254 Timer

To program a given counter to divide the CLKinput frequency, one must send the divisor to

that specific counters register.

Although all three counters share the samecontrol register, the divisor registers are separate

for each counter

Example: given the port addresses for 8253/54:Counter 0: 94H Counter 1: 95H

Counter 2: 96H Control Reg: 97H


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8253 / 8254 Timer

Task1: The instruction to send the control wordand count to counter 0 of the 8254

MOV AL, 00010111B;control word for counter 0MOV DX,0FF07H;point at 8254 control register

OUT DX,AL ; send control word

MOV AL,32H;load lower byte of countMOV DX,0FF01H;point to counter 0 count register

OUT DX,AL;send count to count register


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Shape of the 8253/54 Output

Given CLK = 1.193 MHz, the clock period ofinput frequency is 838 ns

If the number N loaded into the counter is even,both high and low pulse are the same length,which is N/2 * 838 ns

If the number N loaded into the counter is odd,the high pulse is (N+1)/2 * 838 ns and the low

pulse is (N1)/2 * 838 ns If N is odd, the high portion of the output

square wave is slightly wider than the low portion


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8253/54 Operation Modes

Mode 0: Interrupt on terminal countThe output is initially low, and remain low for the

duration of the count if GATE=1. When the terminal

count is reached, the output will go high and remain

high until a new control word or new count number

is loaded

Width of low pulse = N * T, where T is clock period

Example: GATE=1 and CLK = 1 MHzClock count N = 1000


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Mode 0: Interrupt on terminal countIf GATE becomes low at the middle of the count, the

count will stop and the output will be low. The countresumes when the GATE becomes high again This

in effect adds to the total time the output is low. Mode 1: HW triggered / programmable one shot

The triggering must be done through the GATE inputby sending a 0-to-1 pulse to it.

Steps: 1) Load the count register

2) A 0-to-1 pulse must be sent to the GATEinput to trigger the count


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8253/54 Operation Modes Mode 1: HW triggered / programmable one shot

In Mode 1, after sending the 0-to-1 pulse to GATE,OUT becomes low and stays low for a duration ofN*T, then becomes high and stays high until the

GATE is triggered againIf during the activation, a retriggered happened, then

restart the down counting

Mode 2: Rate Generator (Divide-by-N counter)

In Mode2, if GATE=1, OUT will be high for N*T,goes low only for one clock pulse, then counter isreloaded automatically, and the process continuesindefinitely.Whole period: (N+1) * T


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Mode 3: Square wave rate generatorMost commonly used

Mode 4: Software triggered strobe

Similar to Mode2, except that the counter is notreloaded automatically

In Mode4, if GATE=1, the output will go high whenloading the count, it will stay high for duration N*T.After the count reaches zero, it becomes low for oneclock pulse, then goes high again and stays high untila new command word or new count is loaded

To repeat the strobe, the count must be reloaded


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Mode 5: Hardware triggered strobeSimilar to Mode4, except that the triggering must be

done with the GATE input

The count starts only when a 0-to-1 pulse is sent to the

GATE input

If GATE retriggered during the counting, it will

restart the down counting


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8253 / 8254 Timer


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8253 / 8254 Timer


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8253 / 8254 Timer


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8253 / 8254 Timer


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8253 / 8254 Timer


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8253 / 8254 Timer


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8253 / 8254 Timer


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8253 / 8254 Timer


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8253 / 8254 Timer


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8259 8259 is Programmable Interrupt Controller (PIC)

It is a tool for managing the interrupt requests.

8259 is a very flexible peripheral controller chip:

PIC can deal with up to 64 interrupt inputs

interrupts can be masked

various priority schemes can also programmed.

originally (in PC XT) it is available as a separate IC

Later the functionality of(two PICs) is in themotherboards chipset.

In some of the modern processors, the functionality of

the PIC is built in.


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Pin description 8-bit bi-directional data bus, one address line is needed,

PIC has two control registers to be programmed, you can think of them as two

output ports or two memory location.

The direction of data flow is controlled by RD and WR.

CS is as usual connected to the output of the address decoder.

Interrupt requests are output on INT which is connected tothe INTR of the processor. Int. acknowledgment is received

by INTA.

IR0-IR7 allow 8 separate interrupt requests to be inputted

to the PIC.

sp/en=1 for master , sp/en=0 for slave.

CAS0-3 inputs/outputs are used when more than one PIC to

cascaded.


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FIGURE 9-4 Block diagram and pin definitions for the 8259A Programmable Interrupt Controller (PIC). (Courtesy of Intel Corporation.)

John UffenbeckThe 80x86 Family: Design, Programming, and Interfacing,

3e

Copyright 2002 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.


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OPERATION PIC is to be initialized and programmed to control

its operation. The operation in simple words:

when an interrupt occurs , the PIC determines the highest

priority, activates the processor via its INTR input, and

sends the type number onto the data bus when the

processor acknowledges the interrupt.

Priority:

What is used in PC isfully nested mode. That is the lowest

numbered IRQ input has highest priority. Lower priority

interrupts will not be forwarded to the processor until the

higher priority interrupts have been serviced.


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FIGURE 9-12 8259A initialization sequence. (Courtesy of Intel Corporation.)

John Uffenbeck

The 80x86 Family: Design, Programming, and Interfacing,

3e

Copyright 2002 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.


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FIGURE 9-13 8259A operation control word format. (Courtesy of Intel Corporation.)

John Uffenbeck

The 80x86 Family: Design, Programming, and Interfacing,Copyright 2002 by Pearson Education, Inc.

mp 8253,54 timer slides

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