MOSIS Scalable CMOS Design Rules

�revision ��

Jen�I Pi

the MOSIS ServiceInformation Sciences Institute

University of Southern California���� Admiralty Way

Marina del Rey� CA �����pi�isiedu

August � ���

� Introduction

��� SCMOS Design Rules

This document de�nes the o cial layout design rules for MOSIS scalable CMOS �SCMOS�design technology It supercedes all previous revisions

In SCMOS technology� circuit geometries are drawn according to Mead and Conway�s��based methodology ��� The unit of measurement� �� can easily be scaled to di�erentfabrication processes as semiconductor technology advances

A user design submitted to MOSIS in SCMOS technology should be in either CalmaGDSII format �� or Caltech Intermediate Form �CIF version ��� ��� Each design hasa technology designation that goes with it for the purpose of MOSIS�s data prep At themoment� three designations are used to specify CMOS processes Each designation may haveone or more options associated for the purpose of either �� special features for the targetprocess or ��� the presence of novel device in the design At the time of writing� MOSIS iso�ering six CMOS processes from three di�erent foundries with drawn feature sizes rangingfrom �� �m down to �� �m

A list of the things that have either been revised or added since our last release can befound in Appendix A Please refer to the speci�c sections for detailed descriptions

� Standard SCMOS

The standard CMOS technology accessed by MOSIS is a single polysilicon� double metal�bulk CMOS process with enhancement�mode n�MOSFET and p�MOSFET devices ���

��� Well Flavor

Three types of designation are used to indicate the �avor of the well �substrate� used forfabrication as shown in Table

Designation DescriptionSCN Scalable CMOS N�wellSCP Scalable CMOS P�wellSCE Scalable CMOS Either�well

Table � SCMOS well �avor designations

The SCN and SCP designations with a submitted project are designed for fabricationof the speci�ed well only For convenience� in both cases� a project may include the �other�well� but it will always be ignored SCE projects are used for fabrication in any CMOSprocess� N�well or P�well �either� A project with SCE designation must include both wells�and correspondingly� well�substrate contacts for proper bias� For any given fabricationprocess� the �other� well will be ignored during the mask generation If twin�tub processesare o�ered in the future� both wells will be used

��� SCMOS Options

SCMOS options are used to designate projects which use additional layers beyond the stan�dard CMOS technology Each option is named by a designator that is tacked onto the basicdesignator for its well �avor Reader should note that not all possible combinations �withwell �avor� are actually available The currently available SCMOS options are listed in Table�

In addition to the options in Table �� two undeclared options also exist One withrespect to the existence of high voltage MOSFET devices� the other� a tight metal rule forhigh�density metal interconnections For options available to speci�c process� please refer toTable � for the current MOSIS o�erings

��� SCMOS O�erings

MOSIS is currently o�ering the fabrication processes as shown in Table � For each process�the list of appropriate SCMOS technology designations is listed Note that whenever SCNxxappears in the table� SCExx is also appropriate Likewise� whenever SCPxx appears� SCExxis also appropriate

�CCD layer not included��CCD layer not included�

�

Designation Long form DescriptionE Electrode Adds a second polysilicon layer �electrode�

that can serve as either one of electrode of a polycapacitor or as a gate for transistors A contactlayer �electrode contact� to metal also exists

A Analog Adds electrode layer �as in E option� plus apbase layer for the construction of vertical NPNtransistor A buried ccd layer is also presentfor buried�channel CCD applications

�M Triple Metal Adds second via �via�� and third metal �metal��layers

LC Linear Capacitor Adds a cap well layer for the implementation oflinear capacitors

MEMS Micromechanical Adds two new layers� mems open andSystems mems etch stop for the purpose of micro�

mechanical device construction

Table �� SCMOS technology options

Foundry Process Lambda OptionsOrbit �� �m N�well � �m SCNA� SCNE� SCN� SCNA MEMSOrbit �� �m P�well � �m SCPE� SCP� SCPE MEMSAMI � �m N�well �� �m SCNA�� SCNE� SCN� High VoltageOrbit � �m N�well �� �m SCNA�

HP AMOSI�CMOS�� �� �m SCNLC� SCN� Tight MetalHP CMOS��B�G��TB ������ �m SCN�M� SCN� Tight Metal

Table �� MOSIS SCMOS technology o�erings

�

� CIF and GDS Layer Speci�cation

Design geometries �or mask features� can be represented either in GDS�II or Caltech Inter�mediate Form �CIF Version ��� While the former is coded in binary format� the latter is aplain text �le and can be easily interpreted For detailed syntax and semantic speci�cationsof Calma�GDS�II or CIF� please refer to �� and ��� respectively

In GDS II format� a mask layer is speci�ed by a layer number between � and �� MOSISnow reserves layers numberd from � to �� for mask speci�cation and future extensionLayers de�ned out of this range can be used by customers for their own purpose MOSISwill ignore all geometry information on these layers �� to �� and ��� and map it to the CIFcomment layer �CX� if necessary In this revision� � new layers are added starting from layernumber �

� CVP �layer �� is used to indicate high�voltage p�type area More comprehensiveinformation can be found in ���

� CVN �layer ��� is used to indicate high�voltage p�type area

� COP �layer ��� is used to indicate substrate pit opening area for MEMS devices

� CPS �layer ��� is used to indicate substrate p� etching�stop area for MEMS devices

� CCC �layer ��� is used for generic contact

� XP �layer ��� is used to indicated pad location

Users should be aware that there exist only one type of physical contact �ie between�rst metal and poly or active�� though several have been de�ned for historical reason andare retained for backward compatibility A complete list of SCMOS layers can be found inTable � on next page

� Sub�micron Rules

The SCMOS design rules have been historically designed for � � �� micron CMOS tech�nology To take full advantage of advanced submicron process technology� a set of rules havebeen selected to be modi�ed to �t our foundry�s rules

Table � lists those rules in MOSIS�s HP CMOS��G��TB processes that are di�erent betweenSCN�M and SCN�M SUBM technology speci�cation with � equals to ������ and ����� �m respec�tively

�

SCMOS layer CIF name GDS II number GDS II typeP HIGH VOLTAGE CVP � �N HIGH VOLTAGE CVN �� �MEMS OPEN COP �� �MEMS ETCH STOP CPS �� �PADS XP �� �P WELL CWP � �N WELL CWN �� �ACTIVE CAA �� �P PLUS SELECT CSP �� �N PLUS SELECT CSN �� �POLY CPG �� �CONTACT CCC� CCP� CCA� CCE ��� ��� ��� �� �METAL CMF �� �VIA CVA �� �METAL� CMS � �GLASS COG �� �ELECTRODE CEL �� �BURIED CCD CCD �� �PBASE CBA �� �CAP WELL CWC �� �VIA� CVS � �METAL� CMT �� �COMMENT CX � � ��� �� �

Table �� SCMOS technology CIF and GDS layers

�

SCMOS SCMOS SCMOS SUBMDescription Rule �Tight Metal�

� � �������m � � �������m � � ������mWELL W � � �WELL S DIFF � � � �WELL O ACT XTOR �� � � �WELL S ACT XTOR �� � � �POLY S �� � � �CON S ����� � � �M W � � � �M S �� � � �M� W � � � �M� S �� � � �M� W � � � �M� S �� � � �

Table �� SCMOS options for CMOS��G��TB

�

� SCMOS Design Rules

Well �CWN� CWP

��� Minimum width ����� Minimum spacing between wells at di�erent potential ��� Minimum spacing between wells at same potential � or ��� Minimum spacing between wells of di�erent type

�if both are drawn� �

1.4

CWNCWNCWN

CWP

1.31.2

1.1

�

Active �CAA

��� Minimum width ��� Minimum spacing �� Source�drain active to well edge ��� Substrate�well contact active to well edge �� Minimum spacing between active of di�erent implant � or �

CAA

CAA CAA

CAA

CAA

CAA

CSP

CSP

CSN

CSN

_

region_

P

regionN

2.1

2.52.2

2.1

2.3 2.4

2.3 2.4

2.52.2

�

Poly �CPG

�� Minimum width ��� Minimum spacing �� Minimum gate extension of active ��� Minimum active extension of ploy � Minimum �eld poly to active �

CAA

CPG

CPG

CAA

3.4

3.5

3.1

3.2

3.3

�

Select �CSN� CSP

��� Minimum select spacing to channel of transistor toensure adequate source�drain width

��� Minimum select overlap of active ��� Minimum select overlap of contact ���� Minimum select width and spacing �

�Note� P�select and N�select may be coincident� butmust not overlap�

4.3

CCA

CSP CSN

CAA

CPG

CAA

CSPCSN

CWP CWN

4.3

4.2

4.1

�

Simple Contact to Poly �CCP

���a Exact contact size � � � ���a Minimum poly overlap �� ��a Minimum contact spacing �

5.2.a

5.3.a

5.1.a

CCP

CPG

Simple Contact to Active �CCA

���a Exact contact size � � ����a Minimum active overlap �� ��a Minimum contact spacing ����a Minimum spacing to gate of transistor �

6.3.a

6.2.a

6.4.a

6.1.a

CCA

CAA

CPG

CAA

�

Alternative� Contact to Poly �CCP

���b Exact contact size � � � ���b Minimum poly overlap � ��b Minimum contact spacing � ���b Minimum spacing to other poly � � �b Minimum spacing to active �one contact� � ��b Minimum spacing to active �many contacts�

5.5.b

5.4.b

5.1.b

5.2.b

5.6.b

5.3.b

CCP

CCP

CAA

CPG

CAA

�If you have di�culties with half lambda rule�

�

Alternative� Contact to Active �CCA

���b Exact contact size � � ����b Minimum active overlap ���b Minimum contact spacing ����b Minimum spacing to di�usion active � �b Minimum spacing to gate of transistor ���b Minimum sapcing to �eld poly �one contact� ����b Minimum spacing to �eld poly �many contacts� ���b Minimum spacing to poly contact �

6.7.b

6.8.b6.2.b

6.1.b

6.6.b

6.5.b

6.3.b

6.4.b

CCA

CAA

CPG

CAA

�If you have di�culties with half lambda rule�

�

Metal� �CMF

��� Minimum width ����a Minimum spacing ����b� Minimum tight metal spacing ��� Minimum overlap of poly contact ���� Minimum overlap of active contact �

CCP

CCA

CPG

CAA

CMF

CMF

7.4

7.3

7.2

7.1

�Only allowed between minimum width wires� otherwise use regular spacing rule�

�

Via� �CVA

��� Exact size � � ���� Minimum via� spacing �� Minimum overlap by metal� ���� Minimum spacing to contact ��� Minimum spacing to poly or active edge �

8.5

8.5CAA

CVA

CCA

CVA

CMSCMF

CAA

CPG 8.4

8.3

8.2

8.1

�

Metal� �CMS

��� Minimum width ����a Minimum spacing �����b� Minimum tight metal spacing �� Minimum overlap of via� �

9.2.a9.2.b

CMSCVA

CMS

CMF

9.3

9.1

�Only allowed between minimum width wires� otherwise use regular spacing rule�

�

Overglass� �COG

�m���� Minimum bonding pad width ��� � ������� Minimum probe pad width � � � ��� Pad overlap of glass opening ���� Minimum pad spacing to unrelated metal� ���� Minimum pad spacing to unrelated metal�� poly�

electrode or active �

CMS CMF

CMS

COG

10.5

10.4

10.3

10.210.1

�Rules in this section are in unit of �m��And metal� if triple metal used�

�

Electrode for Capacitor �CEL Analog Option

���� Minimum width ���� Minimum spacing ��� Minimum poly overlap ����� Minimum spacing to active or well edge ���� Minimum spacing to poly contact

CEL

CMF

CWNCPG

CEL

11.5

11.4

11.3

11.2

11.1

�

Electrode for Transistor �CEL Analog Option

���� Minimum width ����� Minimum spacing ��� Minimum electrode gate overlap of active ����� Minimum spacing to active ���� Minimum spacing or overlap of poly ���� Minimum spacing to poly or active contact

CEL12.6

12.6CCA

CCE

12.2

12.5

12.4

12.3

12.1

CAA

CPG

CEL

��

Electrode Contact �CCE Analog Option

��� Exact contact size � � ���� Minimum contact spacing ��� Minimum electrode overlap �on capacitor� ��� Minimum electrode overlap �not on capacitor� ��� Minimum spacing to poly or active

13.5

CPGCAA

13.5

13.4

13.3

13.2

13.1

CMF

CEL

CPG

CEL

�

Via� �CVS Triple Metal Option

���� Exact size � � ����� Minimum spacing ��� Minimum overlap by metal� ����� Minimum spacing to via� �

CVA

CVS

CVA

CMS

CMT

14.3

14.414.1

14.1

14.2

��

Metal� �CMT Triple Metal Option

� �� Minimum width � �� Minimum spacing to metal �� � Minimum overlap of via� �

15.1

15.3

15.2

CMT

CVSCMT

��

NPN Bipolar Transistor �CBA Analog Option

��� All active contact � � ���� Minimum select overlap of emitter contact �� Minimum pbase overlap of emitter select ���� Minimum spacing between emitter select and base select ��� Minimum pbase overlap of base select ��� Minimum select overlap of base contact ���� Minimum nwell overlap of pbase ��� Minimum spacing between pbase and collector active ���� Minimum active overlap of collector contact ����� Minimum nwell overlap of collector active ���� Minimum select overlap of collector active �

CCA CCACCA

CWN

CSN

CSN CSPCAA

CBA

16.11

16.10

16.9

16.8

16.7

16.6

16.516.4

16.3

16.2

16.1

��

Capacitor Well �CWC Linear Capacitor Option

���� Minimum width ������ Minimum spacing ���� Minimum spacing to external active ���� Minimum overlap of active

CWPCWC

CAACWN

CWC

CAA

17.4

17.3 17.2

17.1

��

Linear Capacitor �Linear Capacitor Option

���� Minimum width ���� Minimum poly extension of active ���� Minimum active overlap of poly ���� Minimum poly contact to active ���� Minimum active contact to poly �

CCA

CWC

CAA

CPG

18.1

18.318.5

18.4

capacitor

linear

18.2

��

Buried Channel CCD �CCD Analog Option

���� Minimum CCD channel active width ����� Minimum CCD channel active spacing ���� Minimum CCD implant overlap of channel active ����� Minimum outside contact to CCD implant ��� Minimum select overlap of electrode �or poly� ���� Minimum poly�electrode overlap within channel active ����� Minimum contact to channel electrode �or poly� �

19.5

19.7

19.7

19.1

19.4

19.2CAA

CSN

CELCEL

CPGCPG

CCD

CEL

CPG

CSN

CAA

19.6

19.5

19.4

19.3

19.1

�Not for all processes

��

References

�� Cadence Design Systems� Inc�Calma GDSII Stream Format Manual� Feb ��� Release��� Documentation No� B��E���

��� J Marshall� M Gaitan� M Zaghloul� D Novotny� V Tyree� J�I Pi� C Pi�n�a� andW Hansford Realizing suspended structures on chips fabricated by CMOS foundryprocesses through the MOSIS service Technical Report NISTIR������ National Instituteof Standards and Technology� US Department of Commerce� Gaithersburg� MD� ���

��� C Mead and L Conway Introduction to VLSI Systems Addison�Wesley� ���

��� N H E Weste and K Eshraghian Principles of CMOS VLSI Design� A System Per�

spective Addison�Wesley� �nd edition� ���

��