Moorestown Platform: Based on Lincroft SoC Designed for Next Generation Smartphones

HOT CHIPS 2009

August 24 2009

Rajesh PatelLead Architect, Lincroft SoCIntel Corporation

2

Legal Disclaimer

• INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life-saving, life-sustaining, critical control or safety systems, or in nuclear facility applications.

• Intel may make changes to dates, specifications, product descriptions, and plans referenced in this document at any time, without notice.

• This document may contain information on products in the design phase of development. The information here is subject to change without notice.

• Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

• Intel, the Intel logo, Centrino, Centrino logo, Core Inside, Intel386, Intel486, Intel Core, Intel Inside, Intel Inside logo, Intel SpeedStep, Itanium, MMX, Pentium, and Pentium Inside, are trademarks of Intel Corporation in the U.S. and other countries.

• *Other names and brands may be claimed as the property of others.

• Copyright © 2009 Intel Corporation. All rights reserved.

Agenda

• Moorestown Platform Overview

• Moorestown Platform Re-Partitioning

• Lincroft SoC: Designed for• High Performance

• Low Power

• Summary

3

4

MedfieldBoard Size - Reduced

Standby Power - Lower

Major Reductions in Power and Form Factor

2008 2009/2010 2011

Power and Form Factor Reductions On Track Moorestown Idle Is Similar To Phone Level Power

MoorestownBoard Size – Reduced 2x

Standby Power Up to 50x*

MenlowBoard Size 8,500 sq mm

Standby Power 1.6W

Forecast

MedfieldMoorestown

•Moorestown Platform Idle power reduction (based on current platform features) compared to Menlow Platform•Drawings are not to scale

Forecast

5

Moorestown Platform OverviewLINCROFT (45nm)

LANGWELL (65nm)

BRIERTOWN

IntegratedPMIC

SDIO Ports

NANDController

USB Controller

Audio Codec

MIPI CSI Interface

. . . . . .

ATOM uLPCPU core

Hardware Video Acceleration

2D / 3D Graphics

Display Controller

Memory Controller

WiFi a/b/g/n

WiMAX

BT

GPS

EVANS PEAK

3G

Today’s Focus

Moorestown Platform Re-Partitioning

66

Menlow (CPU+IOH)

Graphics

South Bridge IOs

Video Decode

Memory Controller

Bus Interface and Coherency engine

Display

ATOM CPU45nm

Graphics Video Decode

Memory ControllerDisplay

Video Encode

Link to Langwell

Langwell

ATOM uLP CPU Core• 45 nm HighK SoC

Process• Intel Hyper Threading

support

Internal Display• LVDS • MIPI-DSI

Internal Graphics• OpenGL ES2.0• OpenVG 1.0

Memory Support• LPDDR1 & DDR2 • Single Channel• x32 bit interface

ATOM uLP CPU Core

Scalable Bus Interface and Coherency engine

Re-Partitioning using 45nm SoC process Higher Performance and Ultra Low Power

Moorestown (CPU+IOH)

Video Decode and Encode

Portedto 45nmSoCprocess + NewLow Power Features Lincroft

Lincroft Innovation Vectors

7

High Performancefor amazing Internet Experience

Dramatically Lower Power Small SizeFor Smartphone Form Factor

LINCROFTINNOVATION

Significant Advancement on all Key Vectors

Upto 50x platform idle power*

* Moorestown Platform Idle power reduction (based on current platform features) compared to Menlow Platform

Wide range of scalable frequencies for multimediablocks

Intel Hyper threading technology

Bus Turbo Technology

Burst Mode technology

8

Lincroft High Performance Innovation

9

Large Range of Scalable Frequencies forMultimedia Engines

DDR_clk0_div

DDR_clk1_div

Gfx_clk_div

VideoD_div

Core_clk div

Bypass_ clk_div

VideoE_div

Display_div

GFX_Freq_ratio

VideoD_Freq_ratio

VideoE_Freq_ratio

Display_Freq_ratio

Bus_Freq_ratio

Bypass enable

DDR_Freq_ratio

DDR_Freq_ratio

DDR_clk0_selector

DDR_clk1_selector

Gfx_clk_selector

VideoD_clk_selector

Core_clk_selector

Bypass_ selector

VideoE_clk_selector

Display_clk_selector

Pre_GFX_clock

Pre_VideoD_clock

Pre_VideoE_clock

Pre_Display_clock

Pre_Bus_clock

Bypass _clocks

Pre_DDR_clock

Pre_DDR_clock1

Bus_clock

DDR_clock0

DDR_clock1

Gfx_clock

VideoD_clock

VideoE_clock

Display_clock

Scalability enables Lincroft SoC into wide spectrum of FFs

Intel Hyper-threading Technology

10

Hyperthreading Performance Increase in an In-order Machine

1.36

1.19

1.39

1.17

1

1.1

1.2

1.3

1.4

1.5

performance power

MT-EEMBC

SPECint2KRate

Hyper-threading technology provides excellent Performance/Power efficiency

Source* : Intel Testing. Specint2k and EEMBC run in Single Threaded / Hyper Threaded Mode on Linux. For Performance the score for each binary is calculated based on the runtimes; For Power, the effective capacitance or C-dyn is measured per binary on each of the benchmark while running in ST and HT modes. The difference in C-dyn and thus total power difference is calculated for ST and HT modes. Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, visit Intel Performance Benchmark Limitations

“Bus Turbo Mode” -- Further Performance Boost

11

“Bus Turbo Mode” substantially reduces memory latency and provides higher bus BW

Bus

Fr

eqCPU FREQUENCY

PRE-DEFINED THRESOLDTO ENABLE BUS TURBO

Bus TurboLFM

MotivationTo reduce memory latency and increase bus BW when CPU bursting at higher frequencies

ImplementationHW dynamically increases BUS frequency at pre-set CPU frequency No need to re-lock PLL that provides clock to busUses clock divider

12

Burst Mode -- Addl Performance Headroom

12

PO

WE

R

FREQUENCY

BURST MODE

HFMLFM

ULFM

OPPORTUNISTIC RESIDENCY

RECOVERY POINTS

SUSTAINEDTHERMAL

LIMITTDP

Burst mode provides on-demand performance without impacting thermal design

Burst if Temparature < Tj or Tskin

TDP

POW

ER

No-Burst

TIME

Tjmax

Tskin

limit

FREQ

Time (t1) in C0-state Time (t2) in C0-state

BU

RST M

OD

E

Idle

Taking advantage of Thermal headroom on Tj and Tskin by increasing CPU frequency for short duration When Tj and Tskin limits are violated, System throttles to Recovery pointsOptimizes consumed energyEnergy(WHr)=Power x timeRace to idleSaves energy if t2/t1 < p1/p2

Idle

Low power architecture featuresMIPI-DSI LP-DDR1HW accelerators for Video Decode/Encode

Enhanced Geyserville to support ULFM

Lincroft CPU Power C-states

Lincroft Distributed Power Gating

13

Lincroft Low Power Innovations

Enhanced Geyserville (eGVL)

14

eGVL mode provides additional range of low power operating point

Bus

Fr

eq

CPU FREQUENCY

PRE-DEFINED THRESOLDTRIGGERS eGVL

Enhanced Geyserville

LFM

ULFM

Motivation To provide lowest possible

CPU frequency To enable “As many P-states

as possible” below LFM at Vmin Linear savings of average

power when CPU is not doing anything useful while in C0 state (cV2F)

Implementation Added P-states below LFM at

Vmin OS can now request CPU to

transition to these new P-states

1515

Lincroft CPU Power C-states

Core voltage

Core clock

PLL

L1 caches

L2 caches

Wakeup time

Power

C0 HFM C0 LFM C1/C2 C4 C6

OFF OFF OFF

OFF OFF

Partial flush off

active active

offflushedflushed

C0 ULFM

active

Lincroft SoC: IREM image of Full ON

1616

Aggressive Distributed Power Gating enables up-to 50x reduction in idle power*

Multiple Physical power Islands

Distributed power gating to enable fine grain power management

SW interface for Active Island power management

HW managed sequencing of power ON and OFF

* Moorestown Platform Idle power reduction (based on current platform features) compared to Menlow Platform

vs. Power Gated

Summary

Moorestown: Based on Lincroft SoC, Designed for High Performance for amazing Internet Experience Dramatically Lower Power – Upto 50x lower idle power Small Size for Next Generation Smartphones

Lincroft High Performance Innovation Wide range of scalable frequencies for multimedia blocks Intel Hyper threading technology Bus Turbo Technology Burst Mode technology Intel 45nm SoC High-K process technology

Lincroft Low Power Innovation Low power architecture features Enhanced Geyserville to support ULFM CPU C-states Lincroft Distributed Power Gating

17

Thank you

Lincroft SoC, Langwelland Moorestown

platform team

18

�Moorestown Platform: �Based on Lincroft SoC Designed for Next �Generation Smartphones����HOT CHIPS 2009��August 24 2009���Rajesh Patel�Lead Architect, Lincroft SoC �Intel CorporationSlide Number 2AgendaSlide Number 4Moorestown Platform Overview�Moorestown Platform Re-PartitioningLincroft Innovation VectorsLincroft High Performance InnovationLarge Range of Scalable Frequencies for�Multimedia Engines Intel Hyper-threading Technology“Bus Turbo Mode” -- Further Performance Boost�Burst Mode -- Addl Performance Headroom�Lincroft Low Power InnovationsEnhanced Geyserville (eGVL)Slide Number 15Lincroft SoC: IREM image of Full ON �SummarySlide Number 18