moore mealy slides
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Computer Science 141
omput ng Har wareFall 2008
Harvard University
Instructor: Prof. David Brooks
Computer Science 141
David Brooks
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Next couple of weeks
Next three lectures on FSM Design
Take-home midterm will be handed out Wednesday 11/5(after class) due Friday 11/7 at 5pm
NO Lab the week of 11/3
Review Session Monday 11/3?
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Finite State Machine (FSM)
Consists of:
State re ister that
CLK
Store the current state and Load the next state at the clock edge
NextState
CurrentState
S S
Combinational logic that
Next StateLogic
Next Computes t e next state
Computes the outputsState
Output
CL
Logic
Outputs
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Moore vs. Mealy machines
block diagrams
CL CL
nputs
outputssta
te
clock
Moore machine
CL
inputs outputs
ate
clock
s
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Mealy machine
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Moore Machine
CurrentExcitation
Inputs
Outputs
Clock in ut
Clock
clock
inputs
state
outputs
Computer Science 141
David Brooks
Moore machine timing
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Mealy Machine
Inputs
State
Excitation Outputs
Clock input
Clock
clock
inputs
state
outputs
Computer Science 141
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Mealy machine timing
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Moore vs. Mealy machines
timing of input, state, and output changes
clock
state
ou pu s
Moore machine timing Mealy machine timing
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Mealy vs. Moore: Design Example
function: assert output if 2 or more 1s in a row
state diagram:
0[0]
reset 0
0
reset 0/0
1/1
0 1[0]
1
1
2[1]
1
Moore machine Mealy machine
advantages/disadvantages Mealy often has fewer states than Moore machine since it associates outputs
with transitions
Computer Science 141
David Brooks
Mealy machine can fall victim to glitches since outputs are asynchronous
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Moore vs. Mealy FSM
Alyssa P. Hacker has a snail that crawls down a paper tape
with 1s and 0s on it. The snail smiles whenever the last four
digits it has crawled over are 1101. Design Moore and MealyFSMs of the snails brain.
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State Transition Diagrams
reset
Moore FSM1
S00
S10
S20
S30
S41
001 0
0
reset1/1
Mealy FSM
S0 S1 S2 S3
0/0 1/0
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0/0
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Moore FSM State Transition Table
Current State Inputs Next State
S S S A S' S' S'
0 0 0 00 0 0 1
State Encoding
S0 0000 0 1 0
0 0 1 1 S1 001
0 1 0 1
0 1 1 0
S3 011
0 1 1 1
1 0 0 0
S4 100
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1 0 0 1
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Moore FSM State Transition Table
Current State Inputs Next State
S S S A S' S' S'
0 0 0 0 0 0 00 0 0 1 0 0 1
State Encoding
S0 0000 0 1 0 0 0 0
0 0 1 1 0 1 0 S1 001
0 1 0 1 0 1 0
0 1 1 0 0 0 0
S3 011
0 1 1 1 1 0 0
1 0 0 0 0 0 0
S4 100
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1 0 0 1 0 1 0
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Moore FSM Output Table
Current State OutputS2 S1 S0 Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
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Moore FSM Output Table
Current State OutputS2 S1 S0 Y
0 0 0 0
0 0 1 0 Y = S2
0 1 0 0
0 1 1 0
1 0 0 1
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Mealy FSM State Transition and Output Table
Current State In ut Next State Out ut
S1 S0 A S'1 S'0 Y0 0 0 State Encoding
0 0 1
0 1 0
0 1 1
S0 00
S1 01
1 0 0
1 0 1
S2 10
1 1 0
1 1 1
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Mealy FSM State Transition and Output Table
Current State In ut Next State Out ut
S1 S0 A S'1 S'0 Y0 0 0 0 0 0 State Encoding
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
S0 00
S1 01
1 0 0 1 1 0
1 0 1 1 0 0
S2 10
1 1 0 0 0 0
1 1 1 0 1 1
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Moore FSM Schematic
S2
S'2
Y
CLKA
'11
S0
S'0
Reset
SS
0
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S2
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Mealy FSM Schematic
A
S'1 S1 Y
S'0
Reset
S0
S0
S
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Moore and Mealy Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10
CLK
Reset
Moore Machine
A
S S0 S3?? S1 S2 S4 S4S2 S3 S0
1 1 0 1 1 0 1 01
S2
Mealy Machine
Y
S S0 S3?? S1 S2 S1 S1S2 S3 S0S2
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Timing
Flip-flop samplesD at clock edge
Similar to a photograph,D must be stable around the clockedge
IfD is changing when it is sampled, metastability can occur
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Input Timing Constraints
Setup time: tsetup = time before the clock edge that data must
be stable i.e. not chan in
Hold time: thold = time afterthe clock edge that data must bestable
Aperture time: ta = time around clock edge that data must be
stable (ta = tsetup + thold)
tsetup
D
thold
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ta
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Output Timing Constraints
Propagation delay: tpcq = time after clock edge that the output
is uaranteed to be stable i.e., to sto chan in
Contamination delay: tccq = time after clock edge that Qmight be unstable (i.e., start changing)
CLK
Q
ccqtpcq
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Dynamic Discipline
The input to a synchronous sequential circuit must be stable
durin the a erture setu and hold time around the clock
edge. Specifically, the input must be stable
at least tsetupbefore the clock edge
at least until thold after the clock edge
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Dynamic Discipline
The delay between registers has a minimum and
maximum dela , de endent on the dela s of the circuit
elementsCLKCLK
CL
R1 R2
Q1 D2
a
CLK
Tc
Q1
D2
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(b)
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Setup Time Constraint
The setup time constraint depends on the maximum delay from
register R1 through the combinational logic.
The input to register R2 must be stable at least tsetupbefore the clock
edge.
CLQ1 D2
R1 R2 T
CLK
Tc
D2
tpcq
tpd
tsetup
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Setup Time Constraint
The setup time constraint depends on the maximum delay from
register R1 through the combinational logic.
The input to register R2 must be stable at least tsetupbefore the clock
edge.
CLQ1 D2
R1 R2 T t + t + t
CLK
Tc
tpd
D2
tpcq
tpd
tsetup
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Setup Time Constraint
The setup time constraint depends on the maximum delay from
register R1 through the combinational logic.
The input to register R2 must be stable at least tsetupbefore the clock
edge.
CLQ1 D2
R1 R2 T t + t + t
CLK
Tc
tpdTc (tpcq + tsetup)
D2
tpcq
tpd
tsetup
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Hold Time Constraint
The hold time constraint depends on the minimum delay from
register R1 through the combinational logic.
The input to register R2 must be stable for at least thold after the clock
edge.CLKCLK
t CLK
Q1
D2tccq
tcd
thold
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Hold Time Constraint
The hold time constraint depends on the minimum delay from
register R1 through the combinational logic.
The input to register R2 must be stable for at least thold after the clock
edge.CLKCLK
t < t + t
CLQ1 D2
R1 R2
tcd> thold - tccqCLK
Q1
D2tccq
tcd
thold
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Timing Analysis
CLK CLK
A
Timing Characteristics
tccq = 30 ps
B
'
tpcq = 50 ps
tsetup = 60 ps
DY' Y
thold = ps
t = 35 sate
tcd= 25 psperg
tpd=
t =
Setup time constraint:
Tc
Hold time constraint:
tccq + tpd> thold ?
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c = c =
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Timing Analysis
CLK CLK
A
Timing Characteristics
tccq = 30 ps
B
'
tpcq = 50 ps
tsetup = 60 ps
DY' Y
thold = ps
t = 35 sate
tcd= 25 psperg
tpd= 3 x 35 ps = 105 ps
t = 25 s
Setup time constraint:
Tc (50 + 105 + 60) ps = 215 ps
Hold time constraint:
tccq + tpd> thold ?
Copyright 2007 Elsevier
c = c = . z 30 + 25 ps > 70 ps ? No!
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Fixing Hold Time Violation
Timing Characteristics
tccq = 30 psCLK CLK
Add buffers to the short paths:
tpcq = 50 ps
tsetup = 60 psB
thold = ps
t = 35 sate
C
D
X'
Y'
X
Y
tcd= 25 psperg
tpd=
t =
Setup time constraint:
Tc
Hold time constraint:
tccq + tpd> thold ?
Copyright 2007 Elsevier
c =
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Fixing Hold Time Violation
Timing Characteristics
tccq = 30 psCLK CLK
Add buffers to the short paths:
tpcq = 50 ps
tsetup = 60 psB
thold = ps
t = 35 sate
C
D
X'
Y'
X
Y
tcd= 25 psperg
tpd= 3 x 35 ps = 105 ps
t = 2 x 25 s = 50 s
Setup time constraint:
Tc (50 + 105 + 60) ps = 215 ps
Hold time constraint:
tccq + tpd> thold ?
Copyright 2007 Elsevier
c = c = . z 30 + 50 ps > 70 ps ? Yes!