MOHAMMAD HASAN

PARTICULARS

Work Address: Full Professor, Electronics Engineering Department, Aligarh Muslim University, Aligarh (202002), India. 0091-571-2721148 (Off), 0091-571-2721148 (Fax) Email:hasan786@ieee.org , mohdhasan097@gmail.com Website:http://www.amu.ac.in/dshowfacultydata2.jsp?did=32&eid=3211 Citations:http://scholar.google.co.in/citations?hl=en&user=85mkRuMAAAAJ&view_op=list_works&is_public_preview=1

Home Address:

Wadi-e-Ismail, Dhorra, Aligarh(202002), U.P., India. 0091-571-2721141(R), 0091-9897790043 (Mob)

EDUCATION

Ph.D.: “Low Power Techniques and Architectures for MC-CDMA Receiver”, University of Edinburgh, United Kingdom(Feb., 2004)

M.Tech. (MS): Integrated Electronics and Circuits, Indian Institute of Technology, Delhi (UK Times Higher Education Ranking-5), India, Third

Position (8.21/10 or 3.26/4) (1992)

B.Sc. Engineering: (BS or Bachelor)

Electronics Engineering, Aligarh Muslim University, Aligarh, (UK Times Higher Education Ranking - 9), India, First Position (9.833/10 or 3.93/4) (1990)

AWARDS / HONOURS / ACHIEVEMENTS

Awarded the highly competitive Commonwealth Fellowship to pursue research on “Energy

harvesting of body based sensor nodes”at the University of Southampton, UK in 2013.

Awarded the prestigious “Royal Academy of Engineering, UK’s research exchange scheme for India and China” to pursue postdoctoral research on “Low power techniques and architectures for FPGA” at the University of Edinburgh, UK, in 2008

Awarded the prestigious Commonwealth Scholarship for pursuing Ph.D. from the University of Edinburgh, U.K. in 2000

Published 143 refereed Journal and Conference papers with 985 citations (h-index=17, i10=35)

Filed three patents on magnetic RAM design using Magnetic Tunnel Junction and CMOS and one on SRAM cell

Supervised four PhD students and currently supervising four more students.

“Paper of the Year 2008 Award” by the Editors of the high impact factor ETRI Journal for the paper entitled “High performance low power FFT cores”.

Best paper award for the paper entitled “Subthreshold CMOS full adder for ultra low power operation”, in International Conference on Systemics, Cybernetics and Informatics (ICSCI-2008), January 02-05, 2008, India.

Best paper award for the paper entitled “High frequency low voltage 32nm node CMOS rectifier for energy harvesting in implanted devices” in 12th IEEE International Conference, INDICON-2015 organised by Jamia Milia Islamia from 17-20 December, 2015.

Presented an invited paper on “Subthreshold Deep Submicron Performance Investigation of CMOS and DTCMOS Biasing Schemes for Reconfigurable Computing”, in a prestigious IEEE International Symposium on Circuits and Systems, ISCAS Conference, Taipei Taiwan, 24-27 May, 2009.

Acted as reviewers for IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, IET proceedings on Circuits, Devices and Systems, Electronic letters, Micro & Nano letters, IEEE International Symposium on Circuits and Systems, International Conference on VLSI Design.

Supervised a B.Tech. (BS) project entitled “Performance analysis of Analog Building blocks in technologies beyond silicon” that was awarded “Innovative Student Project Award” by the Indian National Academy of Engineering in 2009.

Awarded Senior Membership of the IEEE.

Awarded six research and development projects by the Indian funding agencies.

Jointly responsible for the award of a grant of $0.325 million for a Department proposal on “Embedded System Design” from the Department of Science and Technology, Government of India in 2007.

Jointly responsible for the award of a grant of $0.3 million for a Departmental research project on Networked Multimedia from the University Grants Commission, Government of India in 2005.

Jointly responsible for the award of a grant of $0.33 million for a Departmental research project on “Multimedia for next generation networks” from the University Grants Commission, Government of India in 2015.

M.Tech. (M.S.) Dissertation was recommended for the IEEE award by IIT, Delhi, India in 1991.

Awarded Gold medal for standing first in B.Sc. Engineering (BS) (Electronics) in 1990.

Supervised the Department’s car racing team that won the runner up prize in an All India “Smart Car Race India-2010” competition jointly organised by Freescale Semiconductors, Centre for Electronic Design and Technology and Indian Institute of Science in Bangalore, India on the 29 th of September, 2010.

KEYNOTE ADDRESSES & INVITED LECTURES IN CONFERENCES

Delivered a half day tutorial on “Circuit and System Design Issues in an IOT sensor node” in 21st International Symposium on VLSI Design and Test (VDAT2017) organised by IIT Roorkee on 29th June, 2017.

Delivering a Keynote on “Spintronics” in a National Seminar on Electronic Devices, Systems and Information Security (SEEDS-2017) which is being organised by the Department of Electronics and Instrumentation Technology, University of Kashmir on 24th of March, 2017.

Delivered a tutorial on “Design of energy and area efficient circuits using Spin devices in combination with CMOS” on 8.1.2017 in “30th International Conference on VLSI Design and 16th International Conference on Embedded Systems” in Hyderabad, India.

Delivered an invited talk on “Low Power DSP Architectures” on 9.9.2016 in a workshop on "High-performance VLSI Architectures for Digital Signal Processing Applications: Design and Implementations” organized by Jaypee University of Science and Technology, Guna from 9-11 September, 2016.

Delivered a Keynote on “Spintronics: Beyond Charge based Electronics” in a Second International Conference on Computing, Communication, Control and Automation (ICCUBEA-2016), technically sponsored by IEEE, Pune Section on 13thAug. 2016, at Pimpri Chinchwad College of Engineering, (PCCOE), Pune, India.

Delivered a tutorial on “Ultra Low Power VLSI Design” on 24th May, 2016 in an International Symposium on VLSI Design and Test (VDAT-2016) organised by IIT Guwahati, India.

Delivered invited talks on “Digital System Design using Verilog HDL” and “Spintronics” on 12th and 13th December, 2015 in a 10 day long faculty development programme organised by NIT, Patna.

Delivered an invited talk on “Spintronics” in a training program on “Advanced Digital Devices and Systems” organised by Malaviya National Institute of Technology, Jaipur, India on 29th March, 2015.

Delivered an invited talk on “Digital System Design with HDL” in a National Seminar on Recent Trends in VLSI and Embedded Systems(RTVES-2014) in Jaipur National University, Jaipur, India on October 15, 2014.

Delivered an invited talk on “Carbon Nanotube Based Electronics: Future Perspective” in Electrical Engineering Department, King Saud University, Riyadh, Saudi Arabia, on 23rd May, 2012.

Delivered a keynote address on “Research Opportunities in VLSI Design & Nanoelectronics” in a National Level Seminar on “Research Opportunities in VLSI Design (ROVD)” organised by PDVPP College of Engineering, Ahmednagar, India, on the 10thApril, 2012.

Delivered a keynote address on “Overview of Nanoelectronics” in a National Conference on Emerging Trends in Electrical, Instrumentation and Communication Engineering (ETEIC-2012) organised by Anand Engineering College, Mathura, India on the 6th of April, 2012.

Delivered a keynote address on “Carbon Nanotube based Electronics” in an International Conference on Computational Intelligence Applications” organised by Sandip Institute of Technology and Research Centre, Nashik, India, on the 4th of March, 2010.

Delivered an invited talk on “VLSI Architectures for Multimedia” in a 2nd Workshop on Multimedia & Applications (MMA-2012) organised by University Women’s Polytechnic, AMU, Aligarh on the 5th of February, 2012.

Delivered an invited lecture on “DSP Processor Architecture” in a workshop on Digital Signal Processing organised by Anand Engineering College, Mathura, India in March, 2010.

Delivered invited lectures on “High Level Design” and “Leakage Power” in a workshop on VLSI Design organised by Hindustan Engineering College, Mathura, India in March, 2008.

Delivered an invited talk on “Low Power VLSI Design” in a National Conference on Nano, Bio and Information Technology Integration in Sanjay Institute of Engineering, Mathura, India in March, 2007.

EMPLOYMENT HISTORY

Teaching Experience 1992-2004: Assistant/Associate Professor, Department of Electronics Engineering, A.M.U.,

Aligarh, India

2005-2008: Full Professor in the same Department

2008-2009: Visiting Researcher in the School of Engineering, University of Edinburgh, United Kingdom.

2009 onwards: Full Professor in the Dept. of Electronics Engineering, A.M.U., Aligarh, India. (UK Times Higher Education Ranking - 9)

Courses Taught:

2004-present: Advanced Analog IC Design, Low Power VLSI Design, Digital System Design using HDL at the MS level (10 students), Digital System Design, Digital Integrated Circuits, Electronic Devices, Digital Signal Processing at the BS level (60 students).

2000-2003: Demonstrated in Verilog HDL Gateway lab in the School of Engineering a Electronics, University of Edinburgh, United Kingdom.

1992-2000: Analog IC Design to MS students, VLSI Design, Microelectronics, Principles of Electronics Engineering, Microprocessors & Microcontrollers and Logic and Digital Circuits to BS students.

Research Experience

Research and Modernisation Projects Completed:

1. Low Power Architectures for DSP algorithms: This project involved exploration of low power architectures for popular DSP algorithms like FIR filtering, FFT processing, Discrete Wavelet Transform by reducing the Switched Capacitance. This project was sanctioned by the All India Council for Technical Education (AICTE) in 2006 under their Research Promotion Scheme (RPS). The total amount sanctioned was $25000.

2. Modernisation and Removal of Obsolescence of the IC Design Lab: This project involved modernisation of the IC Design lab. It was sanctioned by the AICTE under their MODROB scheme in April, 2006. The total amount sanctioned was $25000.

3. Low Power FPGA Architectures: This project explored low power architectures for FPGA. It minimised leakage and dynamic power and maximised speed of the FPGA by using either CMOS or by exploring emerging technologies like Carbon nanotubes. This prestigious project was funded by the Royal Academy of Engineering, UK under their research exchange scheme with India and China. The total amount sanctioned was $36000 in 2009. This project has resulted in a few journal papers and numerous conference papers on the effectiveness of carbon nanotube based transistors and bundles of carbon nanotubes as interconnects in realisation of next generation Integrated Circuits and Systems.

4. Creation of an ASIC Design Facility: This project with a total grant of $25000 was awarded for creating an ASIC and FPGA design infrastructure in the Department. This project was sanctioned under upgradation of our College to IIT level scheme of the Government.

Projects ongoing:

1. Embedded System Design: This departmental project involves exploration of novel signal, image, video and networking algorithms and their implementation in FPGA and Application specific integrated circuits. The total amount sanctioned to the department by the Department of Science and Technology, Government of India is $0.325 million.

2. Networked Multimedia: This departmental project under DRS-II scheme of the UGC investigates novel algorithms for multimedia and wireless communications and their implementation in FPGA and application specific integrated circuits. The total amount sanctioned under the scheme by the University Grants Commission is around $0.3 million.

Patents Filed:

1. “Power Efficient Magnetic Content Addressable Memory (MCAM)”, Application number:811/DEL/2015; Publication Date: 03.07.2015

2. “Robust Binary Content Addressable Memory using Magnetic Tunnel Junction (MTJ) for Wide Arrays (BMCAM)”, Application number: 1406/DEL/2015; Publication Date: 03.07.2015

3. “A novel circuit of variation immune magnetic tunnel junction based Ternary CAM”,Application

number: 2732/DEL/2015; Publication Date: 25.09.2015

4. Robust and Low Power Static Random Access Memory Cell (RLP-SRAM) Published in the Indian

Patent Office Journal Issue No. 17, pp. 14992, 2016.

Ph.D. theses supervised:

1. Low power techniques and architectures for Field programmable Gate Arrays: FPGA has become very popular in non-portable applications due to its high power consumption. There is a pressing need for reducing the power consumed by the FPGA so that it can also be used in portable battery operated systems. This research work explored different techniques and architectures for reducing the dynamic and leakage power in the configurable logic blocks, routing switches and configuration RAM of Field programmable gate arrays. Moreover, Carbon nanotube based transistors (CNFET) and bundles of carbon nanotube based interconnects were also investigated to realize low power and high speed FPGA architectures.

2. Power and Variability Aware Design of Circuits and Systems: The parameters like threshold voltage and dimensions of the transistor vary significantly even for adjacent transistors in deep submicron beyond 32nm technology node. This is caused by random dopant fluctuations, line edge roughness due to sub-wavelength lithography, temperature and supply voltage gradients on a chip. This project investigated techniques at the circuit level to create low power robust circuits and systems which are immune to these device variations. Circuits in upcoming technologies like CNFET and FinFET were also explored for their robustness and power.

3. Robust Subthreshold Circuits for Ultra Low Power Moderate Throughput Applications:

Subthreshold circuits operate at a supply voltage lower than the threshold voltage, thereby, consuming ultra low power consumption. These circuits are ideal for ultra low power low throughput applications mostly in Biomedical domain. This project explored the design of subthreshold circuits and interconnects for FPGA at the nanoscale. The whole idea was to extend the FPGA operation in the subthreshold domain leading to the arrival of a subthreshold FPGA.

4. Optimal Design and Performance evaluation of devices beyond bulk CMOS: This thesis primarily deals with the optimization of bulk CMOS and beyond bulk CMOS devices like Tunnel FET and Carbon nanotube FET in the realization of both analog and digital building blocks for ultra low power applications.

Ph.D. theses under supervision:

1. Ultra Low Power Design using Tunnel FETs: This project primarily deals with the minimization of power consumption in key building blocks like SRAM cells, adders and basic gates under subthreshold conditions by exploiting better subthreshold characteristics of optimized Tunnel FETs.

2. Design of neuromorphic circuits/systems using CMOS and beyond CMOS devices: There is a need to explore the implementation of neuromorphic circuits/systems in hybrid technology (CMOS and memristor or Tunnel FET and memristor) and then to compare their performance with their only CMOS counterparts. Subthreshold performance of Tunnel FET is much better than MOSFET and these devices will be ideal for ultra low power neuromorphic circuits. Moreover, memristors will also be explored to further improve the performance of these circuits.

3. Design and Optimization of CNFET based Biomedical Circuits: It is important to reduce the power consumption of Biomedical Circuits so as to extend their battery life. Carbon nanotube based FET (CNFET) exhibits higher speed compared to bulk CMOS due to ballistic transport of carriers through the nanotubes in CNFET. This higher speed of CNFET can be effectively traded for lower power consumption. Hence, this thesis investigates the low power potential of CNFET in the design of ultra low power biomedical circuits.

4. Design of Spintronic Devices based Electronic Circuits: It is difficult to maintain scaling of CMOS

technology at the nanoscale due to process variations, leakage power consumption and other short channel effects. It is, therefore, important to explore technologies beyond CMOS like Spintronics. Spintronic devices like magnetic tunnel junctions, domain wall switches and MRAM are non-volatile and can be used with CMOS to improve its performance at the nanoscale or to create all spin systems with better characteristics than CMOS. This project investigates the hybrid design of novel CMOS circuits with spintronic devices for achieving better performance in termsof power and delay both in logic and interconnect domains.

Some of M.Tech. (MS) dissertations supervised:

2015: Design of neuromorphic circuits using CMOS and memristors

2015: Robust design of ultra low power SRAM cell in devices beyond CMOS

2014: Design of magnetic tunnel junction based circuits

2013: Design of a low power neural amplifier for the Brain Machine Interface.

2013: Design and Performance investigation of Energy Harvesting Circuits.

2012: Design and optimization of MRAM cell and its performance comparison with CMOS based SRAM

2012: Design and optimization of a SiC based VJFET.

2010: Design of variability aware adder circuit

2010: Design of a carbon nanotube FET based current conveyor

2008: Low Power Building Blocks for Network on Chip.

2007: VLSI architecture of an FIR filter.

2007: Verilog modelling and FPGA based implementation of a Fuzzy logic controller

2006: Energy efficient architecture of a 2D-Discrete Wavelet transform.

2000: VHDL modeling and FPGA based implementation of a pipelined FFT processor.

1999: VHDL modeling and FPGA based implementation of an 8085 microprocessor.

1998: Design and FPGA based implementation of a Telephone Set Tester.

1996: Design and FPGA based implementation of a Synchronisation Signal generator for Television.

1996: A CAD Tool for Automatic Design of a fixed topology CMOS Opamp

1994: A Layout Editor and Design Rule Checker for CMOS Technology.

Some of the projects supervised at the BS Level:

Verilog modelling and FPGA based implementation of zero memory SPECK algorithm

VLSI architecture of a Set partitioning in Hierarchical trees (SPIHT) algorithm.

VHDL modelling and FPGA based implementation of an 8-bit microprocessor.

Verilog modelling and FPGA based implementation of a Discrete Wavelet Transform.

Verilog modelling and FPGA based implementation of advanced encryption standard.

VHDL modelling and FPGA based implementation of an FIR filter.

VHDL modelling and FPGA based implementation of a memory efficient Huffman decoder.

Development of microprocessor based Robot arm controller.

A CAD tool for automatic generation of optimised layout for a PLA based combinational and sequential system.

A CAD tool for automatic design of fixed topology OPAMPs.

Design of circuits using Carbon nanotube based FET

Design of a Smart Car based on Freescale Design kits

Ph.D. Thesis:

Low power Techniques and Architectures for Multicarrier Wireless Receivers:

Power consumption is a critical issue in portable wireless communication. Multi-carrier code division multiple access (MC-CDMA) has a significant potential to be included as a standard in the next generation of mobile communication. This thesis investigates new low power architectures for a MC-CDMA receiver. The FFT processor is one of the major power consuming blocks in multi-carrier systems based on Orthogonal frequency division multiplexing (OFDM), like MC-CDMA, wireless LANs etc. Two low power schemes are presented for reducing the power consumption in FFT processors namely order based processing and coefficient memory reduction. The order based processing scheme is based on a novel concept of using either the normal or two's complement form for only the real part of the coefficients selectively to minimise the Hamming distance between successive coefficients fed to the multipliers. Low power single butterfly radix-2 FFT processor and radix-4 ordered pipelined FFT processor architectures based on the novel order based processing scheme are also proposed. The ordered low power radix-4 FFT processor is combined with the combiner to realise a low power MC-CDMA receiver.The coefficient memory reduction scheme exploits the relationship among the coefficient values to reduce the coefficient memory size from N/2 locations to ((N/8)+1) locations for an N-point FFT, thereby saving both area and power for long FFTs.

The power consumption in a MC-CDMA receiver can be further reduced by introducing the concept of dynamically altering the complexity of the receiver in real time as per the changing channel parameters such as the signal to noise ratio(SNR) instead of using a receiver designed for the worst case channel conditions.

M.Tech. (M.S.) Dissertation

Development of intelligent auxiliary CAMAC Crate Controller: CAMAC stands for computer automated measurement and control system. This dissertation involves the design and implementation of a microprocessor based controller for CAMAC. The indigenous controller is much more economical than the costly imported controller used by the Nuclear Science Centre. This project was recommended for the IEEE award by the Indian Institute of Technology, Delhi in 1991.

M.Tech. (MS)(Minor Project)

Design of a low power CMOS OPAMP: This project involves the design of a low power CMOS operational amplifier.

The main highlight of this design is the operation of differential amplifier transistors under subthreshold conditions to achieve low power consumption.

PROFESSIONAL ACTIVITIES

Senior Member of IEEE

Head of the Department since 12 Oct., 2015

Chaired a session on “Nanotechnology and its applications-II” on 20th December, 2015 in the 12th IEEE International Conference, INDICON 2015, at Jamia Millia Islamia, New Delhi.

Key member of Departmental accreditation, curriculum development, research and purchase committees

Chaired a session in an International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT-2013) organised by the Department of Electronics Engineering, AMU, Aligarh, India, on the 23th of Nov. 2013.

Acted as a Co-ordinator of a workshop on “Recent Trends in Embedded System Design” organisedby the Electronics Engineering Department, AMU, Aligarh, India on the 2nd of March, 2013.

Acted as a Co-Coordinator of an intensive summer course on “VLSI Design &Nanoelectronics” organised by the Electronics Engineering Department, AMU, Aligarh, India, from 25-30 June, 2012.

Acted as a Co-Coordinator of an intensive course on “Recent Trends in VLSI Design and Embedded Systems” organised by the Electronics Engineering Department, AMU, Aligarh, India from 24th January to 4th of February, 2012.

Chaired a session in an International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT-2011) organised by the Department of Electronics Engineering, AMU, Aligarh, India, on the 18th of Dec. 2011.

Acted as a Coordinator of a workshop on “Recent Trends in VLSI Design and Technology” organised by the Electronics Engineering Department, AMU, Aligarh, India, on the 20th of March, 2010.

Chaired a session in the Conference on “Modern Trends in Electronics and Communications Systems-2008” organised by the Department of Electronics Engineering, AMU, Aligarh, India.

RESEARCH INTERESTS

Ultra Low Power Circuit/System Design in Deep Submicron (Battery-less Electronics)

Analog IC Design of Biomedical circuits

Low Power Architectures for Signal Processing and Multimedia and their FPGA/ASIC realization

Robust Circuit Design (Memory and Datapath) in Deep submicron

Design of neuromorphic circuits/memories using beyond CMOS devices like memristors and spin

devices (spintronics)

TEACHING INTERESTS

Digital Integrated Circuits

Analog IC Design

Nanoelectronics

Digital System Design

Low Power VLSI Design

Embedded System Design

Digital Signal Processing

VLSI Architectures for Signal Processing & Multimedia

RF Microelectronics

COLLABORATIONS

Collaborating with Central Electronics Research Institute (CEERI, Pilani, India) and ST-Microelectronics Noida, India in the area of “Ultra Low Power Analog IC Design for Body based sensor node” and “Embedded Systems” respectively.

Collaborating with the Electronics Group of King Saud University, Saudi Arabia in the area of “Design of Analog Circuits using Carbon nanotube based FET”.

Collaborated with the School of Engineering, University of Edinburgh, UK on “Low Power FPGA Architectures” till 2010

Submitted a joint proposal on “Smart Low Power Sensor Networks to Optimize Building Energy Usage” in collaboration with Glasgow Caledonian university to the British Council under its Global Innovation Initiative programme

PUBLICATIONS

Book Chapters

1. High Speed Cache Design Using Multi-Diameter CNFET at 32nm Technology in Springer Information and Communication Technologies. Series:Communications in Computer and Information Science. Volume101, Part 1, Pages: 215-222. Aminul Islam, Mohd. Hasan. Venu V Das, R. Vijay Kumar et al. (Eds). ISBN-10 3-642-15765-3 Springer Berlin Heidelberg New York. Springer-Verlag Berlin Heidelberg 2010, printed in Germany. (Held as International Conference on Advances in Information and Communication Technologies -ICT-2010 held in Kochi, Kerala, India in September 2010, DOI: 10.1007/978-3-642-15766-0_31, DOI Bookmark: www.springerlink.com/index/H8U0467P094564W3.pdf

2. Amir Khan, Mohd.Hasan, Anwar Sadat and Shamsuz Z.Usmani, “6H-SiC Based Power VJFET and Its Temperature Dependence”,Quality, Reliability, Security and Robustness in HeterogeneousNetworks. Lecture Notes of the Institute for Computer Sciences, SocialInformatics and Telecommunications Engineering, 2013, ISSN 1867-8211,ISBN978-3-642-37949-9, Volume 115, DOI 10.1007/978-3-642-37949-9_28,pp 325-332, Publisher: Springer Berlin Heidelberg.

Selected Journal Publications

1. Sayeed Ahmad, Naushad Alam, Mohd. Hasan, “Pseudo Differential Multi-Cell Upset Immune Robust SRAM Cell for Ultra-Low Power Applications”, International Journal of Electronics and Communications (Elsevier), Vol. 83, pp. 366-375, 2018.

2. S. Ahmad, M. K. Gupta, N. Alam, M. Hasan, “Low Leakage Single Bitline 9T (SB9T) Static Random Access Memory”, ISI indexed Elsevier’s Microelectronics Journal, Vol. 62, pages 1-11, 2017

3. Mohit K. Gupta and M. Hasan, “Self-Terminated Write Assist Technique for STT-RAM”, ISI indexed IEEE Transactions on Magnetics, Vol. 52 Issue 8, August, 2016.

4. Sayeed Ahmad, M.K. Gupta, Naushad Alam, M. Hasan, “Single-Ended Schmitt-Trigger-Based Robust Low-Power

SRAM Cell”, ISI indexed IEEE Transactions on VLSI Systems, vol. 24, no. 8, 2634-2642, August, 2016.

5. Yogendra Upadhyaya, Mohit K. Gupta, M. Hasan, S. Maheshwari, “High Density Magnetic Flash ADC using Domain Wall Motion and Pre-Charge Sense Amplifiers”, ISI indexed IEEE Transactions on Magnetic, Vol. 52, Issue 6, June 2016.

6. Mohit Kumar Gupta and M. Hasan, “A Low Power Robust Easily Cascaded PentaMTJ based Combinational and

Sequential Circuits” ISI indexed IEEE Transactions on VLSI Systems, Vol. 24, Issue 1, pp. 218-222, Jan. 2016.

7. Mohit K. Gupta and M. Hasan, “Robust High speed Ternary Magnetic Content Addressable Memory” ISI indexed

IEEE Transactions on Electron Devices, Vol. 62, Issue 4, pp. 1163-1169, April, 2015.

8. Mohit Kumar Gupta and M. Hasan, “Design of high speed energy efficient masking error immune PentaMTJ based TCAM” ISI indexed IEEE Transactions on Magnetics, Vol. 51, No. 2, 3400209, Feb., 2015.

9. S.D. Pable, Mohd. Hasan, S.A. Abbasi and A.R.M. Alamoud, “Interconnect optimization to enhance the performance

of subthreshold circuits”, ISI indexed Elsevier’s Microelectronics Journal, Vol. (44), Issue (5), pp. 454-461,

March 2013.

10. Ale Imran, Aminul Islam, M. Hasan and S.A. Abbasi, “Optimized Design of a 32nm CNFET based Low Power Ultra Wide band CCII”, ISI indexed IEEE Transactions on Nanotechnology, Vol. 11, Issue 6, pp. 1100-1109, Nov.,

2012.

11. Aminul Islam and Mohd. Hasan, “Leakage Characterization of 10T SRAM Cell”, ISI indexed IEEE Transactions on Electron Devices, Vol. 59, Issue 3, pp. 631-638, March, 2012.

12. S.D. Pable and Mohd. Hasan, “Interconnect Design for Subthreshold Circuits”, ISI indexed IEEE Transactions on

Nanotechnology, Vol. 11, Issue 3, pp. 633-639, May, 2012.

13. Aminul Islam and Mohd. Hasan, “A Technique to Mitigate Impact of Process Voltage and Temperature Variations on Design Metrics of SRAM Cell” ISI indexed Elsevier’s Microelectronics Reliability, Vol. 52, no. 2, pp. 405-411,

February, 2012.

14. Aminul Islam and Mohd. Hasan, "Variability Aware Low Leakage Reliable SRAM Cell Design Technique, "ISI indexed Elsevier’s Microelectronics Reliability, Vol. 52, Issue 6, pp. 1247-1252, June, 2012.

15. Aminul Islam and Mohd. Hasan, “Variation Resilient Subthreshold SRAM Cell Design Technique," ISI indexed International Journal of Electronics, Vol. 99, No. 9, pp. 1223-1237, Sept. 2012.

16. S.D. Pable and Mohd. Hasan, “Ultra-low-power signaling challenges for subthreshold global interconnects”, ISI

indexed Elsevier’s Integration, The VLSI Journal, Vol. 45, Issue 2, pp. 186-196, March, 2012.

17. S.D. Pable and Mohd. Hasan, “A Novel Robust FPGA Routing Switch Box Design for Ultra Low Power Applications”,

ISI indexed International Journal of Electronics, Vol. 99, Issue 1, pp. 15-27, Sept. 2011, DOI: 10.1080/00207217.

2011.609977.

18. S.D. Pable and Mohd. Hasan, “Robustness comparison of emerging devices for portable applications,” Journal of Nanomaterials, Volume 2012 (2012), Article ID 242459, 8 pages DOI:10.1155/2012/242459.

19. S.D. Pable and Mohd. Hasan, “High Speed Interconnect through Device Optimization for Subthreshold FPGA”, ISI indexed Elseviers’s Microelectronics Journal, Vol. 42, No. 3, pp. 545-552, Jan., 2011.

20. Aminul Islam, Mohd. Hasan, “Power optimized variation aware dual-threshold SRAM cell design technique”, Nanotechnology, Science and Applications Journal Vol. 2011:4, pp. 25-33, Feb., 2011, DOI:

10.2147/NSA.S15719.

21. Aminul Islam, Mohd. Hasan, “Dual-Diameter Variation –Immune CNFET-based 7T SRAM Cell”, Nanosciences and Nanotechnologies: An International Journal (NIJ), Vol. 1, No. 1, pp. 1-14, Feb. 2011.

22. Aminul Islam, Mohd. Hasan, “Single-Ended 6T SRAM Cell to Improve Dynamic Power Dissipation By Decreasing Activity Factor,” Mediterranean Journal of Electronics and Communications, Vol. 7, No. 1, pp. 172-181, 2011.

23. A.K. Kureshi and M. Hasan, "DTMOS based low power FPGA building blocks", Mediterranean Journal of

Electronics and Communication, Vol. 6, No. 4, Oct. 2010, ISSN:1744-2400.

24. Fahad Ali Usmani and M. Hasan, " Carbon Nanotube Field Effect Transistors for High Performance Analog Applications: An Optimum Design Approach”, ISI indexed Elseviers’s Microelectronics Journal, Vol. 41, Number

7, pp. 395-402, July, 2010.

25. A.K. Kureshi and M. Hasan, "Analysis of CNT Bundle and its Comparison with Copper Interconnect for CMOS and CNFET Drivers," Journal of Nanomaterials, Vol. 2009, Article ID 486979, 6 pages, 2009.

26. Kureshi A. K. and Mohd. Hasan, “DTMOS Based Low Power High Speed Interconnects for FPGA", Journal of Computers (Academy Publisher Finland), vol.4, No.10, pp.921-926, Oct. 2009.

27. A.K. Kureshi and M. Hasan, “Comparison of performance of Carbon nanotube FET and bulk CMOS based 6T SRAM cell in deep submicron”, ISI indexed Elsevier’s Microelectronics Journal, Vol. 40, No. 6, pp. 979-982, June 2009.

28. W. Han, A.T. Erdogan, T. Arslan and M. Hasan, ‘High performance low power FFT cores’, ISI indexed ETRI

Journal, vol.30, no.3, pp. 451-460, June 2008. (Paper of the year 2008 award)

29. A.K. Kureshi and M. Hasan, “Leakage Power Estimation and Minimisation in Configurable logic block of FPGA”, International Journal of Systemics, Cybernetics and Informatics (IJSCI), pp.49-53, January, 2008.

30. Hemendra Varshney, Sambhav Jain and Mohd. Hasan, ‘Energy efficient novel architectures for the lifting based Discrete Wavelet Transform’, ISI indexed IET Proceedings on Image Processing, Vol. 1, Issue 3, P305-310

September, 2007.

31. Syed Mohsin Reza Zaidi and M. Hasan, “An Energy Efficient Programmable Hardware Implementation of the Secure Hash 384 and 512 Algorithms” ISI indexed IETE Journal of Research, Vol. 53, No. 5, September-October,

2007. 32. M. Hasan, T. Arslan and J.S. Thompson, ‘Low power adaptive MC-CDMA transceiver architectures’, ISI indexed ETRI

Journal, vol. 29, no. 1, pp. 79-88, Feb. 2007.

33. M. Hasan, T. Arslan and J.S. Thompson, ‘A low power architecture for a MC-CDMA receiver’, ISI indexed IETE Journal of Research, vol. 51 no. 6, pp. 459-464, November-December 2005.

34. M. Hasan and T. Arslan, ‘Implementation of low power FFT processor cores using a novel order based processing scheme’, IEE proceedings on Circuits, Devices and Systems, vol. 150, no. 3, pp. 149-154, June 2003.

35. A.T. Erdogan, M. Hasan and T.Arslan, ‘Algorithmic low power FIR cores’, ISI indexed IEE proceedings on Circuits,

Devices and Systems, vol. 150, no. 3, pp. 155-160, June 2003.

36. M. Hasan, T. Arslan and John Thompson, ‘A Novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications’, ISI indexed IEEE Transactions on Consumer Electronics, vol. 49, no. 1,

pp.128-134, February, 2003.

37. M. Hasan and T. Arslan, ‘Scheme for reducing size of the coefficient memory in FFT processor’, ISI indexed Electronic letters, Vol. 38, no. 4, pp.163-164, February, 2002.

38. M. Hasan and T. Arslan, ‘Coefficient memory addressing scheme for high performance FFT processors", ISI indexed Electronic Letters, Vol. 37, no. 22, pp.1322-1324, October, 2001.

39. M. Hasan, M. S. Imam, R. Sharma and S. A. Abbasi, ‘A Novel Design and FPGA Based Implementation of a Complex Synchronization Signal Generator for Television’, ISI indexed IEEE Transactions on Consumer Electronics, Vol. 43, no.4, p1143-1151, 1997.

Journals under review

Mohit K. Gupta and M. Hasan, “High Speed Resilient Non-volatile Magnetic Content Addressable Memory,” submitted to IEEE Transactions on VLSI Systems

Ajmal Kafeel and M. Hasan, “Design of ultra low power high performance Tunnel FET based current conveyor” submitted to Elsevier’s Microelectronics Journal.

Other Journal Publications

40. M. Ajmal Kafeel, M. Zulqarnain, M. Hasan,“Reconfigurable Memristor and CNFET based four quadrant multiplier for

low power applications”, International Journal of Computer Applications 173(6):14-20, September, 2017.

41. M. Ajmal Kafeel, M. Hasan,“Performance Evaluation of CNFET based Single-Ended 6T SRAM cell” SCI Indexed

Wulfenia Journal Volume 20, Issue 7, July 2013, pages 364-383.

42. S.D. Pable and Mohd. Hasan, “Performance analysis of DG FinFET for ultralow-power subthreshold applications”, Journal of Electronic Design Technology, Vol. 2, No. 2, 2011.

43. Aminul Islam, Mohd. Hasan, “Variability Analysis of 6T and 7T SRAM Cell in Sub-45nm Technology”, IIUM

Engineering Journal, Vol. 12, No. 1, pp. 13-30, May, 2011.

44. Aminul Islam, M. W. Akram, Mohd. Hasan, “Energy Efficient and Process Tolerant Full Adder in Technologies Beyond

CMOS,” International Journal on Recent Trends in Engineering and Technology, Vol. 05, no. 01, pp. 1–7, March

2011.

45. S.D. Pable and Mohd. Hasan, “Performance analysis of interconnects driver for ultra low power application,” International Journal on Electrical and Power Engineering, Vol. 2, No.1, pp. 30-35, Feb. 2011.

46. Aminul Islam, Mohd. Hasan, “Process Variation and Radiation-Immune Single Ended 6T SRAM Cell”, ACEEE

International Journal on Signal & Image Processing - IJSIP, Vol. 1, No. 3, pp. 37-45, Dec. 2010.

47. Aminul Islam, Mohd. Hasan, “Design and Analysis of Power and Variability Aware Digital Summing Circuit,” ACEEE

International Journal of Recent Trends in Engineering and Technology, Vol. 4, No. 1, pp. 29-37, Nov. 2010.

48. A.K. Kureshi and M. Hasan, "Analysis of CNT Bundle and its Comparison with Copper for FPGA Interconnect,"

International Journal of Applied Science, Engineering and Technology, pp. 178-183, 2009.

49. M.A. Saeed, M. Hasan and Nesar Ahmad, “High speed optimized reconfigurable architecture of Fuzzy logic controller”, IETECH Journal of Information Systems, Vol. 2, No. 4, pp. 172-175, 2008.

50. Mohammad Hasan and Shuja A. Abbasi, ‘An Optimized Automatic PLA Based Combinational & Finite State Machine Layout Generator’, Journal of Engineering, Vol. 15, no. 2, pp 115–119, 2005.

51. Mohammad Hasan, V. Mohan and Shuja A. Abbasi, ‘A Novel User Friendly PC Based IC Layout Editor and Design Rule Checker’, Journal of Engineering, Vol 14, no. 1, pp. 7–12, 2004.

52. Prabhat Arora, Manish Singhal, M. Hasan, S.A. Abbasi, ‘VHDL modeling and FPGA based implementation of a memory efficient Huffman decoder’, IETE Technical review, vol. 21, No. 6, pp-371-377, November-December 2004

53. Usmani Afzal Ahmad and Mohd. Hasan, “Microprogrammed Control Based System Design and FPGA based Implementation of a Telephone Dial Tester”, IETE Journal of Education, Vol. 41, Nos. 3 & 4, July-December 2000,

pp. 93-100.

54. M. Hasan, S. A. Abbasi, K. N. Khan and S. A. Faraz, ‘A Novel Design and FPGA Based Implementation of a Byte Wise CRC Code Generator Chip using VHDL’, IETE (Institution of Electronics and Telecommunication Engineers) Technical Review, Vol. 15, no.6, p487 - 490, 1998.

Selected Conference Publications

55. C1. Sayeed Ahmad, Naushad Alam, Mohd. Hasan, “Soft Error Hardened Symmetric SRAM Cell with High Read Stability”,

International Conference on Multimedia, Signal Processing And Communication Technologies, IMPACT-17, November

2017.

56. L Y. Upadhyaya, M. Hasan, S. Maheshwari, “Low Power and High Density Magnetic Flash Analog to Digital Converter

using spintronic devices and CMOS”, International Conference on Multimedia, Signal Processing And Communication Technologies, IMPACT-17, November 2017.

57. S Sayeed Ahmad, Naushad Alam, Mohd. Hasan, “Low Leakage Write Enhanced Robust 11T SRAM cell with Fully Half-

Select Free Operation”, International Conference on Trends in Electronics and Informatics (ICEI), SCAD College of Engg. & Tech. Tirunelveli, May 2017.

58. Sa Sayeed Ahmad, Naushad Alam, Mohd. Hasan, “A comparative study of read stability and write ability of bit-interleaving

SRAM cells under parameter fluctuations”, 3rd International Conference on Emerging Electronics, IIT Bombay, December 2016.

59. Bel Belal Iqbal, Naushad Alam, Mohd. Hasan, “Investigation of BTI Effects on Sense Amplifiers”, International Conference

on Multimedia, Signal Processing And Communication Technologies, IMPACT-17, November 2017.

60. M. Ajmal Kafeel, M. Hasan, M. S. Alam et.al “Performance Evaluation of CNFET Based Operational Amplifier at

Technology node Beyond 45-nm” IEEE INDICON 2013 Conference, Mumbai, December 13-15, 2013, pp. 1-5.

61. Khan, A.; Imran, A.; Hasan, M., "A 2.25kV, 6.1mΩ-cm2 4H-SiC normally-off VJFET", Power, Control and Embedded

Systems (ICPCES), 2012 2nd International Conference on, pp.1-4, 17-19Dec., ISBN 978-1-4673-1047-5, DOI

10.1109/ICPCES.2012.6508119

62. Aminul Islam and Mohd. Hasan, “FinFET based variation resilient 8T SRAM cell”, IEEE Annual India Conference

(INDICON), pp. 121–125, Kochi, Kerala, India, December 7-9, 2012. ISBN: 978-1-4673-2270-6, DOI: 10.1109/INDCON.2012.6420600.

63. Aminul Islam, Mohd. Ajmal Kafeel, Tanzeem Iqbal, and Mohd. Hasan, “Variability Analysis of MTJ Based Circuit” IEEE

International Conference on Computer and Communication Technology, Allahabad, India, pp. 57-62, 23-25 November, 2012.

64. Aminul Islam, Mohd. Ajmal Kafeel, S. D. Pable, and Mohd. Hasan, “Variation immune near threshold SRAM cell,” in IEEE International Conference on recent advances in Information Technology (RAIT), ISM, Dhanbad, India, Vol. II, pp.

286-291, 15-17 March, 2012.

65. Aminul Islam, S.D. Pable, M. Hasan, “Performance and Variability improvement of subthreshold SRAM cell using DTMOS and cell content body bias techniques”, Proceedings of Second International Conference on Meta Computing, 15-16 Dec. 2011, Goa, India pp. 29-32.

66. Aminul Islam, Mohd. Ajmal Kafeel, Ale Imran and Mohd. Hasan, “Low Active Power High-Speed Cache Design”, IEEE

International Symposium on Electronic System Design (ISED-2011), pp. 254-259, December 19-21, Kochi, India

67. S.D. Pable, Mohd. Ajmal Kafeel and Mohd. Hasan, “Performance analysis of ultralow-power mixed CNT interconnects for scaled technology”, IEEE International Symposium on Electronic System Design (ISED-2011), pp. 285-289,

December 19-21, Kochi, India

68. Aminul Islam, Ale Imran and Mohd. Hasan, “Robust Subthreshold Full Adder Design Technique”, IEEE International

Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT-2011), pp. 99-102, December 17-19, 2011, AMU, Aligarh, India.

69. Aminul Islam, Ale Imran and Mohd. Hasan, “Optimized Design of Hybrid CMOS and CNFET 32 nm Dual-X Current Conveyor”, IEEE International Conference on Multimedia, Signal Processing and Communication Technologies

(IMPACT-2011), pp. 76-79, December17-19, 2011, AMU, Aligarh, India.

70. S. D. Pable, Ale Imran and Mohd. Hasan, “Performance investiagtion of DG-FinFET for subthreshold applications”, IEEE

International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT), pp. 16-19, Dec. 17-19, 2011, AMU, Aligarh, India.

71. S. D. Pable, A.K. Kureshi, and Mohd. Hasan, “Performance analysis of SRAM cell for ultralow power Applications,”IEEE

International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT), pp. 12-15, Dec., 17-19 , 2011, AMU, Aligarh, India.

72. Aminul Islam, M. W. Akram, Mohd. Hasan,” Variability Immune FinFET-Based Full Adder Design in Subthreshold Region,” in Proceedings of IEEE International Conference on Devices and Communications–11 (ICDeCom–11), BIT, Mesra, Ranchi, Jharkhand, India, February 24-25, 2011, pp. 1-5. DOI: 10.1109/ICDECOM.2011.5738477 .

73. Aminul Islam, Farhan Aziz, Mohd. Hasan, M.W. Akram, “Analysis of Impact of Device Parameters Fluctuation on SRAM

Cell for Process-Tolerant Cache Architecture,” in Proceedings of International Conference on Advances in Electrical & Electronics Engineering (ICAEEE-2011), Moradabad, Uttar Pradesh, India, 25-26 Feb., 2011.

74. S.D. Pable and Mohd. Hasan, "Performance analysis of FPGA interconnects fabric for ultra-low power

applications,”International Conference on Communication, Computing and security, NIT Rourkela, pp. 210-214, 12-14 Feb. 2011.(ACM 978-1-4503-0464-1/11/02)

75. S.D. Pable and Mohd. Hasan, "Performance optimization of CNFET for ultra-low power reconfigurable architecture" International Conference on Communication, Computing and security, NIT Rourkela, pp. 215-220, 12-14 Feb. 2011. (ACM 978-1-4503-0464-1/11/03)

76. Aminul Islam, M. W. Akram, Mohd. Hasan, “Energy Efficient and Process Tolerant Full Adder Design in Near Threshold Region using FinFET”, IEEE International Symposium on Electronic System Design (ISED-2010), ISBN: 978-1-4244-8979-4, 2010, pp. 56-60, DOI:10.1109/ISED.2010.19, Bhubaneswar, India, 20-22 Dec., 2010.

77. Aminul Islam and Mohd. Hasan, “Power and Variability Aware Design of SRAM using Carbon Nanotube Field Effect

Transistor” IEEE Annual India Conference INDICON -2010, ISBN: 978-1-4244-9072-1, DOI:10.1109/INDCON.2010.

5712597, pp. 1-4, Jadavpur University, Kolkata, India, 17-19 Dec. 2010.

78. S.D. Pable, M.W. Akram, Mohd. Hasan and Aminul Islam, “Performance Optimization of LUT of Subthreshold FPGA in Deep Submicron”, IEEE International Conference on Computer and Communication Technology (ICCCT-2010), pp.

64-69, 17-19 Sept., 2010, Allahabad, India.

79. Ale Imran and Mohd. Hasan, “A Comparative study of CMOS & CNFET based Current Conveyor at 32nm technology node”, IEEE International Conference on Computer and Communication Technology (ICCCT-2010), 17-19 Sept.,

2010, Allahabad, DOI: 10.1109/ICCCT.2010.5640522, 2010, pp. 276-281, India.

80. Ale Imran and Mohd. Hasan, “High Performance Optimised CNFET based Current Conveyor at 32nm technology node”, IEEE International Conference on Computer and Communication Technology (ICCCT-2010), 17-19 Sept.,

2010, Allahabad, DOI: 10.1109/ICCCT.2010.5640522, 2010, pp.324-329, India.

81. Aminul Islam, M.W. Akram, S.D. Pable, Mohd. Hasan, “Statistical Data Stability and Leakage Evaluation of SRAM Cell in Sub-45nm Technology”,IEEE International Conference on Advances in Communication, Network, and Computing–

CNC 2010, pp. 149-152, 4-5 Oct, 2010.

82. Aminul Islam, M.W. Akram, S.D. Pable, Mohd. Hasan, “Design and Analysis of Robust Dual Threshold CMOS Full Adder Circuit in 32nm Technology”, IEEE International Conference on Advances in Recent Technologies in

Communication & Computing, ARTCom 2010, pp. 418-420, 16-17 Oct, 2010.

83. Ale Imran, M.W. Akram, Mohd. Hasan, “Design of High frequency low power CMOS Dual-Output Current Conveyor at 32nm technology node” ACEEE International Conference on Advances in Recent Technologies in Communication &

Computing, ARTCom 2010, DOI: 10.1109/ARTCom.2010.85, 2010, pp.200-203,16-17 Oct, 2010.

84. Mohd. Hasan, “Carbon nanotube based Electronics”, International Conference on Computational Intelligence

Applications”, ICCIA-2010, Sandip Institute of Technology and Research Centre, Nashik, India 3-5 March, 2010.

85. Aminul Islam, M. W. Akram, Mohd. Hasan, ”Variation Resilient Subthreshold Full Adder Cell,” in Proceedings of National Conference on Information and Communication Technology–2010 (NCICT–10), Nagpur, Maharashtra, India, pp. 27-32, December 23-25, 2010.

86. Aminul Islam, M. W. Akram, S. D. Pable, Mohd. Hasan, “Robust 1-Bit Full Adder Design using FinFET at 32 nm Technology Node,” International Conference on Communication, Computers and Devices (ICCCD-2010), IIT, Kharagpur, India, 10-12 Dec., 2010.

87. S. D. Pable, M. W. Akram, Mohd. Hasan, Aminul Islam, “Variability aware interconnect driver design for subthreshold

circuits,” International Conference on Communication, Computers and Devices (ICCCD-2010), IIT, Kharagpur, INDIA 10-12 Dec., 2010.

88. Aminul Islam, M.W. Akram, S.D.Pable, and Mohd. Hasan, “Design of a Novel CNTFET-Based 1-Bit Full Adder in Deep Submicron Technology”, 14th VLSI Design andTest Symposium, VDAT 2010, July 7-9, 2010.

89. S.D. Pable, Aminul Islam, M.W. Akram, and Mohd. Hasan, “Design of Robust Subthreshold Circuits”, 14th VLSI Design and Test Symposium, VDAT2010, July 7-9, 2010.

90. Aminul Islam and Mohd. Hasan, “Design and Development of clocked transmission gate cross-coupled adiabatic (CTGCA) circuit”,IEEE International Conference on Advances in Computing, Control and Communication

Technologies, pp. 650-653, 28-29 December, 2009, Trivandrum, India..

91. F.A. Usmani and Mohd. Hasan,”Design and parametric analysis of CMOS and CNFET based OPAMP at 32nm technology node for optimum performance”, 4thIEEE Argentine School of Micro-Nanoelectronics, Technology and

Applications, pp. 87-92, Sept., 2009, Argentina.

92. F.A. Usmani and Mohd. Hasan, “Novel Hybrid CMOS and CNFET Analog Inverting Amplifier Design for Area, Power and Performance Optimization” 2nd International Workshop on Electron Devices and Semiconductor Technology, Indian Institute of Technology, Bombay, India, 1-2 June, 2009.

93. A.K. Kureshi, Naushad Alam, Mohd. Hasan and Tughrul Arslan “Subthreshold Deep Submicron Performance Investigation of CMOS and DTCMOS Biasing Schemes for Reconfigurable Computing”, IEEE International Symposium on Circuits and Systems, ISCAS 2009 Conference, Taipei Taiwan, pp. 2545-2548. (Invited paper)

94. A.K. Kureshi, Mohd. Hasan and Tughrul Arslan, “Leakage Reduction in FPGA Routing multiplexers”, IEEE

International Symposium on Circuits and Systems, ISCAS 2009 Conference, Taipei Taiwan, pp. 1129-1132, 24-27 May, 2009.

95. A.K. Kureshi, Naushad Alam, Mohd. Hasan and Tughrul Arslan “Carbon Nanotube Interconnect for Low-Power High-Speed Applications”, IEEE International Symposium on Circuits and Systems, ISCAS 2009 Conference, Taipei

Taiwan, pp. 2273-2276, 24-27 May, 2009.

96. A.K. Kureshi, Mohd. Hasan and Tughrul Arslan, “Energy Efficient High Speed CNFET Based Interconnect Drivers for FPGAs “, IEEE sponsored International Conference on Multimedia, Signal Processing and Communication

Technologies, A.M.U., Aligarh., India, March, 2009, pp. 48-52.

97. N. Alam, A.K. Kureshi, Mohd. Hasan and Tughrul Arslan “Analysis of Carbon Nanotube Interconnects and their Comparison with Cu Interconnects”, IEEE sponsored International Conference on Multimedia, Signal processing and

Communication Technologies, A.M.U., Aligarh., India, March, 2009, pp. 125-128.

98. N. Alam, A.K. Kureshi, Mohd. Hasan and Tughrul Arslan “Performance comparison and variability analysis of CNT bundles and copper interconnect”, IEEE sponsored International Conference on Multimedia, Signal processing and

Communication Technologies, A.M.U., Aligarh., India, March, 2009, pp. 170-173.

99. Fahad Ali Usmani, Shadab Mallick and Mohd. Hasan, “Performance Analysis of Bulk CMOS, Strained Si and CNFET based Operational Amplifiers in VDSM Technology” IEEE International Advance Computing Conference organised by

Thapar University, Patiala, India, March, 2009, pp. 2567-2570.

100 Fahad Ali Usmani, Shadab Mallick and Mohd. Hasan, “Optimal Design of CNFET based Inverting Amplifier for Best Performance at 32nm Technology Node”, IEEE International Advance Computing Conference organised by Thapar

University, Patiala, India, March, 2009, pp. 1568-1572.

101 Naushad Alam and Mohd. Hasan, “Mixed Bundle of CNTs for Interconnect Applications”, International Conference on VLSI and Communication (ICVCOM-2009) organized by SaintGits College of Engineering, Kottayam, Kerala, April, 2009, India.

102 A.K. Kadir and Mohd. Hasan, ‘Low leakage high speed carbon-nanotube field effect transistor based Look up Table’, Proceedings IEEE International Conference on Emerging Trends in Engineering and Technology (ICETET-08), 16-18

July, 2008, Nagpur, India.

103 A.K. Kureshi and Mohd. Hasan, “Leakage estimation and minimisation of CLB in FPGA” IEEE International Conference

on Computer and Communication Engineering”, pp. 270-274, 13-15 May, 2008 Kuala Lampur, Malaysia.

104 Tarun Agarwal, Anurag Sawhney, A.K. Kureshi and Mohd. Hasan, “Subthreshold operation of MCML gates” IEEE

International Conference on Computer and Communication Engineering”, pp. 284-287,13-15 May, 2008, Kuala Lampur, Malaysia.

105 Naushad Alam, A.K. Kadir and Mohd. Hasan, “Analysis and Comparison of Subthreshold 1-Bit Full Adder Cells” IEEE International Conference and Colloquim SPIT-IEEE Colloquim, Vol. 2, pp. 127–131, February, 4-5, 2008, Mumbai,

India.

106 A.K. Kureshi, Naushad Alam and Mohd. Hasan, “A novel low power high speed FPGA routing interconnects”, IEEE International Conference and Colloquim SPIT-IEEE Colloquim, Vol. 2, pp. 145 – 149, February, 4-5, 2008, Mumbai,

India.

107 N. Alam, A.K. Kureshi and M. Hasan, “Subthreshold CMOS full adder for ultra low power operation”, International Conference on Systemics, Cybernetics and Informatics (ICSCI-2008), pp. 48-51, January 02-05, 2008, India. (Best Paper Award)

108 Naushad Alam, A.K. Kadir and Mohd. Hasan, “Dynamic Threshold PMOS Switch for Power Gating”, Proceedings of VLSI Design and Test Symposium, pp. 173-180, 23-26 July, 2008 in Bangalore, India.

109 Tarun Agarwal, Anaurag Sawhney, A.K. Kureshi and Mohd. Hasan, “Performance Comparison of CNFET and CMOS Based Full Adders at The 32nm Technology Node”, Proceedings of VLSI Design and Test Symposium, pp. 49-57, 23-26 July, 2008 in Bangalore, India.

110 A.K. Kureshi, Naushad Alam and Mohd. Hasan, “Performance Comparison of CNFET and CMOS based 8T SRAM Cell in Deep Submicron”, Proceedings of VLSI Design and Test Symposium, pp. 441-442, 23-26 July, 2008 in Bangalore, India.

111 A. K. Kureshi and M. Hasan, “Leakage Power and Delay Optimization of FPGA Interconnects” Proceedings of International Conference on Signal Processing, Communications and Networking (ICSCN 2008), pp. 568-572, Jan 4-6, 2008, Chennai, India.

112 M. Asim Saeed, M. Hasan and Nesar Ahmad, “High speed optimized reconfigurable architecture of a Fuzzy logic controller” IET-UK International Conference on Information and Communication Technology in Electrical Sciences”, vol. II, pp. 558-561, 20-22, December 2007.

113 W. Han, A. T. Erdogan, T. Arslan, and M. Hasan, ‘Low Power Commutator for Pipelined FFT Processors’, IEEE

International Symposium on Circuits and Systems, Vol. 5. pp: 5274 – 5277, 23-26 May, 2005.

114 W. Han, A. T. Erdogan, T. Arslan, and M. Hasan, ‘Multiplier-Less based Parallel-Pipelined FFT Architectures for Wireless Communication Applications’, IEEE International Conference on Acoustics, Speech, and Signal Processing

(ICASSP 2005) held in Philadelphia, USA, pp. V/45-V/48, 19-23 March, 2005.

115 W. Han, A. T. Erdogan, T. Arslan, and M. Hasan, ‘The Development of High Performance FFT IP Cores through Hybrid Low Power Algorithmic Methodology’, IEEE Asia and South Pacific Design Automation Conference 2005 (ASP-

DAC 2005) held in Shanghai, China, pp. 549-552, January 18-21, 2005.

116 W. Han, T. Arslan, A.T. Erdogan and M. Hasan , ‘A novel low power pipelined FFT based on sub-expression sharing for wireless LAN applications’, IEEE Workshop on Signal and Image processing in Austin, Texas, USA, pp. 83-88,

Oct., 2004

117 M. Hasan, T. Arslan and J. Thompson, ‘A Delay spread based low power reconfigurable FFT processor architecture for wireless receivers’, IEEE International Symposium on SoC in Finland, pp. 135-138, November, 2003.

118 M. Hasan, T. Arslan and J. Thompson, ‘A Novel Low Power Pipelined Architecture for a MC-CDMA receiver’, 3rd IEEE

International Symposium on Image and Signal processing and Analysis, Part-II, pp. 1048-1053, September, 2003.

119 M. Hasan and T. Arslan, ‘A Triple Port RAM Based Low Power Commutator Architecture for a Pipelined FFT Processor’, IEEE International Symposium on Circuits and Systems, vol. 5, pp. 353-356, May, 2003.

120 M. Hasan and T. Arslan, ‘A coefficient memory addressing scheme for VLSI implementation of FFT processors’, IEEE

International Symposium on Circuits and Systems, Volume: 4, pp. 850-853, May, 2002.

121 M. Hasan and T. Arslan, ‘FFT coefficient memory reduction technique for OFDM Applications’, IEEE International

Conference on Acoustics, Speech and Signal processing, Volume: 1, pp. 1085-1088, May 2002.

122 A.T. Erdogan, M. Hasan and T. Arslan, ‘A low power FIR filtering core’, IEEE International Conference on ASIC/SoC ,

pp. 271-275, September, 2001.

123 V. Mohan, M. Hasan and S. A. Abbasi, ‘A New Interactive CAD Tool for IC Layout Design and Verification’, 6th IEEE

International Symposium on IC Technology, Systems and Applications (ISIC-95), Singapore, pp. 87-91, Sept., 1995.

Other Conference Publications

124 Ankit Bhatia, Ashraf Ali, M. Hasan, “Leakage and Performance comparison of Dual Vth 6T LCSRM and Dual Vth 8T SRAM”, National Conference on Emerging Technology Trends (NCETT-2010), organised by VNS Institute of Technology, Bhopal, India, pp. 393-395, 19-20 March, 2010.

125 W. Ahmad, Amir Khan and M. Hasan, “A novel Design of CMOS XOR gate with improved robustness to process variation at 32nm Technology node”, National Conference on Recent Trends in Communication Technologies and VLSI Design (RTCTV-2010), organised by Vardhman College of Engineering, Hyderabad, 2-3 June, 2010.

126 A.K. Kureshi and Mohd. Hasan , “Leakage Analysis of CNFET Based Basic Digital Building Blocks”, published in the proceedings of International Conference on Emerging Techniques in Electronics, Computing, Embedded Systems and VLSI, 20-21, March, 2008, PVDDP College of Engineering, Ahmednagar, India.

127 Mohd. Hasan, “Low power design issues in CMOS” in International Conference on Emerging Techniques in Electronics, Computing, Embedded Systems and VLSI, 20-21, March, 2008, PVDDP College of Engineering, Ahmednagar, India.

128 Fahad Ali Usmani and Mohd. Hasan, “Operation of Advanced CNFET based Inverting Amplifier at 32nm Technology Node”, in INDIACom-2009 organised by BhartiVidyapeeth’s Institute of Computer Applications and Management, 26-27th February, 2009, pp. 569-571.

129 A.K. Kureshi and Mohd. Hasan, “Interconnect Performance Comparison of FPGAs at 32nm Technology”, National Systems Conference, (NSC-08), organized by Electrical Engineering Department, IIT, Roorkee, India, Dec., 2008, pp. 766-769.

130 A. K. Kureshi, N. Alam, and M. Hasan, “Low power Field programmable Interconnects”, International Conference on Systemics, Cybernetics and Informatics, pp. 52-55, January 02-05, 2008, India.

131 Naushad Alam and Mohd. Hasan, “Comparison of Hybrid-CMOS Adders with static CMOS Adder in deep submicron Technology” Proceedings of Conference on Modern Trends in Electronics and Computer Systems (MTECS-2008), pp. 255–258, 8-9 March, 2008, Aligarh, India.

132 A.K. Kureshi, Naushad Alam and Mohd. Hasan, “Subthreshold Field programmable Gate Arrays”, Proceedings of Conference on Modern Trends in Electronics and Computer Systems (MTECS-2008), pp. 244–247, 8-9 March, 2008, Aligarh, India.

133 Mohd. Tauheed Khan and Mohd. Hasan , “A novel architecture of the 2D wavelet transform”, National Conference on Control and Instrumentation, National Institute of Technology, Kurukshetra, India, pp. 12-19, 29-30 Dec. 2007.

134 A. K. Kureshi and M. Hasan, “Static leakage power estimation and reduction techniques for SRAM cell” National Systems Conference (NSC-2007), pp. 34-35, 15-16 December, 2007, Manipal University, India.

135 M. Hasan, “Low Power design Issues in deep submicron” in National Conference on Nano, Bio and Information Technology Integration, March 23-25, 2007, Mathura, India.

136 Kureshi Kadir and Mohd. Hasan, "A study of different circuit level techniques for low leakage SRAM cell", Proceedings of National Conference on Advanced Computing & Computer Network NCACCN-2007, pp. 438-441, March 9-10, 2007.

137 M. Hasan and S.A. Abbasi, ‘Programmable Logic Based Implementation of Digital Systems’, Proc. National Symposium on Design of Electronics Systems (NSDES) – 97, Aligarh, India, pp.279 – 284, 1997.

138 M. Hasan and S. A. Abbasi, ‘Introduction to High Level Design of Digital Systems’, Proc. NSDES – 97, Aligarh, India. pp. 297–302, 1997.

139 M. Hasan and S. A. Abbasi, ‘A CAD Tool for an Automatic Design of a Fixed Topology CMOS Op-Amp’, Proc. National Systems Conference (NSC)-96, Thiruvanthapuram, India, pp. 92-96, December, 1996.

140 M. Hasan and S. A. Abbasi, ‘Development of intelligent auxiliary CAMAC crate controller’, Proc. NSC-96, Thiruvanthapuram, India, pp. 87-91, December, 1996.

141 G. Sharma, M. Hasan and S. A. Abbasi, ‘A CAD tool for an automatic optimised PLA based combinational and Finite state machine layout generator’ Proc., NSC-95, Coimbatore, India, pp. 77-81, 1995.

142 A. S. Khan and M. Hasan, ‘A CAD tool for two dimensional placement problem in VLSI Design’, Proc. of Seminar on Electronic Systems and Applications, Roorkee, India, pp. 257-260, 1994.

143 D. Solanki and M. Hasan, ‘A new multilingual editor implemented only for Hindi language’, Proceedings of the Eighteenth National Systems Conference (NSC-94), Agra, India, pp. 87-91, January , 1994.

(Mohd. Hasan)