module fpga
TRANSCRIPT
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FPGA Module
• Presented By
– Natalija Jovanovic ([email protected]) – Raj Sood ([email protected])
– David Gilon ([email protected])
• 6.371 Final Project• Dec 11th, 2002
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PROJECT OVERVIEW
Field Programmable Gate Arrays (FPGA)chips allow hardware developers to simulate circuit
designs without having to fabricate and test circuit logic. Typically, many FPGAs would beused together to simulate a circuit or component of a circuit.
FPGA chips contain 3 major sets of components:
1. Combination Logic Block (CLB) - contains the basic programmable logic functions and
general purpose registers
2. Inter-Cell Switch Matrix (SM) - contains circuitry which allows cells to communicate withone another or with external pins
3. Input/Output pin-management circuitry - allows the chip to communicate with the host
system
Present in all three components is an embedded set of control/configuration circuitry whichonce programmed, will determine which logic functions will be implemented in eachCombination Logic Block (CLB) as well as how the switch matrix and input/output pins will beconfigured.
The goal of this project was to design a basic CLB and Switch Matrix cell design which couldbe used to build out a full FPGA network of cells and interconnects. More specifically, wefocused on component 1 [CLB] and 2 [Switch Matrix].
Our design creates an FPGA module that is composed of 4 CLB and 4 Switch Matrix Units,
which together could be used to simulate simple gate functions, 2,3 or 4 bit counters, andsimple adders.
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Switch
Matrix
1
Figure 1. FPGA 4 Cell Module Data Pathways
Switch
Matrix
3
Combination
Logic Block 1
Combination
Logic Block 3
Switch
Matrix
2
Switch
Matrix4
Combination
Logic Block 2
Combination
Logic Block 4
out3
out3
8 inputs 3
8 inputs 3
9 bits
9 bits
9 bits
9 bits
out3
out3
9
9
99
carry bit
out
carry bit
out
carry bit
out
carry bit
out
carry bit
in
carry bit
in
carry bit
in
carry bit
in
9
9
8 inputs
8 inputs
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Figure 1a. FPGA Module Layout
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Figure 3. Combination Logic Block (CLB) With Input/Output Selectors
8 bit Input Lines
CLB Logic Core
8 bit config 8 bit config
8 bit config 8 bit config
3 bit Output
Lines
Carry Out
Carry In
Scan Out
Scan In
CLB Scan Out
DI
F0
F1
F2
F3
CLK_EN
CLB Scan In
CLB Carry Out
DO
Q
X
CLB Carry In
Program Enable CLK
Program Enable CLK Preset
PresetNOTE: 3 + 8 = 9 (two lines are In/Out)
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Figure 3a. CLB Capsule Layout
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Figure 4. Combination Logic Block (CLB) Core Function
F Block
4 Bit
Programmable
Logic Function
( built in 16 bit
Configuration
Array )
FD Block
1 Bit
Configurable
Register
8 bit Configuration Array
D Q
DI
F0
F1
F2
F3
CLK
CEn_input
DO
Q
X
C_OUT
C_IN Presetprog_en scan_in
scan_out
scan_in
4 ctrl bits
0
1
0
1
0
1
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Figure 4b. CLB Core Logic
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Figure 4c. 8 Bit Scan Chain Configuration Array (A shift register)
b0
b1
b2
scan_in program_enable CLK
scan_out
f3
b3
b4
b5
b6
b7
NOTE:
Several instances of this configuration
and dual scan chain arrays were
developed for specialty layout needs
o0
o1
o2
o3
o4
o5
o6
o7
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Figure 4d. Scan Chain Sample Layout (Horizontal Version)
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Figure 5. F Block (programmable 4 bit combination logic function)
1,1,1,1
0,1,1,1
0,1,1,0
0,1,0,1
0,1,0,00,0,1,1
0,0,1,0
0,0,0,1
0,0,0,0
1,1,1,0
1,1,0,1
1,1,0,01,0,1,1
1,0,1,0
1,0,0,1
1,0,0,0
b0
b1
b2
b15
12 more
bit state
units
Decoder
scan_in program_enable CLK
X
scan_out
f3
f2
f1
f0
NOTE:
Each decoder row has a
corresponding bit value
which is set at configuration
time (when program_enable
is set high).
For example, when f0..f3 areall 0, the tri state inverter
infront of b0 register will be
enabled, allowing the bit
value of the b0 register to
transmit to output X
T
he Program CLK logic
allows clocking of the
registers only when
program_enable is high
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Figure 5a. F Block Programmable Combination Logic
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Figure 6. FD Block (programmable 1 bit register)
0
1
0
1
0 1
0
1
0
1
NORNOR
NOR
DQ
CLK
CEn_pgm
CEn_input
TCLKHI TCLKLO
VSS
Preset_Value
Preset
“Master” “Slave”
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Figure 6a. FD Block Programmable Register
Pass Through LatchGoverned by CE_Input11
Latch on Clock Low10
Latch on Clock High01
Flip Flop00
SettingTCLKLTCLKH
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Figure 7a. Switch Matrix Overview
See figure 7c for allowed pin connections
8 bit Configuration Array
8 bit Configuration Array
8 b i t C o n f i g u r a t
i o n A r r a y
8 b i t C o n f i g u r a t i o n A r r a y
8 b i t C o n f i g u r a t i o n A r r a y
8 b i t C o n f i g u r a t i o n A r r a y
8 b i t C onf i g u
r a t i onA r r a y
8 b i t C onf i g ur a t i onA r r a y
wires
Top 0..8
wires
Right
0..8
wires
Bottom
0..8
wiresLeft
0..8
0 8
0
8
0 8
0
8
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Figure 7b. Reach Out and Touch Someone… (64 allowed conn)
1 0 0 0 1 0 0 1
8 bit Configuration Array
wires
Top 0..8
wires
Right
0..8
wires
Bottom
0..8
wiresLeft
0..8
0 8
0
8
0 8
0
8
Disabled
TransmissionGate
Enabled
Transmission
Gate
Transmission
Gate Layout
E
E
A B
A B
E
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Figure 7d. Switch Matrix Layout
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So what Can We Do With It?
• Given the data path specifications and
CLB functionality, various simple hardwareemulators can be configured.
• The following are simplified examples ofhow to route a 2 bit counter which drives
off the clock, and of a compound logic
function of 8 inputs.
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Bottom 0..8 Bottom 9..17
Top 0..8 Top 9..17
SM1
Figure 8. FPGA_Module Data Path Pin Outs
SM3
CLB1 CLB3
SM2 SM4
CLB2 CLB4
3
3
out3
out3
carry_out_top 0
Carry_in_bottom 0
Right 0..8
Right 9..17
Left 0..8
Left 9..17
carry_out_top 1
Carry_in_bottom 1
CLB_IN_Left 3..5
CLB_IN_Left 0..2
CLB_OUT
Right 0..2
CLB_OUT
Right 3..5
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SM 1
CLB 1 Programing
F0..3 X
xx01 0
xx10 1
xx01 1
xx00 0
CLB 2 Programing
F0..3 X
xxx1 0
xxx0 1
SM 2 SM 4
SM 3
F0
F0
Counter Bit 0
F1
Counter Bit 1
q
q
Figure 9. Example 1: A 2 Bit Counter State Machine
Specifications:
- 2 full CLB cells (Both F and FD blocks)
- 4 Switch nodes (could also use 2)
- CLB register configured as positive edgetriggered dRegister on the clock
- NOTE: NOT ALL SIGNALS SHOWN
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SM 1
CLB 1
AND(F0,F1,F2,F3)
CLB 2
XOR(J0,J1,J2,J3)
SM 2 SM 4
SM 3
F0
Q2
Q1
Figure 10. Example 2: A Compound Logic Function
F1
F2
F3
J0
J1
J2
J3
CLB 3
OR(Q1, Q2)Q2
X
Specifications:
X = OR( AND(f0,f1,f2,f3 ) , XOR(j0,j1,j2,j3))
- 3 CLB cell function blocks
- 4 Switch nodes
- NOTE: NOT ALL SIGNALS SHOWN
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The Team Effort
Our design effort partitioned along the following architectural components:
• CLB Programmable Register (Raj)
• CLB Interconnect (Raj)• CLB Programmable Function Block (David)
• CLB Capsule Layout & Testing (Raj/David)
• Scan Chain Configuration Cells (David)
• Switch Matrix Architecture, Layout & Testing (Natalija) – Transmission Gate
– Specialized Scan Chain Layouts For Space Maximization
– 95% manual wiring
• Fpga_Module Final Layout (David)
• Programming Documentation (David)
• Application Demo for 2 bit counter & compound function (Raj (Natalija&David helped)
• Presentation (David)
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The Results
• All Major Subcomponents s.a. CLB Capsule, SwitchMatric, Scan Chaining and their subcomponents were
successfully logic tested and laid out, and timing tested• The final FPGA_MODULE was wired and laid out.
Verification was not completed. This was not due to a
lack of effort on all counts.
• Layout Extracted Timing Tests For – Switch Matrix Min Propagation Between Pins:
• .6 nano seconds
– CLB Capsule Clock Period Boundary…:
• Around 40 nano seconds (~25Mhz)
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Lesson’s Learned
• Programming an FPGA module by hand is a pain in the back yard. How didthose corporate guys do it?
• Last minute changes to signal routing specifications must sometimes be
made to make life easier • Switch Matrix spec and I/O Wiring to CLB is key for flexibility in
programming
• Using standard cell designs help in layout and testing
• LOGIC TEST EVERYTHING !!!!
• SHOULD HAVE DONE SYSTEM WIDE TESTING EARLIER
• IS THERE ENOUGH TIME TO TEST EVERYTHING ??
• SHOULD HAVE ESTABLISHED BETTER MODULE PROGRAMMING
CONVENTIONS FOR EASIER DEBUGGING OF SCAN BITS
• THIS WAS A REALLY INTERESTING AND FUN PROJECT!!!
• WE ALL LEARNED A LOT!!!
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Programming 1: Overview
I. Overview
The FPGA Module can be programmed with a serial bit sequence when the pen_insignal is high. the s_in terminal is the interface to the module scan chain whichtravels through all the subcomponents of the module. The programmingdocumentation is also written in the FPGA.SLS file.
Each bit in the chain should be timed with a rising clock edge and must be held forthe full duration of the clock period. or 2 period counts in the Simeye simulation.
For example, to program a high, low, high bit sequence into a component, do thefollowing:
set sys_clk = h*1 l*1 h*1 l*1 h*1 l*1set pen_in = h*6set s_in = h*2 l*2 h*2
1 0 1SomeConventions: XXX = unused bit space
OUT1[1..0] = A 2 bit sequence with least significant bit to the right
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II CLB Core Programming:
A CLB Core requires 24 bits of programming. of those, on 22 bits are actively used.
CLB_CORE_BITs = fb15 fb14 fb13 fb12 fb10 fb9 fb8 fb7 fb6 fb5 fb4 fb3 fb2 fb1 fb0 XXX XXX mux3 mux2 pres tll tlh cen
fb15..0: Combination logic evaluation bits corresponding to rows 15 through 0
mux2: 0=CO, 1=DI
mux3: 0=DO, 1=Xcen: 0=input driven, 1= data pass through to flip flop
pres: Values loaded in register when Preset signal is high
tll(tclock low) 0 = flip flop l = latch on low 0 = latch on high 1 = CEN Input Latch on high
tlh(tclock high): 0 0 1 1
Example: set s_in = (h*2 l*2)*8 l*2 l*2 h*2 h*2 l*2 l*2 l*2 h*2
fb15..0 XXX XXX m3 m2 pres tll tlh cen
this example can be used with a feedback loop to create a 1 bit counter.
Programming 2: CLB CORE
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Programming 3: CLB Capsule• III. CLB Capsule Programming
In addition to the CLB Core bits, 32 more bits are required for capturing the input mux and output mux settings.These settings allow values to come in from the switch matrix and back out to the switch matrix.
The Input wires are generally from the Bottom of the corresponding Switch Matrix (by number), meaning thatCLB2 receives inputs from the bottom of Switch Matrix 2 wires B1..B8, corresponding to inputs 0..7.
CLB_CAPSULE_BITS = CLB_CORE_BITS +
XXX XXX XXX XXX XXX OUT2 OUT2[1..0] OUT1 OUT1[1..0] OUT0 OUT0[1..0] CEn_Sel F1_Sel F2_Sel F3_Sel F4_Sel DI_SelEn Sel En Sel En Sec [2..0] [2..0] [2..0] [2..0] [2..0] [2..0]
Input Mux Values: For deciding which wires from the routing matrix map onto the CEN, F[0..3] and DI signals which are in the CLB_Core
Sel[2..0] => IN[0..7]----------------------------------------------------------000 0001 1010 2
011 3100 4101 5110 6111 7
Output Mux Values: For deciding which values go to routing wires on OUT[0..2], which correspond to wires values B[0..2] in the corresponding switch matrices
NOTE: Output muxes also must be enabled to drive data
Sel[1..0] => Data[0..2]
----------------------------------------------------------00 DO01 Q10 X11 -unused
Example:
set s_in = (h*2 l*2)*8 l*2 l*2 h*2 h*2 l*2 l*2 l*2 h*2 (l*2)*5 h*2 h*2 l*2 h*2 l*2 h*2 h*2 l*2 l*2 h*4 l*2 h*2 l*4 l*2 h*4 l*2 h*2 l*2 l*4 h*2 l*6fb15..0 b7 b6 m3 m2 pres tll tlh cen Xtr_St OUT OUT2 OUT OUT1 OUT OUT0 CEn_Sel F0_Sel F1_Sel F2_Sel[2..0] F3_Sel DI_Sel
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Programming 4: Switch Matrix• IV . Switch Matrix Programing
The switch matrix has 81 connection terminals and 64 allowable connections.Each pin can be connected to 1,2, or 3 pins on a different side.
The matrix pins are organized in the following geometry:
T0 T1 T2 T3 T4 T5 T6 T7 T8+-------------------------------+
L0| |R0L1| |R1L2| |R2L3| Switch |R3L4| Matrix |R4L5| |R5L6| |R6
L7| |R7L8| |R8
| |+-------------------------------+
B0 B1 B2 B3 B4 B5 B6 B7 B8
The matrix is programmed in the following order of below (connection table follows as well) :
SM_BITS = HTC[7..0] + VRC[15..8] + HBC[7..0] + VLC[15..8] + HTC[15..8] + VRC[7..0] + HBC[15..8] + VLC[7..0]
For example, To make a connection between L0 and B0, bit HTC[7] must be set to high during programming.
The table below provides a translation of each config bit to the correlating wire connections. The conventions usedwill be T0..T8, R0..R8, B0..B8, and L0..L8 corresponding to Top, Right, Bottom, and Left wires.
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Programming 4: Cont…• Connection bit
-----------------L0 - B0 HTC[7]B1 - R0 HTC[6]R1 - T1 HTC[5]R2 - T2 HTC[4]L3 - T2 HTC[3]B2 - R3 HTC[2]R4 - T4 HTC[1]
L2 - B2 HTC[0]
L3 - B3 VRC[15]L4 - B4 VRC[14]R5 - T5 VRC[13]L5 - B5 VRC[12]R6 - T6 VRC[11]R6 - B7 VRC[10]R7 - T7 VRC[9]L7 - B7 VRC[8]
L7 - R8 HBC[7]L6 - R7 HBC[6]L5 - B8 HBC[5]R5 - L5 HBC[4]L2 - R3 HBC[3]L1 - R2 HBC[2]L0 - R1 HBC[1]B7 - T8 HBC[0]
B0 - T0 VLC[15]B1 - T1 VLC[14]
B2 - T2 VLC[13]B3 - T3 VLC[12]B4 - T4 VLC[11]B5 - T5 VLC[10]B6 - T6 VLC[9]B7 - T7 VLC[8]
R0 - T0 HTC[15]
B0 - T1 HTC[14]
L1 - T0 HTC[13]
L2 - T3 HTC[12]
B3 - R2 HTC[11]
R3 - T3 HTC[10]
L4 - T5 HTC[9]L1 - B1 HTC[8]
R5 - B4 VRC[7]
L6 - B6 VRC[6]
L6 - T7 VRC[5]
L7 - T6 VRC[4]
R7 - B6 VRC[3]
B8 - L8 VRC[2]
B8 - R8 VRC[1]R8 - T8 VRC[0]
L8 - T8 HBC[15]
R8 - L8 HBC[14]
R7 - L7 HBC[13]
R6 - L6 HBC[12]
R4 - L4 HBC[11]
R3 - L3 HBC[10]
R2 - L2 HBC[9]R1 - L1 HBC[8]
B1 - T2 VLC[7]
B2 - T3 VLC[6]
B3 - T4 VLC[5]
B4 - T5 VLC[4]
B5 - T6 VLC[3]
B6 - T7 VLC[2]
B8 - T8 VLC[1]R0 - L0 VLC[0]
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Programming 5: Putting it All
together Full Module Programing.
Now that the the programmer knows how to set thebit sequence for each component in the module, the finalbit sequence is the
serial sequence of bits of each component in thefollowing order:
MODULE_BITS = CLB2 + CLB4 + CLB3 + CLB1
+ SM2 + SM4 + SM3 + SM1
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Simulations
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Example 2: Compound Function Logic Sim
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CLB C l Ti i Si l ti
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CLB Capsule Timing Simulations
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CLB Capsule
Simulation
EmulatingProgramming
And Execution
Of a 1 Bit Counter
(also tested a twoBit counter cmd)
Execution
Programming(in the red box)
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CLB CORE
Simulation
Testing CE_Latch
mode
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Programmable
F Block
(4 bit CombinationLogic)
Scan in values
And read out
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Programmable
FD Block
(1 bit register)
All Flip Flop Modes
Tested
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8 Bit Scan Chain
Programming
Example
Switch Matrix Configuration Scan Box Logic Simulation
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Programming
Switch Matrix Pin Connection Logic Simulation
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Programming Single Connection
Terminals
T8 and B8connected
A single
Transmission Gate
Configured On