module-4 · any combination of inputs relates to a unique output. 4.7.1introduction: circuits in...

Module 4: Design and Analysis of Combinational Circuits

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Module-4

Design and Analysis of Combinational Circuits

4.1 Motivation:

This topic develops the fundamental understanding and design of adder, substractor, code

converter multiplexer, demultiplexer etc combinational circuits.

4.2 Syllabus:

Module Contents Duration Self-Study

4.1 Introduction, 01 Lecture 1 hour

4.2 Half and Full Adder, 01 Lecture 2 hours

4.3 Half and Full Subtractor, 01 Lecture 2 hours

4.4 Four Bit Binary Adder,

01 Lecture 2 hours

4.5 One digit BCD Adder, 01 Lecture 2 hours

4.6 code conversion,

01Lecture 2 hours

4.7 Encoder and Decoder , 01Lecture 2 hours

4.8 Multiplexers and De- multiplexers

01 Lectures 2 hours

4.9 Binary comparator (2,3 variable)4-bit Magnitude Comparator IC 7485 and ALU IC74181

01 Lectures 2hours

4.3. Weightage in university Examination: -

4.4. Learning Objective/ Outcome :

4.4.1 Learning Objective: In this module student will try to Design and implementation of

combinational circuits

4.4.2 Learning Outcome: At the end student will be able to Design and develop

combinational circuits

4.5 Theoretical Background:

One has to have basic knowledge of binary addition and subtraction, to describe and

understand the analysis and design of adder and subtractor, also basic knowledge of

code used in digital electronics .


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4.6. Key Definitions:

Combinational

logic

The logic in which the outputs at any instant of time are

dependent only on the inputs present at that time

Literal A logic variable in either inverted or non-inverted form

Maxterm A logical term consisting of all the literals in the ORed forming

logic functions.

Minterm A logical term consisting of all the literals in theANDed forming

logic functions.

Product of

Sum (POS)

A logical expression in the form of ORed terms ANDed together.

Standard POS A POS form of logic expression consisting of only maxterm.

Standard SOP A SOP form of logic expression consisting of only minterm

Don’t care A minterm/maxterm in a logic function may or may not be

included

Essential

Prime

implicants

A tern in SOP form in a logic function that must be present in the

minimal expression

4.7 Objective

This chapter introduces several logical networks that are useful as building blocks for larger systems. Be able to design and build small-to-moderate size circuits. Understand and practice modular design. Understand large complicated circuits. In the following sections, we are going to review a few of the design techniques of Combinational Circuits that we are already familiar with. A combinational circuit is defined as a circuit in which the present output is a function of the present inputs only. Note that:-


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The output may not appear instantaneously, i.e., delays may be associated with a combinational circuit. The output may appear a few nanoseconds after the inputs are available.

Any combination of inputs relates to a unique output. 4.7.1Introduction:

Circuits in which all outputs at any given time depend only on the inputs at that time are called combinational logic circuits. The design procedures will be illustrated with important classes of circuits that are now universal in digital systems. The approach taken is to examine the tasks that a combinational logic circuit is intended to perform and then identify one or more circuits that can perform the task. One circuit may have some specific advantages over others, but it may also have certain deficiencies. Often one factor can be improved, but only at the expense of others. Some important factors are speed of operation, complexity or cost of hardware, power dissipation, and availability in prefabricated units. We will take up a number of different operations that are useful in different contexts and show how appropriate circuits can be designed to carry out these operations. Combinational circuit is a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits are following − The output of combinational circuit at any instant of time, depends only on the levels present at input terminals. The combinational circuit do not use any memory. The previous state of input does not have any effect on the present state of the circuit. A combinational circuit can have an n number of inputs and m number of outputs. Block diagram

Fig 4.1

We're going to elaborate few important combinational circuits as follows.

4.7.2 Half Adder

Half adder is a combinational logic circuit with two inputs and two outputs. The

half adder circuit is designed to add two single bit binary number A and B. It is the basic


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building block for addition of two single bit numbers. This circuit has two outputs carry

and sum.

Block diagram

Fig 4.2

Truth Table

Table 4.1

Circuit Diagram

Fig 4.3

4.7.3 Full Adder

Full adder is developed to overcome the drawback of Half Adder circuit. It can add two

one-bit numbers A and B, and carry c. The full adder is a three input and two output

combinational circuit.


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Block diagram

Fig 4.4

Truth Table

Table 4.2

Circuit Diagram

Fig 4.5


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Full Adder Circuit

A Full Adder is a combinational circuit that performs the arithmetic sum of three input bits. It consists of three inputs and two outputs. Three of the input variables can be defined as A, B, Cin and the two output variables can be defined as S, Cout. The two input variables that we defined earlier A and B represents the two significant bits to be added. The third input Cinrepresents the carry bit. We have to use two digits because the arithmetic sum of the three binary digits needs two digits. The two outputs represents S for sum and Coutfor carry.

For designing a full adder circuit, two half adder circuits and an OR gate is required. It is the simplest way to design a full adder circuit. For this two XOR gates, two AND gates, one OR gate is required.

Truth Table

Input A

Input B Input Cin

Output Cout

Output S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Table 4.3

Solution using K-map For S A\BCin 00 01 11 10

1 1

1 1

S=A'B'Cin+A'BCin'+AB'Cin'+ABCin

http://en.wikipedia.org/wiki/Adder_%28electronics%29

http://implement-logic.blogspot.com/2011/08/half-adder-circuit.html

http://implement-logic.blogspot.com/2011/08/half-adder-circuit.html

http://implement-logic.blogspot.com/2011/07/universal-gate-nor.html

http://implement-logic.blogspot.com/2011/07/normal-0-false-false-false-en-us-x-none.html


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For Cout A\BCin 00 01 11 10

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1 1 1

Cout=AB+ACin+BCin Circuit Diagram

Fig 4.6

Implementation Using Boolean Function For S S=Cin XOR (A XOR B) =Cin'(AB'+A'B)+Cin (AB'+A'B)' =Cin'(AB'+A'B)+Cin(AB+A'B') =AB'Cin'+A'BCin'+ABCin+A'B'Cin For Cout Cout=Cin(AB'+A'B)+AB =AB'Cin+A'BCin+AB This is the simple design procedure of Full Adder circuit.

N-Bit Parallel Adder

The Full Adder is capable of adding only two single digit binary number along with

a carry input. But in practical we need to add binary numbers which are much longer

than just one bit. To add two n-bit binary numbers we need to use the n-bit parallel adder.

http://4.bp.blogspot.com/-NIy45k3TuEE/TkouUTvUOZI/AAAAAAAAAG8/SQiB48Yi_UQ/s1600/550px-Full-adder.png


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It uses a number of full adders in cascade. The carry output of the previous full adder is

connected to carry input of the next full adder.

4 Bit Parallel Adder

In the block diagram, A0 and B0 represent the LSB of the four bit words A and B.

Hence Full Adder-0 is the lowest stage. Hence its Cin has been permanently made 0. The

rest of the connections are exactly same as those of n-bit parallel adder is shown in fig.

The four bit parallel adder is a very common logic circuit.

Block diagram

Fig 4.7

4.7.4 N-Bit Parallel Subtractor

The subtraction can be carried out by taking the 1's or 2's complement of the

number to be subtracted. For example we can perform the subtraction (A-B) by adding

either 1's or 2's complement of B to A. That means we can use a binary adder to perform

the binary subtraction.

4 Bit Parallel Subtractor

The number to be subtracted (B) is first passed through inverters to obtain its 1's

complement. The 4-bit adder then adds A and 2's complement of B to produce the

subtraction. S3 S2 S1 S0 represents the result of binary subtraction (A-B) and carry output

Cout represents the polarity of the result. If A > B then Cout = 0 and the result of binary

form (A-B) then Cout = 1 and the result is in the 2's complement form.


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Block diagram

Fig 4.8

Half Subtractors

Half subtractor is a combination circuit with two inputs and two outputs (difference

and borrow). It produces the difference between the two binary bits at the input and also

produces an output (Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-

B), A is called as Minuend bit and B is called as Subtrahend bit.

Truth Table

Table 4.4


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Circuit Diagram

Fig 4.9

Full Subtractors

The disadvantage of a half subtractor is overcome by full subtractor. The full

subtractor is a combinational circuit with three inputs A,B,C and two output D and C'. A is

the 'minuend', B is 'subtrahend', C is the 'borrow' produced by the previous stage, D is the

difference output and C' is the borrow output.

Truth Table

Table 4.5


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Circuit Diagram

Fig 4.10 Four Bit Binary Adder, A 4-bit Ripple Carry Adder

Fig 4.11

One main disadvantage of “cascading” together 1-bit binary adders to add large binary numbers is that if inputs A and B change, the sum at its output will not be valid until any carry-input has “rippled” through every full adder in the chain because the MSB (most significant bit) of the sum has to wait for any changes from the carry input of the LSB (less significant bit). Consequently, there will be a finite delay before the


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output of the adder responds to any change in its inputs resulting in a accumulated delay.

When the size of the bits being added is not too large for example, 4 or 8 bits, or the summing speed of the adder is not important, this delay may not be important. However, when the size of the bits is larger for example 32 or 64 bits used in multi-bit adders, or summation is required at a very high clock speed, this delay may become prohibitively large with the addition processes not being completed correctly within one clock cycle.

This unwanted delay time is called Propagation delay. Also another problem called “overflow” occurs when an n-bit adder adds two parallel numbers together whose sum is greater than or equal to 2n

One solution is to generate the carry-input signals directly from the A and B inputs rather than using the ripple arrangement above. This then produces another type of binary adder circuit called a Carry Look Ahead Binary Adder where the speed of the parallel adder can be greatly improved using carry-look ahead logic.

The advantage of carry look ahead adders is that the length of time a carry look ahead adder needs in order to produce the correct SUM is independent of the number of data bits used in the operation, unlike the cycle time a parallel ripple adder needs to complete the SUM which is a function of the total number of bits in the addend.

4-bit full adder circuits with carry look ahead features are available as standard IC packages in the form of the TTL 4-bit binary adder 74LS83 or the 74LS283 and the CMOS 4008 which can add together two 4-bit binary numbers and generate a SUM and a CARRY output as shown.

74LS83 Logic Symbol

Fig 4.12


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4.7.5 BCD Adder (One digit BCD Adder,)

A BCD adder is a digital combinational circuit thatadd two BCD number and produces a sum digit in BCD. It consists of two 4-bit adder. The two decimal digits, together withthe input carry are first added in the top 4-bit adder to producethe binary sum. When the output carry is equal to 0, nothing isadded to binary sum. When it is equal to 1 then binary 0110 isadded to binary sum through the bottom 4-bit adder.

If two BCD digits are added then their sum result will not always be in BCD. Consider the two given examples.

In the first example, result is in BCD while in the second example it is not in BCD. Four bits are needed to represent all BCD digits (0 – 9). But with four bits we can represent up to 16 values (0000 through 1111). The extra six values (1010 through 1111) are not valid BCD digits.

Whenever the sum result is > 9, it will not be in BCD and will require correction to get a valid BCD result.

http://4.bp.blogspot.com/-2tCMXHG-pRo/TsN4WbyDFdI/AAAAAAAAAN0/i7c452MHQqg/s1600/Capture8.PNG


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Table 4.6

Correction is done through the addition of 6 to the result to skip the six invalid

values as shown in the truth table by yellow color. Consider the given examples of non-BCD sum result and its correction.

http://4.bp.blogspot.com/-cjBfCSIZK74/TsN4lMUJUeI/AAAAAAAAAN8/0ZXGx-SrKvo/s1600/Capture9.PNG


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A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum BCD digit and a carry out bit.

The maximum sum result of a BCD input adder can be 19. As maximum number in BCD is 9 and may be there will be a carry from previous stage also, so 9 + 9 + 1 = 19

The following truth table shows all the possible sum results when two BCD digits are added.

http://implement-logic.blogspot.com/2011/08/full-adder-circuit_16.html

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Table 4.7

The logic circuit that checks the necessary BCD correction can be derived by

detecting the condition where the resulting binary sum is 01010 through 10011 (decimal 10 through 19). It can be done by considering the shown truth table, in which the function F is true when the digit is not a valid BCD digit. It can be simplified using a 5-variable K-map.

But detecting values 1010 through 1111 (decimal 10 through 15) can also be done by using a 4-variable K-map as shown in the figure.

http://4.bp.blogspot.com/-X8PqzpuJJjc/TsN5LCHfp5I/AAAAAAAAAOM/0PucuiyJksM/s1600/Capture11.PNG

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Values greater than 1111, i.e., from 10000 through 10011 (decimal 16 through 19)

can be detected by the carry out (CO) which equals 1 only for these output values. So, F = CO = 1 for these values. Hence, F is true when CO is true OR when (Z3 Z2 + Z3 Z1) is true.

Thus, the correction step (adding 0110) is performed if the following function equals 1:

F = CO + Z3 Z2 + Z3 Z1 The circuit of the BCD adder will be as shown in the figure.

Fig 4.13

The two BCD digits, together with the input carry, are first added in the top 4-bit binary adder to produce the binary sum. The bottom 4-bit binary adder is used to add the correction factor to the binary result of the top binary adder. Note:

4. When the Output carry is equal to zero, the correction factor equals zero. 2. When the Output carry is equal to one, the correction factor is 0110.

The output carry generated from the bottom binary adder is ignored, since it

supplies information already available at the output-carry terminal.

http://implement-logic.blogspot.com/2011/08/full-adder-circuit_16.html

http://implement-logic.blogspot.com/2011/11/binary-parallel-addersubtractor.html

http://implement-logic.blogspot.com/2011/11/binary-parallel-addersubtractor.html

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A decimal parallel adder that adds n decimal digits needs n BCD adder stages. The output carry from one stage must be connected to the input carry of the next higher-order stage. 4.7.6 THE BINARY TO GRAY CODE CONVERTER (i)No. of inputs and outputs

Number of inputs = 4 Number of outputs = 4 (ii)Assigning letter symbols

Symbols of inputs = B4, B3, B2, B1 Symbols of outputs = G4, G3, G2, G1 where B4Â is most significant bit and B1 is least significant bit.

(iii)Truth table

INPUT OUTPUT

B4 B3 B2 B1 G4 G3 G2 G1

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1


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1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

(iv) Boolean equation

G4

All the entries of B4Â and G4 are same in truth table.

G4 = B4

G3 G2

G1

http://www.knowelectronics.org/wp-content/uploads/2012/12/g31.jpg



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Fig 4.14 Logic Diagram

(i) No. of inputs and outputs Number of inputs = 4 Number of outputs = 5 (ii) Assigning letter symbols Symbols of inputs – B4, B3, B2, B1 Symbols of outputs – A, B, C, D, E

(iii) Truth table

As the range of BCD is from 0 to 9, a additional bit ‘A’ is taken. ’A’ is 1 or high when input is more than 9 i.e. it is high for 10, 11, 12, 13, 14 and 14.

INPUT OUTPUT

B4 B3 B2 B1 A B C D E

0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 1

0 0 1 0 0 0 0 1 0

0 0 1 1 0 0 0 1 1

0 1 0 0 0 0 1 0 0

0 1 0 1 0 0 1 0 1


http://www.knowelectronics.org/wp-content/uploads/2012/12/binary-to-gray-code-converter.png


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0 1 1 0 0 0 1 1 0

0 1 1 1 0 0 1 1 1

1 0 0 0 0 1 0 0 0

1 0 0 1 0 1 0 0 1

1 0 1 0 1 0 0 0 0

1 0 1 1 1 0 0 0 1

1 1 0 0 1 0 0 1 0

1 1 0 1 1 0 0 1 1

1 1 1 0 1 0 1 0 0

1 1 1 1 1 0 1 0 1

(iv) Boolean equation

E

All the entries of E and B1 are same in truth table.

E = B1

D

Binary to BCD converter ‘D’ truth table

D = B4‘B2 + B4B3B2‘

C

C = B4‘B3 + B3B2

B

http://www.knowelectronics.org/binary-to-bcd-code-converter/capture3-5/


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Through Boolean manipulation we get,

B = B4B3‘B2‘

A

A = B4B3 + B4B2

4.7.7 Decoder

A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs.

Decoder is identical to a demultiplexer without any data input. It performs operations

which are exactly opposite to those of an encoder.

Block diagram

Fig 4.15

Examples of Decoders are following.

Code converters

BCD to seven segment decoders

Nixie tube decoders

Relay actuator

2 to 4 Line Decoder

The block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two inputs

where D through D are the four outputs. Truth table explains the operations of a decoder.

It shows that each output is 1 for only a specific combination of inputs.


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Block diagram

Fig 7.16

Truth Table

Table 4.8

Logic Circuit

Fig 4 .17


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Encoder

Encoder is a combinational circuit which is designed to perform the inverse operation

of the decoder. An encoder has n number of input lines and m number of output lines.

An encoder produces an m bit binary code corresponding to the digital input number.

The encoder accepts an n input digital word and converts it into an m bit another digital

word.

Block diagram

Fig 4.18

Examples of Encoders are following.

Priority encoders

Decimal to BCD encoder

Octal to binary encoder

Hexadecimal to binary encoder

Priority Encoder

This is a special type of encoder. Priority is given to the input lines. If two or more input

line are 1 at the same time, then the input line with highest priority will be considered.

There are four input D0, D1, D2, D3 and two output Y0, Y4. Out of the four input D3 has the

highest priority and D0 has the lowest priority. That means if D3 = 1 then Y1Y1 = 11

irrespective of the other inputs. Similarly if D3 = 0 and D2 = 1 then Y1 Y0 = 10 irrespective

of the other inputs.

Block diagram


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Fig 4.19

Truth Table

Fig 4.8


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Logic Circuit

Fig 4.20

4.7.8.1 Multiplexers

Multiplexer is a special type of combinational circuit. There are n-data inputs, one

output and m select inputs with 2m = n. It is a digital circuit which selects one of the n

data inputs and routes it to the output. The selection of one of the n inputs is done by the

selected inputs. Depending on the digital code applied at the selected inputs, one out of n

data sources is selected and transmitted to the single output Y. E is called the strobe or

enable input which is useful for the cascading. It is generally an active low terminal that

means it will perform the required operation when it is low.

Block diagram


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Fig 4.21

Multiplexers come in multiple variations

2 : 1 multiplexer

4 : 1 multiplexer

16 : 1 multiplexer

32 : 1 multiplexer

Block Diagram

Fig 4.22


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Truth Table

Table 4.10

4.7.8.2 Demultiplexers

A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input

and distributes it over several outputs. It has only one input, n outputs, m select input. At

a time only one output line is selected by the select lines and the input is transmitted to

the selected output line. A de-multiplexer is equivalent to a single pole multiple way

switch as shown in fig.

Demultiplexers comes in multiple variations.

1 : 2 demultiplexer

1 : 4 demultiplexer

1 : 16 demultiplexer

1 : 32 demultiplexer

Block diagram


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Fig 4.23

Truth Table

Fig 4.11

4.7.9 Digital or Binary Comparators

Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that compare the digital signals present at their input terminals and produce an output depending upon the condition of those inputs.

For example, along with being able to add and subtract binary numbers we need to be able to compare them and determine whether the value of input A is greater than, smaller than or equal to the value at input B etc. The digital comparator accomplishes this using several logic gates that operate on the principles of Boolean algebra. There are two main types of Digital Comparator available and these are.

4. Identity Comparator – an Identity Comparator is a digital comparator that has only one output terminal for when A = B either “HIGH” A = B = 1 or “LOW” A = B = 0


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2. Magnitude Comparator – a Magnitude Comparator is a digital comparator which has three output terminals, one each for equality, A = B greater than, A > B and less than A < B

The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for example A (A1, A2, A3,…. An, etc) against that of a constant or unknown value such as B (B1, B2, B3,….Bn, etc) and produce an output condition or flag depending upon the result of the comparison. For example, a magnitude comparator of two 1-bits, (A and B) inputs would produce the following three output conditions when compared to each other.

Which means: A is greater than B, A is equal to B, and A is less than B

This is useful if we want to compare two variables and want to produce an output when any of the above three conditions are achieved. For example, produce an output from a counter when a certain count number is reached. Consider the simple 1-bit comparator below.

1-bit Digital Comparator Circuit

Fig 4.24

Then the operation of a 1-bit digital comparator is given in the following Truth Table.

Digital Comparator Truth Table

Inputs Outputs

B A A > B A = B A < B

0 0 0 1 0

0 1 1 0 0


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1 0 0 0 1

1 1 0 1 0

You may notice two distinct features about the comparator from the above truth table. Firstly, the circuit does not distinguish between either two “0” or two “1”‘s as an output A = B is produced when they are both equal, either A = B = “0” or A = B = “1”. Secondly, the output condition for A = B resembles that of a commonly available logic gate, the Exclusive-NOR or Ex-NOR function (equivalence) on each of the n-bits giving: Q = A ⊕ B

Digital comparators actually use Exclusive-NOR gates within their design for comparing their respective pairs of bits. When we are comparing two binary or BCD values or variables against each other, we are comparing the “magnitude” of these values, a logic “0” against a logic “1” which is where the term Magnitude Comparator comes from.

As well as comparing individual bits, we can design larger bit comparators by cascading together n of these and produce ann-bit comparator just as we did for the n-bit adder in the previous tutorial. Multi-bit comparators can be constructed to compare whole binary or BCD words to produce an output if one word is larger, equal to or less than the other.

A very good example of this is the 4-bit Magnitude Comparator. Here, two 4-bit words (“nibbles”) are compared to each other to produce the relevant output with one word connected to inputs A and the other to be compared against connected to input B as shown below.

4-bit Magnitude Comparator

Fig 4.25


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Some commercially available digital comparators such as the TTL 74LS85 or CMOS 4063 4-bit magnitude comparator have additional input terminals that allow more individual comparators to be “cascaded” together to compare words larger than 4-bits with magnitude comparators of “n”-bits being produced. These cascading inputs are connected directly to the corresponding outputs of the previous comparator as shown to compare 8, 16 or even 32-bit words.

4.8 Objective Type Questions: 1) A full-adder has a Cin = 0. What are the sum () and the carry (Cout) when A = 1 and B = 1? a) ∑ =0, Cout = 0

b) ∑ = 0, Cout = 1

c) ∑= 1, Cout = 0

d) ∑= 1, Cout = 1

2) Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input is 4. What are the values for the sum and carry output? a) ∑4∑3∑2∑1 = 0111, Cout= 0 s

b) ∑4∑3∑2∑1 = 1111, Cout= 1

c) ∑4∑3∑2∑1 = 1011, Cout= 1

d) ∑4∑3∑2∑1 = 1100, Cout= 1

3) How many 4-bit parallel 2 adders would be required to add two binary numbers each representing decimal numbers up through 30010? a) 1

b) 2

c) 3

d) 4

4) The carry propagation can be expressed as ________. a) Cp = AB

b) Cp = A + B


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c) Cp =

d) Cp = A+B

5) Which gate is best used as a basic comparator? a) NOR

b) OR

c) Exclusive-OR

d) AND

6) The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? a) A > B = 1, A < B = 0, A < B = 1

b) A > B = 0, A < B = 1, A = B = 0

c) A > B = 1, A < B = 0, A = B = 0

d) A > B = 0, A < B = 1, A = B = 1

7) Which of the following combinations of logic gates can decode binary 1101? a) one 4-input AND gate

b) one 4-input AND gate, one OR gate

c) one 4-input NAND gate, one inverter

d) one 4-input AND gate, one inverter

8) A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW

outputs. Which output goes LOW when the inputs are 1001? a) 0

b) 3

c) 9

d) None. All outputs are HIGH.

9) How many 1-of-16 decoders are required for decoding a 7-bit binary number? a) 5

b) 6

c) 7

d) 8

10) How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? a) 1

b) 2


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c) 4

d) 8

11) A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What would be the state of the four outputs if inputs 4 and 5 are LOW and all other inputs are HIGH?

a) A0=0, A1 =1, A2=0, A3=1

b) A0=0, A1 =1, A2=0, A3=1

c) A0=0, A1 =1, A2=0, A3=1

d) A0=0, A1 =1, A2=0, A3=1

12) How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have? a) 3

b) 4

c) 5

d) 6

13) Convert BCD 0001 0111 to binary.

a) 10101

b) 10010

c) 10001

d) 11000

14) Convert BCD 1100 0110 to binary.

a) 1111110

b) 1111101

c) 1111000

d) 1111111

15) How many data select lines are required for selecting eight inputs? a) 1

b) 2

c) 3

d) 4

16) A decoder can be used as a demultiplexer by ________. a) tying all enable pins LOW

b) tying all data-select lines LOW


35

c) tying all data-select lines HIGH

d) using the input lines for data selection and an enable line for data input

17) The device shown here is most likely a ________. a) comparator

b) multiplexer

c) demultiplexer

d) parity generator

18) For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW. What is the status of the Y output? a) LOW

b) HIGH

c) Don't care

d) The status cannot be determined.

19) For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be HIGH. What is the status of the Y output? a) LOW

b) HIGH

c) Don't care

d) The status cannot be determined.

20) The device shown here is most likely a ________. a) comparator

b) multiplexer

c) demultiplexer

d) parity generator

21) For the device shown here, assume the D input is LOW,

both S inputs are HIGH, and the input is HIGH. What is

the status of the outputs? a) All are HIGH.

b) All are LOW.

c) All but 0 are LOW.


36

d) All but 0 are HIGH.

22) For the device shown here, assume the D input is LOW,

both S inputs are LOW, and the input is LOW. What is the

status of the outputs? a) All are HIGH.

b) All are LOW.

c) All but 0 are LOW.

d) All but 0 are HIGH.

23) Which of the following devices has the largest number of output terminals? a) 74XX42 BCD-to-decimal decoder

b) 74XX47 BCD-to-7-segment decoder

c) 74XX151 8-input multiplexer

d) 74XX154 1-of-16-line decoder

24) When adding an even parity bit to the code 110010, the result is ________. a) 1110010

b) 1111001

c) 110010

d) 001101

25) Which of the following statements is true? a) Glitches are usually caused by timing problems.

b) Glitches only occur in programmable logic simulations.

c) Glitches cannot be avoided or eliminated.

d) Glitches are mainly software bugs.

Answer: 1) b, 2)c, 3)c, 4) b, 5)c 6) a, 7) d, 8) c,9)d, 10)c, 11) d, 12) b, 13) c, 14) a, 15) c 16) d, 17) b, 18) a, 19) a, 20) c, 21) a, 22) c, 23) d, 24) a, 25) a 4. 9 Subjective Questions 1) Implement the following using 8:1mux and few gates

f = ∑ (0,1,3,4,5,7,9,10,12,13,14,15,17,21,22,23,24,28,29,30,31)


37

2) Design a BCD To Exess-3 code converter using minimum number of NAND gates.

3) Design a one digit BCD to Binary converter using IC 74184.

4) Design a 4 digit BCD adder using IC

5) Design a BCD to 7 segment decoder with active low outputs using Exess-3 code

converter using

(a) Dual 4:1 multiplexer and some gates. (b) 1:16 demultiplexer and some gates (c) A BCD to decimal decoder and NAND gates

6) Design a full adder using suitable decoder

7) Design a two bit magnitude comparator circuit using gates

8) Design a BCD -7 segment display decoder 4.

Design full subtractor using two half subtractor

9) Design and implement BCD-to excess 3 code convertor using suitable decoder and

minimum number of logic gates

10) A and B are the 2 bit input to the comparator for the following condition

1. A = B

2. A< B

3. A>B

11) Implement the following using 8:1 MUX

F(A,B,C)=∑m(0,1,2,4,6,7,8,10,14,15)

12) Design a 4-bit adder (BCD adder) using IC7483

13) Design a 3 bit even and odd parity generator

14) State truth table of 3 bit gray to binary conversion and design using 3:8

15) Decoder and additional gates.

16) Design full adder using 3:8 decoder with active low output and NAND gates

17) Design a 2 bit digital magnitude comparator and implement using NAND gates only

18) Design 32:1 multiplexer using 4:1 multiplexers

19) Implement F(A,B,C,D) = ∑m(1,2,3,4,6,7,9,10,11,12,13,15) using

(i) one 8:1 multiplexer

(ii) 4:1 multiplexers tree

4.10 References

1. R.P Jain, “Modern Digital Electronics”,Tata McGraw Hill.


38

2. John F Wakerly, “Digital Design Principles and Practices”, Pearson

Education,Russia.

3. M.MorrisMano,”Digital Logic and Computer Design”,PHI.

4. John M Yarbough,”Digital Logic”,Thomas Learning.

5. Samuel Lee “Digital Circuits and Logic Design”,PHI.

Self-evaluation

Name of

Student

Class SE

Roll No.

Subject Logic Design

Module No. 04

S.No Tick

Your choice

1. Do you understand the combinational circuits ? o Yes

o No

2. Do you understand multiplexers and

demultiplexers?

o Yes

o No

3. Do you understand different adders and

substractor?

o Yes

o No

4. Do you understand how comparator works s?

o Yes

o No

5. Do you understand module ?

Yes, Completely.

Partialy.

No, Not at all.

module-4 · any combination of inputs relates to a unique output. 4.7.1introduction: circuits in...

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