modular dc to dc converter

5128 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 11, NOVEMBER 2013

Secondary-Side Phase-Shift-Controlled ZVS DC/DCConverter With Wide Voltage Gain for High Input

Voltage ApplicationsWuhua Li, Member, IEEE, Sheng Zong, Fangrui Liu, Huan Yang, Member, IEEE, Xiangning He, Fellow, IEEE,

and Bin Wu, Fellow, IEEE

Abstract—In this paper, a soft-switching dc/dc converter withsecondary-side phase-shift control strategy is proposed to improvethe conversion efficiency and minimize the primary switch volt-age stress in the high input voltage applications. Zero-voltage-switching performance is achieved for both the primary- andsecondary-side power devices in a wide load range to reducethe switching losses due to the secondary-side phase-shift controlscheme. Furthermore, compared with the conventional phase-shiftcontrol mechanism, the circulating current at the freewheelingstage is effectively suppressed as well to minimize the conductionlosses. Moreover, the voltage stress of the primary switches is onlyhalf of the input voltage by employing the improved three-levelstructure, which makes the low-voltage rated power devices avail-able to improve the circuit performance. In addition, the convertercan work in the buck, balance, and boost modes to achieve a rela-tively wide input voltage range, which is an expected advantage forthe communication power system to minimize the electrolytic ca-pacitors with an acceptable hold-up time. The operation principleis analyzed and experimental results of a 1-kW 100-kHz prototypeare provided to verify the effectiveness and the advantages of theproposed converter.

Index Terms—High input voltage applications, secondary-sidephase-shift control, wide voltage conversion range, zero-voltageswitching (ZVS).

I. INTRODUCTION

IN the high input voltage applications, the high-voltage ratedswitching devices are commonly required to construct the

conventional full-bridge dc/dc converters. However, the con-duction resistor RDS ON of the switching devices increases ex-ponentially as the voltage stress rises, which results in the severeconduction losses. Recently, many research contributions have

Manuscript received July 10, 2012; revised September 5, 2012 and October10, 2012; accepted January 11, 2013. Date of current version May 3, 2013. Thiswork was supported by the National Basic Research Program of China (973Program 2012CB215106), the National Nature Science Foundations of Chinaunder Grant 51277195 and Grant 50907060, and the Power Electronics Scienceand Education Development Program of Delta Environmental & EducationalFoundation Grant DREG2011002. Recommended for publication by AssociateEditor F. L. Luo.

W. Li, S. Zong, H. Yang, and X. He are with the College of Electrical Engi-neering, Zhejiang University, Hangzhou 310027, China (corresponding e-mail:[email protected]).

F. Liu and B. Wu are with the Department of Electrical and ComputerEngineering, Ryerson University, Toronto ON M5B 2K3, Canada (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2013.2242490

been carried out to make the low-voltage rated power devicesavailable in the high input voltage conversion systems. One ofthe main concepts is to connect the switches in series to sustainthe high voltage stress. In [1], three pairs of series switches areconnected in the primary side, which reduces the switch voltagestress to only one-third of the high input voltage. This topologyis further extended to N pairs of series switches [2], where theswitch voltage stress is reduced to one N th of the high inputvoltage. Unfortunately, the number of the transformer windingsas well as the control complexity increases as N goes up. A rec-tifier is added to the middle pair of the three series switch pairs torealize the voltage autobalance of the series input capacitors [3].Nevertheless, the auxiliary snubber and the extra rectifier in-crease the power losses. Apart from the bridge-type topology,Qian and Lehman [4] present a coupled dual-interleaved flybackconverter. The voltage stress is reduced to half of that of the con-ventional flyback converter. However, it still remains higher thanhalf of the input voltage due to the inversely addressed outputvoltage in the primary side of the transformer. A three-switchactive-clamped forward converter is introduced in [5], whereasthe voltage stress is only reduced to around the input voltage andthe soft-switching is not achieved, which impacts the efficiencyimprovements.

Although the conventional phase-shift full-bridge (PSFB)converter has some clear advantages in the low-voltage appli-cations, the circulating current at the freewheeling stage causesadditional losses, especially when the duty cycle is small. Largeamount of work has been done to solve this problem. Gener-ally, some extra components are added to suppress the circulat-ing current to reduce power losses. For instance, an auxiliarytransformer or an extra winding is introduced to the converter,through which the energy in the inductor is fed back to the inputor output terminals [6]–[8]. In [9] and [10], the main transformerhas a center tap on the secondary winding, and a capacitor andsome auxiliary diodes are connected in the secondary side tosuppress the circulating current and recycle the energy of the in-ductor. A blocking capacitor and a saturable inductor instead ofan usual inductor are adopted in the primary side to eliminate thefreewheeling current and achieve zero-current switching (ZCS)of the lagging leg with extended load range [11], [12], but thesaturable inductor causes additional core losses due to the largepeak-to-peak flux density, which may result in the high induc-tor temperature. Furthermore, the secondary-side diodes in theconventional PSFB converters are connected in series with theactive switches to reduce the circulating current and minimize

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LI et al.: SECONDARY-SIDE PHASE-SHIFT-CONTROLLED ZVS DC/DC CONVERTER WITH WIDE VOLTAGE GAIN 5129

the leakage inductance [13]–[15]. Unfortunately, the two ac-tive secondary-side switches cause extra losses especially in thehigh step-down applications. All the aforementioned improvedconverters are derived from the conventional PSFB topology byinserting some additional power components. These convertershave to sacrifice the inherent structural simplicity of the PSFBconverters to tackle the problem of the circulating current andvoltage spikes on the secondary rectifier diodes. Unfortunately,other unexpected problems emerge, such as the complex circuitstructure, low controllability, and extra power losses.

In addition, in order to reduce the primary switch voltagestress, the conventional three-level structure is widely adoptedand discussed in [16]–[18], and the switch voltage stress isreduced to half of the input voltage, which is essential for thehigh input voltage applications. However, the circulating lossesand the voltage spikes on the secondary-side diodes still existwith the conventional phase-shift control scheme.

In order to overcome the disadvantages of the conventionalphase-shift control scheme, secondary-side phase-shift (SSPS)control strategy is proposed in [19], [20], where the duty cycle ofboth the primary and secondary active switches keeps 0.5 and thephase-shift angle between the primary and secondary switches isemployed as the control freedom to regulate the output voltage.With the SSPS control strategy, the output filter inductor in theconventional phase-shift converter can be removed to simplifythe circuit structure. Moreover, the freewheeling current is effec-tively suppressed and the voltage spikes on the secondary-sideswitches are eliminated. However, how to employ the advancedsecondary-side phase-shift control strategy in the high inputvoltage applications with reduced primary switch voltage stressstill remains unclear and it is necessary to carry out more scien-tific discovery and research exploration. Besides, how to achievehigh-efficiency dc/dc conversion in a wide voltage range is anemergent research topic in the renewable energy applicationsand communication power systems [21], [22]. For example, theoutput voltage of the photovoltaic (PV) array may fluctuate byover 100% due to the change of the ambient environment. Theadopted front-end dc/dc converters in the grid-connected PVsystem have to provide high-efficiency conversion with a widevoltage conversion range. Also in the communication powersupply system, the front-end dc/dc converters with a wide volt-age conversion range are required to extend the hold-up timewith minimum electrolytic capacitors, which cannot only im-prove the power density, but also enhance the system reliability.As a result, how to achieve high-efficiency and wide voltagegain conversion with the advanced secondary-side phase-shiftcontrol strategy is another interesting and valuable innovation.

An SSPS-controlled ZVS dc/dc converter with reducedswitch voltage stress is proposed in this paper. The improvedthree-level structure is employed in the primary side to reducethe switch voltage stress to half of the input voltage. As a result,the low-voltage rated devices can be used to improve the cir-cuit performance. In addition, due to the SSPS control scheme,ZVS switching is achieved for all the power devices in a wideload range without any auxiliary components. Different fromthe conventional primary-side phase-shift converters, there isno circulating current at the freewheeling stage, which reduces

Fig. 1. Proposed SSPS ZVS dc/dc converter.

the conduction losses effectively. And the overshoots on the rec-tifier are effectively suppressed since the rectifier is clamped tothe output voltage. Moreover, the converter can work in threemodes, including the buck, balance, and boost modes, whichmeans the converter has a wide voltage conversion range. Allthe advantages make the proposed converter competitive in thehigh input voltage and wide range conversion applications, suchas the three-phase front-end communication power systems.

II. PROPOSED CONVERTER AND OPERATIONAL PRINCIPLE

The proposed SSPS-controlled ZVS dc/dc converter for thehigh input voltage application is shown in Fig. 1, where all of thefour primary switches have the constant duty cycle of 0.5. Theouter pair of switches Sp1 and Sp4 turns ON and OFF simul-taneously, while the inner pair of switches Sp2 and Sp3 sharesthe same gate signal. The two pairs of the primary switchesoperate in the complementary manner. The two secondary-sideswitches Ss1 and Ss2 also act with 0.5 duty cycle comple-mentarily. The phase-shift angle between the primary and sec-ondary active switches is employed to control the output voltageand power. LLk stands for the transformer leakage inductance,which usually includes an external inductor if the practical leak-age inductance is not large enough to realize the expected circuitoperation. The input series capacitors C1 and C2 have the samecapacitance to clamp the primary switch voltage stress to half ofthe input voltage. vp and vs are the voltages on the primary sideand the secondary side of the transformer, respectively. Andip and is are the primary and secondary currents through thetransformer with the positive direction shown in Fig. 1.

The operations of the proposed converter are elaborated in thissection. According to the work conditions of the primary cur-rent, the converter has three different operation modes, namelycontinuous current mode 1 (CCM1), continuous current mode 2(CCM2), and discontinuous current mode (DCM), respectively.Considering only half of the input voltage is imposed on the pri-mary side of the transformer, in order to simplify the analysis,the gain G is defined as

G =2NVout

Vin(1)

where Vin , Vout , and N are the input voltage, output voltage,and transformer turns ratio n1 /n2 , respectively. The convertercan work in the buck mode (G < 1), balance mode (G = 1),and boost mode (G > 1). And the primary current increases,


Fig. 2. Waveforms of CCM1 balance mode.

keeps constant, and decreases at the power-transferring stage ofthe three modes, respectively.

A. CCM1 Mode

The key voltage and current waveforms in the balance modeare shown in Fig. 2. The corresponding equivalent circuit atevery stage is illustrated in Fig. 3. As given in Fig. 2, ϕ is thephase-shift angle between the leading primary switches and thecorresponding lagging secondary active switch. β is the timeinterval during which the primary current returns to zero afterthe primary active switches turn OFF. ϕ ≥ β is met in the CCM1mode. Due to the symmetrical operations, only the first sevenstages are analyzed as follows.

Stage 1 [θ0 , θ1]: During this interval, the primary currentip flows reversely through Sp1 and Sp4 . The power is deliveredfrom LLk to the input and the secondary side. The output voltageVout is adversely addressed in the secondary side of the trans-former. Due to the negative voltage across the leakage inductor,the current ip declines rapidly, which is expressed as

ip = ip(θ0) +NVout

LLk(1/G + 1)(θ − θ0), (θ0 ≤ t < θ1).

(2)In the CCM1 mode, Stage 1 lasts for phase angle β. That is

β = θ1 − θ0 . (3)

Stage 2 [θ1 , θ2]: At θ1 , ip reaches zero and starts increasinglinearly due to half of the input voltage across the leakage in-ductor. As ip reverses, the secondary-side current is begins tocirculate freely through Ss1 and the antiparallel diode of Ss2 .The voltage of both sides of the transformer is zero. The poweris delivered from Vin to LLk . ip is regulated by

ip = ip(θ1) +NVout

GLLk(θ − θ1), (θ1 < θ ≤ θ2). (4)

Fig. 3. Equivalent circuits in CCM1 and CCM2. (a) Stage 1: θ0 -θ1 . (b1) Stage2 of CCM1: θ1 -θ2 . (b2) Stage 2 of CCM2: θ1 -θ2 . (c1) Stage 3 of CCM1: θ2 -θ3 .(c2) Stage 3 of CCM2: θ2 -θ3 . (d1) Stage 4 of CCM1: θ3 -θ4 . (d2) Stage 4 ofCCM2: θ3 -θ4 . (e) Stage 5: θ4 -θ5 . (f) Stage 6: θ5 -θ6 . (g) Stage 7: θ6 -θ7 .


Fig. 3. Continued.

In the CCM1 mode, ip keeps increasing at this stage. As aresult, the ZVS-on of Ss2 is achieved naturally. There is not anyextra condition to be satisfied for the ZVS-on operation of thesecondary-side switches.

Stage 3 [θ2 , θ3]: Ss1 turns OFF at θ2 and Cs1 is charged toVout by is at the end of this stage. ip is regulated by (4) until θ3 .And the phase angle ϕ is expressed as

ϕ = θ3 − θ0 . (5)

Stage 4 [θ3 , θ4]: When Cs1 is charged to Vout at θ3 ,Do1becomes forward-biased. is flows through Do1 and the bodydiode of Ss2 , delivering the power from Vin to the load. Mostof the power is transferred to the load during this stage which isnamed as the power-transferring stage. The primary current canbe obtained as

ip = ip(θ3) +NVout

LLk(1/G − 1)(θ − θ3), (θ3 < θ ≤ θ7).

(6)In the balance mode, G = 1 and ip keeps constant during this

stage, as shown in Fig. 2. If the converter operates in the buck orboost modes, ip will increase or decrease, respectively, duringthis stage.

Stage 5 [θ4 , θ5]: At the beginning of this interval, Ss2 turnsON with ZVS and begins working in the synchronous rectifica-tion mode. The primary current is also regulated by (6).

Stage 6 [θ5 , θ6]: At θ5 , Sp1 and Sp4 turn OFF. ZVS turn-offsoft switching performance for Sp1 and Sp4 is achieved due tothe parallel capacitors Cp1 and Cp4 . Cp1 and Cp4 are charged,while Cp2 and Cp3 are discharged by the primary current. Allthe parallel capacitors can be charged or discharged completely

Fig. 4. Waveforms of CCM2.

before Sp1 and Sp2 turn ON only if the energy stored in LLk

is large enough. The ZVS condition will be analyzed further inthe next section.

Stage 7 [θ6 , θ7]: When Cp2 and Cp3 are discharged com-pletely, the antiparallel diodes of Sp2 and Sp3 are forward-biased, which enables ZVS-on of Sp2 and Sp3 . The primarycurrent decreases rapidly due to the negative voltage across LLk ,which is the sum of 1

2 Vin and NVout . At the end of Stage 7, ipbecomes negative but has the same absolute value as that at thebeginning of Stage 1, which is expressed as

ip(θ7) = −ip(θ0). (7)

The succeeding operation stages from 8 to 13 are similar toStage 1–7.

B. CCM2 Mode

The above analysis of the CCM1 mode is based on the condi-tion of ϕ ≥ β, which means the secondary-side semiconductordevices commutate after ip returns to zero. If that is not thecase, i.e., ϕ < β, the circuit will enter the CCM2 mode. Thekey waveforms of the CCM2 mode are shown in Fig. 4 andthe operational stages are illustrated in Fig. 3. As shown inFig. 4, in the CCM2 mode, the converter can only work in thebuck mode because the voltage across the leakage inductor mustbe positive in order to increase the primary current during thepower-transferring stage. Otherwise, there would be almost nocurrent through the inductor and the power cannot be deliveredto the load.

There are also 14 operational stages in a switching pe-riod of CCM2. The power-transferring stage and the primaryMOSFETs switching stages are similar to the CCM1 mode,while the main differences between CCM1 and CCM2 can beobserved in the secondary-side MOSFETs switching intervals.


As a result, the Stages 2–5 are analyzed in detail with the de-scription of the other stages omitted.

Stage 2 [θ1 , θ2]: Before is returns to zero, Ss1 turns OFF.The operation of the converter does not change, except that thecurrent through Ss1 changes to flow through the body diode. ipis still regulated by (2), while the phase-shift angle is expressedas

ϕ = θ2 − θ0 . (8)

Stage 3 [θ2 , θ3]: Before ip declines to zero, there is no cur-rent through the body diode of Ss2 , and the voltage of Ss2 stillequals the output voltage Vout . As a result, Ss2 turns ON withhard switching. Therefore, ZVS is lost for the secondary-sideswitches in CCM2. After turning ON of Ss2 , the current throughDo2 is shunted through Ss2 . The secondary-side current circu-lates through Ss1 and Ss2 freely, and the secondary winding ofthe transformer is shorted. Therefore, the output voltage is de-coupled from the transformer, and the load is supplied by onlythe output capacitor.

The primary current at this stage is also regulated by (4). Withonly half of the input voltage across the leakage inductor, thecurrent falling rate is smaller compared to CCM1 and it takeslonger time for ip to decline to zero. In addition, the power ofthe leakage inductor only returns to the input. As a result, lesspower is transferred to the load than CCM1 mode during theintervals prior to the power-transferring stage.

Stage 4 [θ3 , θ4]: As the primary current reverses, the parallelcapacitor of Ss1 is charged by the secondary-side current. And

β = θ4 − θ0 . (9)

Stage 5 [θ4 , θ5]: Most of the power is transferred during thisstage with ip regulated by (6). This stage is the same as Stage 5 ofCCM1 except that ip is zero at the beginning of this stage. Thatis, ip (θ4) = 0. As to the CCM 1 mode, ip is larger than zero atthe beginning of the power-transferring stage. Assuming G andVout are the same for both the modes, it is clear that less poweris transferred to the output terminal in CCM2 than in CCM1during the power-transferring stage. In addition, as explainedin Stage 3 of CCM2 mode, the converter transfers less powerbefore the power-transferring stage. As a whole, less power istransferred in the CCM2 mode than the CCM1 mode during awhole switching period, which will be illustrated further in thenext section.

When the converter works in the boost or balance modes, i.e.,G ≥ 1, ip keeps zero at the power-transferring stage and nopower is transferred to the load. Thus, the converter has to workin the buck mode if it enters the CCM2 mode.

However, the CCM2 mode is not recommended for the prac-tical applications. The secondary active switch turns ON beforethe primary current returns to zero. As a result, ZVS-on is lostfor the secondary-side switches. And it costs longer time thanCCM1 mode for the primary current to return to zero since theinductor voltage is only half of Vin . This results in extra powerlosses due to the secondary-side circulating current through Ss1and Ss2

Fig. 5. Operation waveforms of DCM mode.

C. DCM Mode

When the converter works in the boost mode, the primarycurrent may decline to zero at the power-transferring stage if theload is relatively light. This is the DCM mode and the operationwaveforms are displayed in Fig. 5.

Since the operations of DCM are similar to the CCM1 andCCM2 modes, the operation analysis of DCM is not provided.The primary current ip at Stage 1 [θ0 , θ1] and Stage 2 [θ1 , θ2]are also regulated by (4) and (6), respectively.

Since Ss1 has turned ON before is starts to flow throughit at θ0 in DCM, ZCS is achieved for Ss1 naturally. No extracondition has to be satisfied for ZVS-on of the secondary-sideswitches.

Different from CCM1 and CCM2, ip has returned to zero be-fore the primary switches commutate at θ0 , which means β = 0and ϕ ≥ β is always satisfied. As a result, the secondary sideis not powered by LLk after the primary switches transition atStage 3 and all of the power is transferred through the trans-former only at Stage 2.

As shown in Fig. 5, ip must keep decreasing linearly to zeroat Stage 2. Therefore, the converter can only work in the boostmode for DCM and G > 1, which means the converter cannotswitch directly between DCM and CCM2 where G < 1.


III. CONVERTER PERFORMANCE ANALYSIS

A. Output Characteristics

1) CCM1 Mode: According to the analysis of the CCM1mode in the previous section, the average primary current canbe obtained as

Iav =ip(θ0) · β

2π+

ip(ϕ) · (ϕ − β)2π

+[ip(ϕ)+ip(π)] · (π − ϕ)

2π.

(10)And the transferred power is expressed as

Pout =12VinIav . (11)

For simplification, the phase-shift angle ϕ is normalized asD and the output power Pout is normalized with the base powerPb , both of which are defined as

D = ϕ/π (12)

Pb =(NVout)2

2πfsLLk, (fs—switching frequency). (13)

From (1)–(7), (10), and (11), the output power can be obtainedas

PCCM1(G,D)

=πPb

[(1+G−2G2)+4D(1+G+G2)−2D2(2+2G+G2)

]

2G(2 + G)2 .

(14)

2) CCM2 Mode: If ϕ is smaller than β, the operation entersthe CCM2 mode. According to the analysis of the CCM2 modein the previous section, the gain G should be smaller than 1. Theaverage primary current can be expressed as

Iav =[ip(θ0)+ip(ϕ)] · ϕ

2π+

ip(ϕ) · (β − ϕ)2π

+ip(π) · (π − β)

2π.

(15)From (2), (4), (6)–(9), and (15), the output power can be

obtained as

PCCM2(G,D)

=πPb [(1 + 4G)(1 − G) + 2(−2+2G−G2)G2 ]

2G(2 − G)2 , (G < 1).

(16)

At the boundary between the CCM1 and CCM2 modes, ϕ =β. Applying the volt–second balance principle to the leakageinductor, the boundary condition can be obtained as

ϕb1 = (1 − G)π

2. (17)

For a given G smaller than 1, if ϕ becomes smaller thanϕb1 , ϕ would always be smaller than β, and the converter worksin the CCM2 mode; otherwise, ϕ is always larger than β, andthe converter enters the CCM1 mode.

3) DCM Mode: When ip becomes discontinuous, the con-verter goes into the DCM mode. As analyzed in the previoussection, the gain G should be larger than 1. And the average

TABLE IRELATIONSHIP BETWEEN GAIN AND OPERATION MODES

Fig. 6. Theoretical output characteristics.

primary current can be obtained as

Iav =ip(ϕ) · (ϕ + γ)

2π. (18)

From (10), (11), and (18), the output power can be expressedas

PDCM(G,D) =πD2Pb

2G(G − 1), (G > 1). (19)

As analyzed in the previous section, the converter can onlywork in the boost mode for DCM and G > 1, which meansthe converter cannot switch directly between DCM and CCM2where G < 1. The boundary between the DCM and CCM1modes is governed by

ϕb2 =G − 1

Gπ. (20)

For a given G larger than 1, if ϕ becomes smaller than ϕb2 ,the primary current would be discontinuous and the converterwould enter the DCM mode; otherwise, the converter will workin the CCM1 mode.

In summary, the relationship between the gain G and theoperation modes is illustrated in Table I. The converter canwork in the buck, balance, or boost modes in the CCM1 mode.And the gain can only be below and over 1 in CCM2 and DCM,respectively. As a result, the converter cannot switch betweenCCM2 and DCM directly.

From the expressions of the output power (14), (16), (19) andthe boundaries (17), (20), the normalized output power versusthe normalized phase-shift angle D is plotted in Fig. 6. For acurve with a certain gain, the transferred power in the CCM2and DCM modes is less than CCM1 mode, which agrees withthe analysis in previous section. In Section II, this phenomenonis explained on a perspective of circuit operation at every stagesrather than the equations or expressions, which is helpful tounderstand the characteristic of the converter. Therefore, CCM2and DCM are suitable for the light-load conditions. Additionally,


Fig. 7. Primary currents with different phase-shift angles in a half switchingperiod.

the areas of CCM2 and DCM modes are not adjacent, which isseparated by CCM1 area.

As shown in Fig. 6, if the gain is smaller than 1, the outputpower cannot be reduced to zero even when the phase-shiftangle is zero in CCM2. The secondary side works as a passiverectifier when the phase-shift angle is zero, while the primaryside works like a traditional non-PSFB converter with 0.5 dutycycle. Thus, the power can still be transferred to the load if theoutput voltage is relatively low. This issue can be solved easilyto make the proposed converter operate in the burst mode forthe light-load applications.

Another potential feature is that the converter can providethe same output power with two different phase-shift angles fora certain gain. To explain this phenomenon, the waveforms ofip in two scenarios during half of a switching period are illus-trated in Fig. 7. In the two situations, the input voltage and thevoltage gain are assumed to be the same. ip1 in the solid linehas a small phase-shift angle ϕ1 , while ip2 in the dotted linehas a larger phase-shift angle ϕ2 . Since most of the power isdelivered at the power-transferring stage, the power is approx-imately proportional to the size of the shadowed rectangulararea. If ϕ increases, ip at the power-transferring stage becomeslarger while the duration of the stage is shortened. As a result, asthe phase-shift angle changes, there are probably two situationswhere the shadowed areas are the same. That means there aretwo possible phase-shift angles for one certain output power.

In the practical applications, only the scenario with thesmaller phase-shift angle is recommended because the primaryand secondary currents are higher with the larger phase-shiftangle ϕ. Fig. 8 illustrates the simulation result waveforms with600-V input voltage, 96-V output voltage, and 1-kW rated out-put power. And the output power curves with three differentinput voltages 600, 720, and 800 V are plotted in Fig. 9. Asshown in Fig. 8, although the converter can provide 1 kW withtwo different phase-shift angles 0.38 and 0.86, the peak primarycurrent with the larger phase-shift angle is almost twice of thatwith the smaller phase-shift angle. Therefore, the left half whitearea in Fig. 9 with D less than 0.5 is recommended for thepractical operation.

B. Soft-Switching Condition

1) Primary Switches: The ZVS turn-off of the primaryswitches is obtained due to the parallel capacitors. The larger theparallel capacitors are, the less turn-off losses would be caused.In the steady-state operation of CCM1 and CCM2, ZVS turn-onis achieved for all the primary power MOSFETs, which reducesthe switching losses greatly. When Sp1 and Sp4 turn OFF, the

Fig. 8. Simulation waveforms of primary current, gating signals of Sp1 andSs2 with two phase-shift angles. (a) D = 0.36. (b) D = 0.86.

Fig. 9. Output characteristics of converter.

Fig. 10. Primary referred equivalent circuit when primary switches turn OFF.

inductor LLk charges Cp1 and Cp4 , and discharges Cp2 andCp3 . As a result, the ZVS turn-on for the switches Sp2 and Sp3can be realized once Cp2 and Cp3 are discharged completely.The condition for the ZVS turn-on of another pair of primaryswitches is the same.

Fig. 10 shows the primary referred equivalent circuit after apair of primary switches turn OFF. Cp is equal to one parallelcapacitance of the primary switches, assuming the four parallelcapacitors are all the same. That is Cp = Cp1 = Cp2 = Cp3 =Cp4 . And Vcp equals to 0.5Vin when the primary switches turnOFF. Since the output capacitor is relatively large, the output


voltage is assumed constant during this short duration. In thefollowing expressions, the primary current is ip (0) when Sp1and Sp4 turn OFF. And Vcp could be expressed as

Vcp = NVout − A · sin(ωt + δ) (21)

where

A =

√(NVout −

12Vin

)2

+ Z2 · ip(0)2 (22)

δ = arctan[NVout − 1

2 Vin

Z · ip(0)

](23)

ω =1

√LLk · Cp

(24)

Z =

√LLk

Cp. (25)

ZVS is achieved only if Vcp could reach –0.5Vin before theother pair of primary switches turn ON. As a result, the conditionfor ZVS in the CCM1 and CCM2 modes can be obtained as

12LLk · ip(0)2 >

V 2in · G · Cp

2. (26)

The condition is related to both the input and output voltages.That is because the leakage inductor energy is transferred to theload and the input terminal during this interval. So a higher out-put voltage consumes more energy and makes ZVS realizationmore difficult.

In addition, the dead time between the inner pair and theouter pair of primary switches should be set long enough toaccomplish ZVS operation, which can be expressed as

Td >1ω

(arcsin

NVout + 12 Vin

A− δ

). (27)

In the DCM mode, ZVS is not assured since the primarycurrent decreases to zero when the primary switches commu-tate, whereas, in case of a small magnetizing inductance of thetransformer, the magnetizing current could facilitate ZVS of theprimary switches. Unfortunately, a large magnetizing currentcould cause more conduction losses. Consequently, a tradeoffbetween the switching losses and conduction losses should bemade.

2) Secondary-Side Switches: As analyzed in Section II, theZVS of the secondary-side switches is achieved naturally inCCM1. No extra condition has to be satisfied for ZVS-on ofthe secondary-side switches. In CCM2, however, ZVS is lostbecause the secondary-side switch turns ON before is declinesto zero.

In DCM, the primary current is not continuous, which maylead to the loss of ZVS. At time θ1 in Fig. 5, Vds of Ss1 isregulated by

Vs1 =12

Vin

N[1 − cos(ω1 · t)] + is(ϕ) · Z1 · sin(ω1 · t) (28)

where

ω1 =1

√Cs · LLk/N 2

(29)

Z1 =√

LLk

N 2Cs(30)

where is(ϕ) is the current through the secondary winding of thetransformer when Ss1 turns OFF. Cs is the parallel capacitanceof the secondary-side switch. That is, Cs = Cs1 = Cs2 . In orderto achieve ZVS, Vs1 should reach Vout before Ss2 turns ON. Asshown in (28), if G < 2, the condition for ZVS is satisfiednaturally even without the help of is(ϕ). Because LLk and Cs1start resonating after Ss1 turns OFF, Vs1 can reach twice of thesecondary-side referred input voltage Vin /2N when is(ϕ) equalszero. In case that G > 2, is(ϕ) should be larger than zero tocharge Cs1 completely. The energy of LLk and the dead timeshould be regulated by

is(ϕ) >Vin

√G2 − 2G

2N · Z1, (G > 2) (31)

Td1 >1ω1

[arcsin

Vin(G − 1)√

4N 2 · Z21 · is(ϕ)2 + V 2

in

+ arctanVin

2N · Z1 · is(ϕ)

]. (32)

The magnetizing current has an influence on efficiency of theconverter because it may cause extra conduction losses in theprimary side. Fortunately, due to the small value of the mag-netizing current, the extra conduction losses are quite smallcompared with those generated by the normal primary current.Furthermore, the magnetizing current facilitates the ZVS op-eration of the primary switches, especially in the low-powerconditions. This raises the circuit conversion efficiency.

C. Voltage Stress Analysis

Once ignoring the voltage ripple on the input capacitors, thevoltage stress of the primary power switches is half of the inputvoltage, which means the low-voltage rated power devices withsuperior performance can be employed to reduce the conductionlosses.

Since there is no filter inductor in the secondary rectifiercircuit, the turn-off voltage across the secondary-side switchesis clamped by the output voltage, and the voltage spikes onthe switches are effectively suppressed. Therefore, the voltagestresses of the secondary-side switches including the MOSFETsand diodes are just the output voltage. The low-voltage ratedMOSFETs and diodes could be adopted as the secondary-sidepower switches, which help the converter accomplish betterperformance.

IV. DESIGN GUIDELINES

A 1-kW 100-kHz prototype is established to be used as anexample to give a clear parameter design procedure. In the testedprototype, the input voltage varies from 600 to 800 V and theoutput voltage is 96 V for the battery charging system.

A. Transformer Turns Ratio

The turns ratio is the key parameter because it determinesthe converter operation mode. The input voltage for the balance


mode should be a moderate one to minimize the switch currentstress, which is selected as 720 V in this test bench. Accordingto (1), the turns ratio can be designed.

B. Leakage Inductor

Based on (1), (14), (16), and (19), the practical output char-acteristic curve can be plotted in Fig. 9. The rated output poweris denoted as a horizontal line which could be moved verticallyin Fig. 9. To guarantee that the rated power can be transferredover the full range of input voltage, the rated power line shouldhave crossing points with every output characteristic curve, es-pecially with the lowest input voltage 600 V curve. Also, theposition of the rated power line needs to be carefully chosen inorder to have a proper working range of the phase-shift angleϕ. Then, the percentage of Pb that the rated power is can beobtained on the y-axis of Fig. 9. And LLk can be calculated as

LLk =(NVout)2ε

2πfsPr(33)

where Pr and ε are the rated power and the percentage of Pb

that the rated power is, respectively.

C. Dead Time

The dead time of the primary switches can be calculated from(23) and (27), while the dead time of the secondary switches canbe obtained through (32).

D. Control Loop

The output voltage and transferred power are regulated byonly directly varying the phase-shift angle ϕ, which is generatedthrough the digital signal processor according to the outputcharacteristic curve shown in Fig. 6.

And the classical voltage feedback loop is adopted to regulatethe output voltage in this experimental prototype. The differencebetween the voltage reference and the sampled output voltagegoes through the PI compensator to the phase-shift generationblock. Due to the updated phase-shift angle, the SSPS converterchanges the output voltage. The PI compensator and phase-shiftgeneration is completed by TI TMS320F2808. Actually, otheradvanced feedback control strategies can be also employed toimprove the steady-state and dynamic response of the proposedconverter [23].

V. EXPERIMENTAL VERIFICATIONS

A 1-kW 100-kHz prototype is established to verify the the-oretical analysis. The specifications are listed in Table II. Theinput voltage is 600–800 V, and the output voltage is 96 V.The transformer turns ratio is 15:4, which means the converterworks in the balance mode at the input voltage of 720 V ide-ally. IRFP460 and IRFP4668 are adopted as the primary andsecondary switches, respectively. 30CPQ150 is selected as thesecondary-side diodes. And the leakage inductor is designed tobe 50 μH. The parallel capacitors of the primary and secondaryswitches are 470 pF and 1 nF, respectively. And a 4.7-μF CBBcapacitor is selected as the primary block capacitor.

TABLE IIUTILIZED COMPONENTS AND PARAMETERS OF PROTOTYPE

Fig. 11. Switching waveforms of primary-side switch.

Fig. 12. Switching waveforms of secondary-side switch.

Figs. 11–13 display the waveforms of the primary, thesecondary-side switch, and the secondary-side diode with Vin =800 V, Vout = 96 V and Pout = 1 kW, respectively. With theparameters, the converter works in CCM1 mode with G < 1.

As shown in Figs. 11 and 12, ZVS is achieved for the primary-side active switch and the secondary-side switch. Since allthe primary switches work in the same pattern and both thesecondary-side switches work symmetrically, ZVS is accom-plished for all the primary and secondary active switches. Anddue to the soft switching, there are no voltage spikes on theprimary switch. It can be seen that the voltage stress of the pri-mary switches is about 400 V, which is half of the input voltage.


Fig. 13. Switching waveforms of secondary-side diode.

As a result, the low-voltage rated power MOSFETs with highperformance can be employed to reduce the conduction losses.

It can be seen from Figs. 12 and 13 that the voltage stressesof the secondary-side active switches and diodes are clampedto the output voltage 96 V. And the voltage spikes on boththe secondary-side MOSFETs and diodes are effectively sup-pressed, since the output filter inductor is removed. Furthermore,there is no reverse recovery problem for the diodes, since thecurrent falling rate of the output diode is controlled by the leak-age inductance.

The three pairs of vp and ip waveforms in Fig. 14 are mea-sured under the condition of 1-kW output power and differentinput voltages. It can be seen that the converter works in theCCM1 mode at all of the three situations. The primary cur-rent increases, remains constant, and declines linearly at thepower-transferring stage in the buck, balance, and boost modes,respectively. Fig. 14(b) demonstrates the balance mode withVin = 730 V, Vout = 96 V, and N = 15/4. The input-side (Vin /2)and output-side (NVout) voltages of the leakage inductor are thesame, considering the forward voltage of diodes and MOSFETs.So the primary current keeps constant at the power-transferringstage, which is in compliance with the theoretical analysis inSection II.

The waveforms of vp and ip in Fig. 15 are measured under thecondition of 400-W output power and 600-V input voltage. Theprimary current decreases rapidly during the power-transferringstage with gain G > 1, which agrees with the above analysis.However, the primary current does not decrease to zero and be-gins increasing again after the power-transferring stage, whichis not completely compatible with the analysis in Section II. Be-cause the transformer magnetizing inductance is not infinitelylarge, the magnetizing current cannot be neglected. The out-put and input voltages are addressed on the transformer duringand after the power-transferring stage, respectively. As a re-sult, the magnetizing current begins increasing from zero sincethe power-transferring stage, and the primary current does notdecrease to zero and begins increasing, as shown in Fig. 15.

As the output power varies from zero to the rated, the mea-sured efficiency curves with respect to different input voltagesare plotted in Fig. 16. The peak efficiency is over 96%, andthe efficiency of 94% is achieved in a wide power range dueto ZVS operation in a wide voltage range, low-voltage ratehigh-performance power device utilization and small circulat-

Fig. 14. Voltage vp and current ip waveforms in (a) buck mode with Vin =800 V, (b) balance mode with Vin = 730 V, and (c) boost mode with Vin =600 V.

Fig. 15. Voltage vp and current ip waveforms in DCM mode.

ing losses. It is demonstrated that the converter is an excellentcandidate for the high input voltage applications.

In order to clearly illustrate the efficiency performance of theproposed converter, the typical primary phase-shift-controlledthree-level converter is used as an example and compared. Thequalitative loss distributions in both converters are summarized


Fig. 16. Measured efficiency.

TABLE IIILOSS DISTRIBUTION COMPARISON BETWEEN THREE-LEVEL PRIMARY

PHASE-SHIFT CONVERTER AND PROPOSED SSPS CONVERTER

in Table III. For the primary-side losses, the proposed converterhas lower conduction losses because it has lower freewheelingcurrent and there is no extra primary clamping diodes. For thesecondary-side losses, the reverse-recovery losses for the outputdiodes that exist in the conventional phase-shift converters areminimized due to the SSPS scheme. Furthermore, the outputdiodes in the conventional primary phase-shift-controlled con-verter suffer higher voltage stress compared with the proposedsecondary-side phase-shift converter, which leads to larger con-duction losses for the output diodes [17]. As a result, the pro-posed converter has higher efficiency than the conventionalthree-level converter. And it is also proved that the proposedconverter has some superior performance from the data in [17].

The operation principle of the proposed converter is quitesimilar to that of the introduced circuit in [19]. However, in the800-V or higher input voltage applications, due to the full-bridgeconfiguration in [19], insulated-gate bipolar transistors shouldbe employed to sustain the high bus voltage, which results inlarge conduction losses. Furthermore, the switching frequencyis limited to impact the power density. This means a large andcostly magnetic core should be selected for the transformer. Inconclusion, in the high input voltage systems, the conversion

efficiency and circuit cost of the proposed converter are a littlecompetitive than those of the topology introduced in [19].

VI. CONCLUSION

In this paper, a secondary-side phase-shift-controlled ZVSdc/dc converter for high-efficiency, wide conversion range andhigh input voltage applications has been proposed and ana-lyzed. The improved three-level configuration in the primaryside halves the primary power devices, which makes it possibleto employ low-voltage rated power switches for high input volt-age applications. Furthermore, the ZVS can be achieved for allthe power devices including the primary and secondary switchesto effectively reduce the switching losses. Moreover, the circu-lating current is effectively suppressed due to the secondary-sidephase-shift control scheme, which largely improves the effi-ciency of the converter. And the overshoots on the secondary-side devices are effectively suppressed by clamping the rectifierto the output voltage. In addition, a wide conversion range can beachieved since the converter can work in three modes includingthe buck, balance, and boost modes. The circuit operation andcharacteristics of the proposed converter is analyzed and sim-ulated. Experimental results of an 800-V-96-V/1-kW prototypehave verified the feasibility and effectiveness of the advantagesof the proposed converter.

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Wuhua Li (M’09) received the B.Sc. and Ph.D. de-grees in applied power electronics and electrical engi-neering from Zhejiang University, Hangzhou, China,in 2002 and 2008, respectively.

From September 2004 to March 2005, he wasan Intern, and from January 2007 to June 2008, aResearch Assistant in GE Global Research Center,Shanghai, China. From July 2008 to April 2010,he was with the College of Electrical Engineering,Zhejiang University, as a Postdoctoral Fellow. In May2010, he became a Faculty Member at Zhejiang Uni-

versity as a Lecturer and promoted to an Associate Professor in December 2010.From July 2010 to September 2011, he was a Ryerson University PostdoctoralFellow with the Department of Electrical and Computer Engineering, RyersonUniversity, Toronto, ON, Canada. He has published more than 70 technicalpapers and holds more than 20 issued/pending patents. His research interestsinclude high-efficiency power converters and renewable energy power conver-sion system.

Sheng Zong was born in Jilin, China, in 1987. Hereceived the B.Sc. degree from Chu Kochen HonorsCollege, Zhejiang University, Hangzhou, China, in2010, where he is currently working toward the Ph.D.degree in the College of Electrical Engineering.

His research interests include paralleled resonantand phase-shift converters, grid-connected inverters,and LED drivers.

Fangrui Liu received the B.Eng. degree in electricalengineering from the Huazhong University of Sci-ence and Technology, Wuhan, China, in 2002, andthe Ph.D. degree from Nanyang Technological Uni-versity, Singapore, in 2006.

He joined the College of Electrical and ElectronicEngineering, Huazhong University of Science andTechnology in September 2006 where he has beena Lecturer since September 2008. He is currently aPostdoctoral Fellow with the Department of Electri-cal and Computer Engineering, Ryerson University,

Toronto, ON, Canada. His research includes power converters, ac motor drives,and renewable energy resources.

Huan Yang (M’09) received the B.Sc. and Ph.D.degrees in electrical engineering and its automationand electrical engineering from Zhejiang University,Hangzhou, China, in 2003 and 2008, respectively.

From January 2009 to March 2011, he joined theCollege of Electrical Engineering, Zhejiang Univer-sity, as a Postdoctoral Fellow. In April 2011, he be-came a Faculty Member at Zhejiang University asa Research Associate. His research interests includemotor drives and multifunctional grid-connected con-verter in microgirds.

Xiangning He (M’95–SM’96–F’10) received theB.Sc. and M.Sc. degrees from the Nanjing Universityof Aeronautical and Astronautical, Nanjing, China,in 1982 and 1985, respectively, and the Ph.D. degreefrom Zhejiang University, Hangzhou, China, in 1989.

From 1985 to 1986, he was an Assistant Engineerat the 608 Institute of Aeronautical Industrial GeneralCompany, Zhuzhou, China. From 1989 to 1991, hewas a Lecturer at Zhejiang University. In 1991, he ob-tained a Fellowship from the Royal Society of U.K.and conducted research in the Department of Com-

puting and Electrical Engineering, Heriot-Watt University, Edinburgh, U.K.,as a Postdoctoral Research Fellow for two years. In 1994, he joined ZhejiangUniversity as an Associate Professor, where since 1996, he has been a Full Pro-fessor in the College of Electrical Engineering. He was the Director of the PowerElectronics Research Institute and the Head of the Department of Applied Elec-tronics, and is currently the Vice Dean of the College of Electrical Engineering,Zhejiang University. His research interests include power electronics and theirindustrial applications. He is the author or coauthor of more than 280 papersand one book Theory and Applications of Multi-level Converters. He holds 22patents.

Dr. He received the 1989 Excellent Ph.D. Graduate Award, the 1995 ElitePrize Excellence Award, the 1996 Outstanding Young Staff Member Award, andthe 2006 Excellent Staff Award from Zhejiang University for his teaching andresearch contributions. He received seven Scientific and Technological Achieve-ments Awards from Zhejiang Provincial Government and the State EducationalMinistry of China in 1998, 2002, 2009, and 2011 respectively, and six ExcellentPaper Awards. He is a Fellow of the Institution of Engineering and Technology(formerly IEE), U.K.

Bin Wu (S’89–M’92–SM’99-F’08) received thePh.D. degree in electrical and computer engineeringfrom the University of Toronto, Toronto, ON, Canada,in 1993.

After being with Rockwell Automation Canadaas a Senior Engineer, he joined Ryerson Univer-sity, Toronto, ON, where he is currently a Professorand NSERC/Rockwell Industrial Research Chair inPower Electronics and Electric Drives. He has pub-lished more than 200 technical papers, authored twoWiley-IEEE Press books, and holds more than 20

issued/pending patents in the area of power conversion, advanced controls,adjustable-speed drives, and renewable energy systems.

Dr. Wu received the Gold Medal of the Governor General of Canada, thePremier’s Research Excellence Award, the Ryerson Distinguished ScholarAward, the Ryerson Research Chair Award, and the NSERC Synergy Awardfor Innovation. He is a Fellow of the Engineering Institute of Canada and theCanadian Academy of Engineering. He is an Associate Editor of the IEEETRANSACTIONS ON POWER ELECTRONICS and IEEE CANADIAN REVIEW.

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