modern vlsi design 4e: chapter 5 copyright 2008 wayne wolf topics n performance analysis of...
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Topics
Performance analysis of sequential machines.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Unbalanced delays
Logic with unbalanced delays leads to inefficient use of logic:
long clock periodshort clock period
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Signal skew
Machine data signals must obey setup and hold times—avoid signal skew.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock skew
Clock must arrive at all memory elements in time to load data.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Qualified clocks and skew
Logic in the clocking path introduces delay. Delay can cause clock to arrive at latches at
different times, violating clocking assumptions.
When designing qualification logic:– minimize and check skew;– sharpen clock edge.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Qualification skew example
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock period
For each phase, phase period must be longer than sum of:– combinational delay;– latch propagation delay.
Phase period depends on longest path.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Unbalanced delays
Logic with unbalanced delays leads to inefficient use of logic:
long clock periodshort clock period
![Page 9: Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf Topics n Performance analysis of sequential machines](https://reader036.vdocuments.mx/reader036/viewer/2022062515/56649c875503460f9493f207/html5/thumbnails/9.jpg)
Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Flip-flop-based system performance analysis
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Flip-flop-based system model
Clock signal is perfect (no rise/fall), period P. Clock event on rising edge. Setup time s.
– Time from arrival of combinational logic event to clock event.
Propagation time p.– Time for value to go from flip-flop input to output.
Worst-case combinational delay C.– Time from output of flip-flop to input.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock parameters
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock period constraint
P >= C + s + p. s p C
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock with rise/fall
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Rise/fall clock period constraint
P >= C + s + p + tr. s p Ctr
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Min-max delays
Delays may vary:– Manufacturing
variations.– Temperature variations.
Min/max delays compound over paths.– Delays within a chip
are correlated.
t
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Latch system clock period
For each phase, phase period must be longer than sum of:– combinational delay;– latch propagation delay.
Phase period depends on longest path.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Latch-based system model
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Two-phase timing parameters
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock period constraint
Total clock period (both phases):– P >= C1 + C2 + 2s + 2p.
Each phase must meet timing for its own latch.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Latch-based system model
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Advanced performance analysis
Latch-based systems always have some idle logic.
Can increase performance by blurring phase boundaries. Results in cycle time closer to average of phases.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Example with unbalanced phases
One phase is much longer than the other:
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Spreading out a phase
Compute only part of long paths in one phase:
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Spreading out a phase, cont’d.
Use other phase for end of long logic block and all of short logic block:
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Problems
Hard to debug—can’t stop the system. Hard to initialize system state. More sensitive to process variations.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Timing and glitches in FSMs
If inputs don’t change, can outputs glitch?
DQ
logicinput output
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Skew
Skew: relative delay between events. Signal skew: most important for
asynchronous, timing-dependent logic. Clock skew: can harm any sequential
system.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Signal skew
Machine data signals must obey setup and hold times—avoid signal skew.
![Page 29: Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf Topics n Performance analysis of sequential machines](https://reader036.vdocuments.mx/reader036/viewer/2022062515/56649c875503460f9493f207/html5/thumbnails/29.jpg)
Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Signal skew example
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock skew
Clock must arrive at all memory elements in time to load data.
![Page 31: Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf Topics n Performance analysis of sequential machines](https://reader036.vdocuments.mx/reader036/viewer/2022062515/56649c875503460f9493f207/html5/thumbnails/31.jpg)
Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock skew example
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock skew in system
D Q
D Q
logic
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock skew and qualified clocks
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock skew analysis model
s12 = 1 – 2s21 = 2 – 1
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Skew and clock period
Assume that each flip-flop operates instantaneously:– T >= 2 + 12
If clock arrives at FF2 after FF1, then we have more time to compute.
Given clock period, determine allowable skew:– s12 >= T + 2
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Timing through logic
As skew increases, we have less time to get the signal through the logic.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock distribution
Often one of the hardest problems in clock design.– Fast edges.
– Minimum skew.
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Clock skew example
10 ps 10 ps
20 ps 20 ps
30 ps 30 ps
D Q D QD Q
D Q
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Retiming
Retiming moves registers through combinational logic:
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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf
Retiming properties
Retiming changes encoding of values in registers, but proper values can be reconstructed with combinational logic.
Retiming may increase number of registers required.
Retiming must preserve number of registers around a cycle—may not be possible with reconvergent fanout.