modeling of total jitter using efficient link analysis
TRANSCRIPT
The Pennsylvania State University
The Graduate School
School of Science, Engineering and Technology
AN EFFICIENT IMPLEMENTATION OF LINK ANALYSIS ALGORITHM IN HIGH-SPEED INTERFACES FOR NRZ IN THE PRESENCE OF CMOS
NON-LINEARITY IN RECEIVERS
A Thesis in
Electrical Engineering
by
Tapan L. Khilnani
© 2015 Tapan Khilnani
Submitted in Partial Fulfillment
of the Requirements
for the Degree of
Master of Science
December 2015
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The thesis of Tapan Khilnani was reviewed and approved* by the following:
Aldo W. Morales
Professor of Electrical Engineering
Thesis Co-Adviser
Sedig S. Agili
Professor of Electrical Engineering
Program Coordinator, Master of Science in Electrical Engineering
Thesis Co-Adviser
Jeremy Blum
Associate Professor of Computer Science
*Signatures are on file in the Graduate School
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ABSTRACT
Today's communication systems have achieved data rates in the range of multi-
gigabits per second (Gb/s). With such an incessant escalation in data rates, design
engineers are working hard to maintain the performance of these high-speed systems. At
higher data rates, it is imperative to preserve the system performance by estimating the
impairments of signal. These impairments are mainly due to the frequency dependent
nature of transmitters, channels, and receivers in a communication system. Jitter plays a
major role in contributing to these impairments thereby, degrading the performance of
communication systems. As the speed of data transfer increases, the effects of jitter
become more critical with tighter jitter budgets. In order to reduce the effects of jitter in
a system, it is crucial to understand its causes and characteristics.
In this thesis, the fundamentals of jitter along with its components and sources are
reviewed. It illustrates several parameters relevant to the analysis of jitter and its types.
This is followed by an overview of some traditional techniques used for jitter measurement
and modeling such as the sampling oscilloscopes, bit error ratio tester (BERT), time interval
analyzer (TIA), and some state-of-the-art algorithms such as the Tail fit, Peak distortion
analysis (PDA), and direct computation of probabilities algorithms. These techniques are
well-elucidated with examples as well as their pros and cons.
This thesis presents an implementation of the most recent link statistical signaling
technique for modeling jitter, in the presence of CMOS non-linearity observed in receivers.
This algorithm is based on a superposition technique using HashMaps for determining the
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accurate logic level of digital data bits, in the presence of jitter. This approach deals with
the overall effect of unwanted alterations observed on a data bit positioned at the cursor,
contributed by neighboring bits in a digital data stream. In this technique, HashMaps are
employed to sustain the computational intricacies involved in this algorithm. The time
required for the execution is also reduced, making it an efficient technique for this
implementation. The execution time of this technique is reduced by more than a third as
compared to a prior implementation of the Link Analysis algorithm called ‘Bin
Multiplication’. This technique is implemented for non-return to zero (NRZ), which is the
most preferred signaling scheme in high-speed digital systems.
Most of the jitter modeling techniques are based on the assumption of linear
behavior of components in communication systems. However, in reality, receivers exhibit
non-linear traits and this aspect substantially detriments the performance of a system.
Thus, the statistical analysis for jitter measurement in terms of bit error rate (BER), is
extended to account for the receiver’s non-linearity. In this research, the voltage
characteristic of complementary metal-oxide semiconductor (CMOS) receivers is
nominated for modeling the non-linearity in terms of hyperbolic tangent. The total jitter
probability density function (PDF) acquired for a linear system is obtained based on this
non-linearity. This precise PDF adjustment for non-linearity can be used to estimate the bit
error rate (BER) values.
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TABLE OF CONTENTS
LIST OF FIGURES ..................................................................................................................... vii
LIST OF ABBREVIATIONS ........................................................................................................... x
ACKNOWLEDGEMENTS ......................................................................................................... xiii
CHAPTER 1. INTRODUCTION .................................................................................................... 1
Fundamentals of Signal Integrity ......................................................................................... 1
Research Motivation ............................................................................................................ 4
Core Idea ............................................................................................................................... 5
Outline................................................................................................................................... 7
CHAPTER 2. LITERATURE REVIEW ............................................................................................ 9
Key Performance Metrics ................................................................................................... 10
Data rate (DR) ................................................................................................................. 10
Unit Interval (UI) ............................................................................................................. 11
Signal to noise ratio (SNR).............................................................................................. 11
Bit Error Ratio (BER) ....................................................................................................... 12
Eye Diagram .................................................................................................................... 12
Bathtub Curve ................................................................................................................. 14
Jitter Budget and Jitter Tolerance ................................................................................. 15
Phase Noise .................................................................................................................... 15
Phase Jitter ..................................................................................................................... 17
Wander ........................................................................................................................... 19
Convolution .................................................................................................................... 19
Jitter Probability Density Function (PDF) ...................................................................... 20
Linear Time Invariance (LTI) ........................................................................................... 21
Dual-Dirac Model ........................................................................................................... 22
Need for Jitter Measurement ............................................................................................ 23
Output Jitter ................................................................................................................... 24
Jitter Tolerance ............................................................................................................... 24
Jitter Transfer ................................................................................................................. 25
Types of Jitter Measurements ........................................................................................... 27
Period Jitter (JPER) ........................................................................................................ 27
Cycle-to-Cycle Jitter (JCC) .............................................................................................. 28
Time Interval Error (TIE) ................................................................................................. 29
Sources of Jitter .................................................................................................................. 30
Intrinsic Sources ............................................................................................................. 31
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Non-Intrinsic Sources ..................................................................................................... 33
Components of Jitter .......................................................................................................... 34
Random Jitter (RJ) .......................................................................................................... 35
Deterministic Jitter (DJ) .................................................................................................. 38
Total Jitter (TJ) ................................................................................................................ 43
Four-Level Pulse Amplitude Modulation (PAM-4) ............................................................ 44
Receiver’s Non-Linearity .................................................................................................... 48
CMOS Receivers ............................................................................................................. 50
CHAPTER 3. EXISTING TECHNIQUES FOR ESTIMATING JITTER ............................................. 52
Traditional Techniques ....................................................................................................... 55
Real-time Oscilloscope ................................................................................................... 55
Time Interval Analyzers (TIA) ......................................................................................... 55
Bit Error Ratio Tester (BERT) .......................................................................................... 56
Recent Techniques ............................................................................................................. 59
Tail fit Algorithm ............................................................................................................. 59
Peak Distortion Analysis (PDA) ...................................................................................... 60
CHAPTER 4. EFFICIENT IMPLEMENTATION OF LINK ANALYSIS ............................................ 63
CHAPTER 5. HASHMAP METHODOLOGY ............................................................................... 67
Inter-Symbol Interference (ISI) Recursive Convolution .................................................... 68
Transition PDF (TPDF) ......................................................................................................... 74
Mean – Convolve Algorithm .............................................................................................. 79
Mean of TPDFs ............................................................................................................... 81
Convolution of TPDFs ..................................................................................................... 83
Detailed Comparison with Bin Multiplication Approach [13], [17] .................................. 88
Non-Linearity in CMOS Receivers ...................................................................................... 90
Implementation of NRZ .................................................................................................. 93
Implementation of PAM-4 ............................................................................................. 95
Consolidation of Receiver PDFs with CMOS Non-Linearity .............................................. 97
CHAPTER 6. CONCLUSION AND FUTURE SCOPE .................................................................101
References ............................................................................................................................104
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LIST OF FIGURES
Figure 1-1. Block Diagram of a standard serial link [4] 2
Figure 2-1. Unit Interval (UI) for an Ideal NRZ Waveform 11
Figure 2-2. Eye Diagram [25] 13
Figure 2-3. Sample Eye Diagram of a Data Signal 14
Figure 2-4. Bathtub Curve [78] 15
Figure 2-5. Phase Noise Representation [23] 16
Figure 2-6. Phase Jitter Representation [23] 18
Figure 2-7. Frequency Scale for Wander and Jitter 19
Figure 2-8. Convolution of RJ and Dual-Dirac DJ = Dual-Dirac Representation for TJ 22
Figure 2-9. Jitter Measurement categories for a simple Transmitter and Receiver System [29] 23
Figure 2-10: Functional blocks in a Phase Locked Loop (PLL) Circuit [32] 26
Figure 2-11. Types of Jitter Measurements [35] 27
Figure 2-12. Measurement of Period Jitter [34] 28
Figure 2-13. Measurement of Cycle-to-Cycle Jitter [77] 29
Figure 2-14. Measurement of TIE [80] 30
Figure 2-15. Various Types of Jitter [81] 35
Figure 2-16. Gaussian distribution representing Random Jitter PDF [44] 38
Figure 2-17. Deterministic Jitter PDF [44] 39
Figure 2-18. Periodic Jitter PDF [44] 40
Figure 2-19. PDF for Duty-Cycle Distortion [44] 41
Figure 2-20. Inter-Symbol Interference PDF [44] 42
Figure 2-21. Total Jitter (TJ) PDF [44] 44
Figure 2-22. Sequence of data bits for NRZ and PAM-4 signaling schemes [73] 45
Figure 2.23. Eye diagram for NRZ and PAM-4 signaling schemes [47] 46
Figure 2-24. CMOS Voltage Transfer Characteristic and noise margin [3] 51
Figure 3-1. Eye Diagram and its significance [57] 54
Figure 3-2. Bathtub Curve in reference to DJ, RJ and Eye Diagram [58] 58
Figure 5-1. Statistical Signaling Analysis Flowchart [7] 68
Figure 5-2. Simulink diagram for generation of ISI pulse response [11] 69
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Figure 5-3. ISI cursors and Main cursor 70
Figure 5-4. Recursive Convolutions of ISI PDFs 71
Figure 5-5. ISI Cursor PDF 1 72
Figure 5-6. ISI Cursor 2 PDF 72
Figure 5-7. PDF of 1st Cursor * 2nd Cursor 72
Figure 5-8. ISI Cursor PDF 3 72
Figure 5-9. PDF of 1st Cursor * 2nd Cursor * 3rd Cursor 73
Figure 5-10. ISI PDF Cursor 4 73
Figure 5-11. PDF of 1st Cursor * 2nd Cursor * 3rd Cursor * 4th Cursor 73
Figure 5-12. Flow chart of TX Jitter and Channel ISI Combining to Form RX Distribution [7] 74
Figure 5-13. Jitter PDF * ISI PDF = TPDF [7] 75
Figure 5-14. UI-based analysis - ISI and TX jitter computation to form Transition PDF [7] 75
Figure 5-15. Jittery Transitions within Each UI [30] 75
Figure 5-17. Transitions between Same Logic Levels 76
Figure 5-16. Transitions between Different Logic Levels 76
Figure 5-18. TX Jitter PDF for 0 - 1 and 1 - 0 Transitions 77
Figure 5-19. TX Jitter PDF for 0 - 0 and 1 - 1 Transitions 77
Figure 5-20. ISI PDF for Segment #2 and Bit level - 0 77
Figure 5-21. TPDF for Segment #2, Transition level - 00 78
Figure 5-22. TPDF for Segment #2, Transition level - 01 78
Figure 5-23. Mean - Convolve Algorithm for RX PDFs [7], [30] 79
Figure 5-24. TPDF of A 82
Figure 5-25. TPDF of B 82
Figure 5-26. Intermediate PDF 82
Figure 5-27. RX PDF for Bit-0 (Blue) and Bit-1 (Red) 87
Figure 5-28. Block Diagram of Non-linearity function 90
Figure 5-29. CMOS receiver’s input–output characteristics 92
Figure 5-30. Non-Linear PDF Modification |dx/dy| 93
Figure 5-31. Simulink Diagram for modeling Non-linearity in NRZ Signaling Scheme 94
Figure 5-32. Data points for NRZ with Non-linearity (Blue) 95
Figure 5-33. PDF for NRZ with Non-linearity correction (Blue) 95
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Figure 5-34. Simulink Diagram for modeling Non-linearity in PAM-4 Signaling Scheme 96
Figure 5-35. Data points for PAM-4 with Non-linearity (Blue) 97
Figure 5-36. PDF for PAM-4 with Non-linearity correction (Blue) 97
Figure 5-37. RX PDF for Bit-0 in the presence of non-linearity correction 99
Figure 5-38. RX PDF for Bit-1 in the presence of Non-linearity correction 99
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LIST OF ABBREVIATIONS
Gb/s – Gigabits per second
BERT – Bit error ratio tester
TIA – Time interval analyzer
PDA – Peak Distortion Analysis
CMOS – Complementary metal-oxide semiconductor
NRZ – Non-return to zero
PAM-4 – 4-level pulse amplitude modulation
PCB – Printed circuit board
I/O – Input/output
BER – Bit error rate
PDF – Probability density function
ISI – Inter-symbol interference
DR – Data rate
UI – Unit interval
SNR – Signal to noise ratio
TIE – Time interval analyzer
FFT – Fast Fourier transform
PDF – Probability density function
LTI – Linear time-invariant
DUT – Device under test
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Kb/s – Kilobits per second
ITU-T - Telecommunication standardization sector of the International
Telecommunications Union
SONET – Synchronous optical network
SDH - Synchronous digital hierarchy
RJ – Random jitter
DJ – Deterministic jitter
CDF – Cumulative distribution function
TJ – Total jitter
TPDF – Transition probability distribution function
I/O – Input/output
Mb/s – Megabits per second
b/s – Bits per second
RMS – Root mean square
PSD – Power spectral density
CDR – Clock data recovery
PLL - Phase-locked loop
VCO – Voltage controlled oscillator
DCD – Duty cycle distortion
EMI – Electromagnetic interference
PJ – Periodic jitter
SJ- Sinusoidal jitter
DDJ – Data deterministic jitter
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BUJ – Bounded uncorrelated jitter
ps - Picosecond
BW – Bandwidth
IC – Integrated circuit
AFE – Analog front end
AWGN – Additive white Gaussian noise
ADC – Analog to digital converter
DSL - Digital subscriber line
DC – Direct current
AC – Alternating current
TX – Transmitter
RX - Receiver
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ACKNOWLEDGEMENTS
I would like to take this opportunity to thank my advisers, Dr. Aldo Morales and Dr.
Sedig Agili, for granting me this opportunity to work under their supervision. My gurus, Dr.
Morales and Dr. Agili are entirely responsible for bringing out the best in me. Right from
assisting me with the selection of this thesis topic to rendering valuable feedback, their
extensive guidance through the course of this research and implementation has been
extremely crucial for this work.
I am fortunate to have had the opportunity to register for the Probability, Random
Variables and Stochastic Processes course taught by Dr. Morales wherein I was introduced
to this research topic. Not only did he patiently answer all my silly questions, but also
significantly bolstered my MATLAB and Simulink skills, from scratch.
Dr. Agili constantly raised his expectations in order to help me push myself forward.
However, he knew exactly when to pull the strings with his words of encouragement. He
always said, “I believe in your abilities and I know you can do it”. I am proud to be their
student, and hope that they will be proud of me some day as well.
I would like to thank Dr. Jeremy Blum for granting me the opportunity to audit his
class CMPSC 461: Data Structures and Algorithms, despite having a full-class of students. I
owe a lot for strengthening my coding skills during his weekly meetings scheduled for the
Penn State Harrisburg Programming team. A special word of thanks to the entire staff of
School of Science, Engineering and Technology, especially the Director Dr. Rafic Bachnak
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and Administrative Support Coordinator Lori Ricard for keeping me focused and making
sure I was not overburdening myself.
The Director of Continuing Education at Penn State Harrisburg and the supervisor
of my campus job as a Virtual Learning Network (VLN) technician, Erin Shannon, made it a
point to always inquire on the progress of my thesis.
I’d like to thank the Chancellor of Penn State Harrisburg, Dr. Mukund Kulkarni, for
being so encouraging and welcoming. He always ensured that I was relishing my time at
Penn State Harrisburg.
A sincere word of thanks to Semontee Mitra, working at the Russell E. Horn Sr.
learning center at Penn State Harrisburg, for enhancing my writing skills by meticulously
proofreading my work and providing meaningful feedback.
A kind note of appreciation to the International advisors of Penn State Harrisburg,
Donna Howard, Anna Marshall, and Ana Patricia, for being so caring and always being there
for me. Much appreciation to my dear friends, Andrew Zern, Darshan Karnawat, Ramy Zaki,
and Justin Lipuma for consistently persuading me, especially during rough days, and
helping me make it to the lab on time in spite of inclement weather conditions.
I appreciate my friend Disha Madhrani for taking active interest in my research by
being a great listener and contributing significantly with her novel ideas and honest
feedback.
My uncle, Dr. Vinod Khilnani has been an inspiration throughout, his concern and
advice has cumulatively helped me make it to this point in my academic career.
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I’d like to convey my love and appreciation to my little brother, Mukul Khilnani, for
being by my side through thick and thin. Although he never shows it, he is most concerned
about my happenings. His support and endless prayers over the course of my studies have
played a crucial role in my accomplishments.
Finally, my Mom, Dr. Veena Khilnani and Dad, Lalit Khilnani deserve my utmost
gratitude for their tireless prayers and support in my endeavors. This thesis, for all its
worth, is dedicated to them.
1
CHAPTER 1. INTRODUCTION
Fundamentals of Signal Integrity
Moore’s law states, “The number of transistors on a chip doubles every two years”
[1]. As a widely known projection, this statement has constantly raised the performance
bar of data bandwidth in interconnect systems. Therefore, digital devices have become
more and more computationally powerful with every new generation of semiconductor
process. Along with the increase in functionalities, there has also been an incredible
increase in performance [2]. The performance of a communication system is defined as
the ability of its receiver to accurately interpret signals being sent by the transmitter. In
order to achieve this increased performance, it is essential to scale the speed of operation
as well.
With data rates approaching multi-gigabits per second (Gb/s), it is extremely
challenging to maintain signal integrity of the system. This is mainly due to the inaccuracy
introduced in determining the system’s behavior, at higher data rates. Therefore, these
modern high-speed digital designs require extensive signal integrity simulations to
evaluate their electrical performance [3].
Digital design facilitates transfer of information through signals represented by
binary values, 0s or 1s. This involves a series of high and low voltage signals being sent and
received. Figure 1.1 characterizes a high-speed serial link which includes the transmitter,
channel, receiver, and some circuitry for timing recovery.
2
As shown in the figure above, digital binary data is transformed to electrical signals
by the transmitter. The transmitter then advances these signals to the channel. The
channel is usually a transmission line and can consist of traces on a printed circuit board
(PCB), traces within packages, cables, and connectors that join these various parts together
[4]. After traversing the channel, these signals are then recovered to their original binary
form by the receiver. In order to achieve this task of recovering electrical signals, it is
essential to integrate a timing recovery circuit. This permits the receiver to sample
incoming electrical data at optimal timing instants so as to distinguish individual binary bits
from each other. At higher data rates, the interaction between jitter and noise sources
plays a crucial role in degrading the performance of links and this also makes it extremely
difficult to analyze performance of the link at such speeds [2].
The signal integrity of a digital system relies directly on the type of signaling scheme
used for its operation. Speed, efficiency, and robustness are the main attributes that are
influenced by the type of signaling method employed in a communication system [2]. In
recent times, with data rates approaching multi-gigahertz input/output (I/O) performance
Figure 1-1. Block Diagram of a standard serial link [4]
3
severely limits the overall system performance. Therefore, determining the type of
signaling method for a digital system is very important for high-speed I/O systems so as to
achieve a robust system with a suitable system performance.
Signaling is used to translate digital symbols (1s and 0s) into physical quantities such
as voltage and current. A signaling system is characterized by six simple constituents:
topology, transmitter, interconnect, receiver, clock, and termination. A number of
potential signaling techniques can be achieved by forming different combinations of the
six components mentioned above. There are certain factors that must be considered while
deciding the signaling method to be employed such as, the required data rate, silicon area,
power, and system cost. A good signaling method achieves the right balance of these
factors for a target application [2].
Signaling schemes help perform the following tasks in a communication system [2]:
1. The transmitter translates logic 1s or 0s to analog signals
2. An interconnect facilitates the transportation of these analog signals between
the transmitter and receiver
3. The receiver compares this analog signal to the reference value, so as to
retranslate these analog voltages to their original digital form of 1s and 0s logic
4. The transmitter is notified by the clock about the timing to send succeeding
signals, and the clock also updates the receiver about the time instant for data
sampling
5. Terminators in the receiver absorb the analog signals
4
The physical limitation of communication channels and semiconductor technology
has become a bottleneck for the system’s performance and this tends to limit the
maximum symbol rate of the serial data transmission. Therefore, much research has been
done to increase the data rates by maintaining the same symbol rate and sustaining signal
integrity of the system [5].
Research Motivation
Serial data communication systems are significantly important to process high
volumes of data [6]. With significant improvements in link architecture, signaling
techniques, and semiconductor process technology, over the last decade or so, data rates
have scaled over several multi-Gb/s [7]. However, along with an increase in speed of
operation, it is extremely important to lower the power consumption and manufacturing
cost of systems [8].
The fundamental concerns of signaling in modern digital interfaces include
reflection, crosstalk, attenuation, resonances, and power distribution noise. Each of these
physical phenomena is unique and follows a particular failure mechanism process.
However, all of them boil down to the one end result: a storage element on the receiver
chip fails to capture the data bit sent by the transmitting chip. These storage elements are
typically registers and flip-flops and it is extremely difficult to model their behavior for
simulation purposes. This is mainly because the failure process not only involves voltage
waveforms at the input pin of the chip, but also contains a timing relationship between
5
these waveforms along with the clock that samples these waveforms [9]. The accuracy of
a system is highly affected with an increase in its data rates. A transmission anomaly occurs
due to several intrinsic and extrinsic instabilities observed in a chip-to-chip signaling circuit
as well as serial I/O links. This transmission anomaly is called jitter [10]. Jitter and noise
sources are responsible for introducing these bit errors in the system. They must be taken
into account while designing, developing, deploying, interconnecting, and maintaining
every digital system. Therefore, there is a growing demand for signal integrity engineers to
develop diagnostic algorithms and tools in order to maintain certain level of accuracy in a
system to avoid bit errors [11]. It is extremely vital for designers to interpret the effects of
jitter in the entire system to prevent bits from getting corrupted.
A communication system generally comprises of three main constituents:
transmitter, channel, and receiver. It is pertinent to isolate the jitter accrued in each of
these constituents. Traditionally, there have been a couple of algorithms established for
modeling jitter in high-speed I/O links. These algorithms only account for a few sources of
jitter and require exhaustive, time consuming simulations to attain rational results.
Therefore, a recent algorithm has been employed to analyze and compute different
forms of jitter, at run-time. This is extremely crucial because acquiring delayed result beats
the whole purpose of using high-speed interconnects for rapid transfer data.
Core Idea
6
Jitter has been discussed and analyzed in several technical research articles,
however, there is no unified and comprehensive treatment as yet [10]. The core idea of
this research is to implement an efficient algorithm to avoid time consuming simulations
for jitter analysis in high-speed serial I/O links. A statistical approach has been recently
introduced to estimate the bit error rate (BER) of a system using probability density
functions (PDF) by estimating the jitter in high-speed interfaces. The statistical approach
used is known as link analysis and it is best suited for jitter modeling in high performance
microprocessors and chip-to-chip signaling [12], [13]. However, one of the base
assumptions for these analysis is that the receiver is linear in nature.
However, receivers generally consist of equalizers which are highly non-linear in
nature and this tends to affect the skew, BER values and jitter PDFs. In order to account for
receiver non-linearity, a CMOS receiver model is taken into consideration for simulating
the PDFs in presence of non-linearity.
Therefore, this thesis presents a robust implementation of statistical link analysis using
HashMaps, to account for individual jitter PDFs in a system. This methodology involves the
calculation of PDF for voltage and timing of a signal at the decision point and is based on
the factors causing significant signal impairment. This further facilitates the estimation of
BER for linear systems. Inter-symbol interference (ISI) is induced in a signal to contribute
towards voltage impairments which is generally calculated using impulse response
obtained from S-parameters and reflection coefficient measurements [14]. Similarly, the
PDF of timing impairments which comprises of random as well as deterministic
components is also calculated.
7
The effect of voltage and timing impairments at each unit interval are computed
such that an effective PDF is estimated for the bit at the cursor position, thus, facilitating a
decision on whether the cursor bit is a ‘0’ or a ‘1’ in presence of a cumulative effect of all
neighboring unit intervals contributed by both RJ and DJ. The PDF of all impairments are
convolved to obtain the final PDF, followed by the application of statistical methods to
calculate the joint PDF. This joint PDF further enables the calculation of bit error rates
(BER).These results are then followed by a non-linear CMOS receiver model in order to
analyze jitter in presence of non-linearity.
Outline
This thesis comprises of five chapters. The first chapter gives a brief review of signal
integrity essentials, motivation for this research and gives a gist of the research along with
an outline illuminating the structure of each chapter in this thesis.
The second chapter sheds some light on the causes of signal degradation in high-
speed interfaces and its impact on the performance of signal. This chapter elucidates the
effects of jitter in high-speed I/O links, its constituents and sources. Some crucial
parameters and performance metrics pertinent to these interfaces are laid out in this
chapter. Additionally, 4-level pulse amplitude modulation (PAM-4) and non-linearity
observed in CMOS receivers are highlighted towards the end of this chapter.
Third chapter is an overview on several aspects taken into consideration in the field
of jitter modeling and measurements. This chapter defines some of the existing technology
8
widely used to measure and analyze jitter. Furthermore, statistical jitter analysis
techniques such as Tail fit algorithm [15], Peak Distortion analysis (PDA) [16] and random
jitter estimation through direct computation of probabilities [13], [17] are explained in
detail.
The fourth chapter analyzes the general flow of total jitter acquisition in a system
using a statistical algorithm known as Link Analysis. Each phase of this algorithm is
elaborated with probabilistic models in this chapter.
Chapter five provides a step-by-step explanation for the implementation of the
algorithm that comprehends total jitter accumulated at the receiver. This total jitter is a
combination of random and deterministic jitter sources which is contributed by the
transmitter and channel respectively. Additionally, this section depicts the jitter PDF
calculation in the presence of non-linearity observed in receivers. This concept is
elucidated with an example of a CMOS receiver exhibiting non-linearity for the NRZ and
PAM-4 modulation schemes.
Finally, the sixth chapter concludes this thesis by displaying the output acquired at
the end of the simulation. It also offers several directions for the expansion of this research,
in the future.
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CHAPTER 2. LITERATURE REVIEW
Today’s typical error rate, necessary for successful processing of serial data
systems, is 10-12 [11]. This translates to only 1 bit error in 2.3 hours at 100 megabits per
second (Mb/s) or 4 minutes at 3 gigabits per second (Gb/s). As data must be provided at
very high-speed with an exceptionally low error probability, the operation of high-speed
serial communication systems ought to have very stringent margins. Hence, jitter is a
crucial concern for engineers developing components such as transmitters, receivers, and
data channels, capable of data transfers at an extremely high-speed [11]. Jitter limits the
maximum achievable data-rates and therefore, tends to degrade the performance of high-
speed serial links [18].
Jitter is basically the instability of location or the relative timing disparity in the
position of signal. The formal definition of jitter is the short-term variation of significant
instants from their ideal position in time. It occurs when the transition to the next symbol
state takes place earlier or later than the end of the exact symbol time interval. The non-
ideal characteristics of digital data transmission give rise to jitter. Jitter components lead
to errors, as they reduce the phase margin of signals. Jitter affects the system as a whole
and can be introduced by every circuit component used to generate, convey, and receive
signals [19]. In previous times, jitter measurements were a priority to determine the
performance of communication systems. Recently, with the rapid increase of data rates to
unprecedented levels, reducing the amount of jitter has become a higher priority for
ensuring high reliability and performance in data buses and integrated circuits. As a result,
10
it is crucial to comprehend the amount of jitter introduced by each element of a system in
order to predict the overall performance of the system [19]. Therefore, jitter must undergo
thorough diagnosis, followed by accurate measurements in order to avoid the occurrence
of bit errors in a system [8]. Traditionally, several tools have been actively employed to
understand and analyze jitter such as real-time oscilloscopes, sampling oscilloscopes, time-
interval analyzers (TIA), phase-noise analyzers, and bit error-rate testers (BERT) [20].
Key Performance Metrics
In order to tackle the issue of jitter, it is initially important to understand jitter and
why it is an undesirable phenomena [20]. Some vital performance metrics used for
describing high-speed interfaces are defined in this section.
Data rate (DR)
In a high-speed link, the number of data bits successfully transferred from the
transmitter to the receiver in 1 second is known as the data-rate of that link. It is usually
measured in bits per second (b/s) and expressed in terms of a data bit’s width.
𝐷𝑅 =
1
∆𝑡𝑏𝑖𝑡 (1)
where ∆𝑡𝑏𝑖𝑡 represents the width of a single bit [3].
11
Unit Interval (UI)
In a non-return to zero (NRZ) encoding scheme, transitions occur at integer
multiples of the symbol period [21]. A unit of time that corresponds to the transmission or
reception of 1 bit of data is known as unit interval (UI).
1 𝑈𝐼 = 𝑇𝑖𝑚𝑒 𝑝𝑒𝑟𝑖𝑜𝑑 𝑜𝑓 1 𝑠𝑦𝑚𝑏𝑜𝑙 (2)
UI is represented as ∆𝑡𝑏𝑖𝑡 and it is the reciprocal of baud (bits/sec). In an ideal data
bit stream as shown in the figure below, a UI is equivalent to the length representing 1 bit
of data which is measured in terms of seconds.
Figure 2-1. Unit Interval (UI) for an Ideal NRZ Waveform
Signal to noise ratio (SNR)
Signal to noise ratio (SNR) is a figure of merit that may easily be compared across a
large number of simulation cases [22]. It is defined as the ratio of desired signal power to
the undesired noise power of a system, often expressed in decibels.
Generally, it is desired to have a SNR value greater than 1; higher signal power as
compared to the noise power indicates a lower probability of error. Additionally, eye
12
openings are directly associated with SNR margins of the system. Therefore, a larger SNR
indicates that the eye opening of the system is wider and vice versa.
Bit Error Ratio (BER)
In a digital transmission system, there are several reasons for occurrence of errors.
The data sent out from transmitter might be incorrect, data might get altered while
traversing through the channel, and the receiver’s decision about the bit value might be
incorrect. BER is a fundamental measure of the overall transmission quality of a system
[23], and it is defined as the ratio of number of incorrect bits detected to the total number
of bits received. It estimates the performance of a communication link. BER of a link can
be denoted as,
𝐵𝐸𝑅 = 𝑁𝑒/𝑁𝑇 (3)
such that 𝑁𝑒 is the number of bit errors detected and 𝑁𝑇 is the total number of bits
received.
At data rates over 1 Gb/s, jitter and noise have a greater impact on the BER than
lower data rates. Hence, at higher data rates, jitter and noise amplitudes must be
proportionately lessened in order to maintain an acceptable error rate.
Eye Diagram
Eye diagram is the most imperative measurement tool used to evaluate and
analyze the reliability of signals in high-speed serial links [24]. It is obtained by overlaying
13
multiple traces of data bits with the help of a real or reconstructed clock as the timing
reference. These superimposed traces form an envelope of amplitude and timing
fluctuations. Eye diagram is very useful in representing jitter making it possible to visualize
the amplitude and timing margins of a waveform. As shown in the figure, eye diagram is
used to specify the signal integrity limits as well as jitter [25].
A BER eye can be considered to be a two-dimensional extension of the conventional
bathtub plot that characterizes BER as a function of voltage and timing offset [7]. Figure 2-
3 illustrates a noisy NRZ waveform and its corresponding eye diagram with timing and
voltage margins. Timing and voltage margins correspond to the horizontal and vertical eye
openings respectively. These margins serve as a visual representation to determine the
occurrence of bit errors. Therefore, larger voltage and timing margins correspond to a
larger eye opening thereby, indicating lower probability of bit errors.
Figure 2-2. Eye Diagram [25]
14
Figure 2-3. Sample Eye Diagram of a Data Signal
Bathtub Curve
The bathtub curve is a visual representation of the BER as a function of unit interval
(UI). It is very useful in specifying the BER in terms of the UI at numerous points within an
eye diagram. This plot provides a direct measurement of total jitter (TJ). Based on the jitter
in the signal, the bathtub plot relates the BER to timing margins of the receiver. Therefore,
this curve does not declare a value for the eye opening, unless it is quantified for a
particular BER. An instance of the deduction from the bathtub curve is the eye opening at
BER of 10-3 is 10 ps. Thus, the duration of the eye opening is obtained by the BER level
measured at either side of the eye. As the figure 2-4 illustrates, the bathtub curve is
extracted from the eye diagram and it is used to specify the eye opening at a specific BER
and reference voltage. The probability of bit errors is high near the transition edges of 0 UI
and 1 UI and it decreases precipitously towards the center of the UI.
15
Jitter Budget and Jitter Tolerance
Jitter tolerance is defined as an effective measure of a receiver's capability to
tolerate incoming accumulated signal in a system [10]. The receiver’s ability to determine
the correct bit level depends on this jitter tolerance value. If the jitter in a system is less
than the jitter tolerance value of a system, then the receiver will be capable of interpreting
all transmitted bits, thereby preventing the occurrence of errors.
Phase Noise
Phase noise is a frequency-domain measure of the clock signal and is defined as the
timing jitter representation for the phase deviation. It is not a voltage noise [2], but a phase
offset quantity that repeatedly varies the timing of the signal. Phase noise is also defined
as the unintentional phase modulation that spreads the signal spectrum in the frequency
Figure 2-4. Bathtub Curve [78]
16
domain [26]. Phase noise depicts the perturbation that fluctuates the timing of the signal.
It is existent in every active and resistive component; however, it is mostly observed in
oscillators such as crystal and phase-locked oscillators used in clock recovery applications.
Phase noise is a specification that characterizes spectral purity [27].
A sine wave represented by the equation below,
𝑋(𝑡) = sin (2𝜋𝑓0𝑡 + 𝜑(𝑡)) (4)
where f0 is the nominal frequency and φ(t) represents the phase noise. The unit of
measurement for phase noise is dBc/Hz. The relationship between RMS jitter (Δt(t)) and
phase noise can described by the following equation:
∆𝑡(𝑡) =
𝜑(𝑡)
2𝜋𝑓0 (5)
Figure 2-5. Phase Noise Representation [23]
17
The unit for RMS jitter is seconds, whereas phase noise is described in terms of
radians. Phase noise influences the value of jitter which is quantified as peak-to-peak
values, whereas jitter is estimated in terms of root-mean square (RMS) jitter. RMS jitter is
one of the most popular jitter measurement parameters, due to phase noise and it is
defined as:
𝐽𝑅𝑀𝑆 = 1/2𝜋𝑓0√ ∫ 𝑆𝜑(𝑓)𝑑𝑓
𝑓𝐻
𝑓𝐿
(6)
where Sφ(f) represents the power spectrum density (PSD) of phase noise and it is used to
describe a stochastic process. This PSD quantifies the distribution of phase noise power in
terms of frequency. Or in other words, it yields the total phase noise power by integrating
the noise power over all frequencies.
Several approaches are used to measure phase noise. The simplest approach
involves the use of a spectrum analyzer, whereas the most commonly used approach is the
reduction of dynamic range while mixing carrier frequency to an intermediate frequency
(IF) level.
Phase Jitter
The timing variability that occurs due to rapid transitions between the logic levels
is known as phase jitter. For the occurrence of transitions between logic levels, every digital
system must have well-defined positions in the time domain. Generally, these positions
18
represent the bit intervals and are exact integer multiples. Phase jitter is the digital
equivalent of phase noise and is defined relative to the ideal positions of the transitions.
From the figure 2-6, a digital jittered signal is described as:
𝑡𝑛 = 𝑇𝑛 − 𝜙𝑛 (7)
where 𝑡𝑛 represents the time when nth transition occurred (solid waveform), 𝑇𝑛 is the
ideal timing for the nth transition (dotted waveform in the first part of figure 2-6), and 𝜙𝑛
is the time jitter that represents the timing offset of the transition in terms of ps.
Although phase jitter is defined at bit transitions, it is easier to understand it as a
continuous function in time.
Figure 2-6. Phase Jitter Representation [23]
T1 T2
T4 T3
t2 t3 t1 t4
19
Wander
Slower variations are termed as wander or drift [6]. The figure 2-6 above
demarcates the range of frequencies for wander as well as jitter wander. The term
“wander” is used for timing variations occurring at a frequency of 10 Hz or lower. For
instance, wander is exhibited by the thermal delay variations caused due to the ambient
temperature changes during the day as well as the year-around seasonal temperature
variations. In some applications, wander is also known as drift [8]. Conversely, drift
corresponds to even lower frequencies as compared to wander. Wander and drift are
major concerns in large-scale synchronous systems [6]. These effects can be ignored in
serial applications with an embedded clock, as the clock data recovery mechanism
eliminates their effect [23].
Convolution
Convolution is the fusion of two quantities with each other. Mathematically,
convolution can be explained as the blending of two functions. If the two functions, p(x)
Figure 2-7. Frequency Scale for Wander and Jitter
20
and q(x) are convolved with each other, then p(x) is placed above q(x) and the overlap is
computed by integrating the product of p(τ) and q(t - τ) as,
(𝑝 ∗ 𝑞)(𝑡) = ∫ 𝑝(𝜏)𝑞(𝑡 − 𝜏)d𝜏
+∞
−∞
(8)
The symbol * is the convolution operator and p * q denotes the convolution of functions p
and q. τ is the amount by which function q is shifted [23].
Convolution is associative and distributive in nature. It is independent of the order
in which functions are selected. The associative law followed by convolution illustrated by
the equation below:
𝑝 ∗ 𝑞 = 𝑞 ∗ 𝑝 (9)
In the event of multiple functions undergoing convolution, the result will always be
independent of the order in which each of these functions are convolved. The distributive
nature of convolution is demonstrated as:
(𝑝 ∗ 𝑞) ∗ 𝑟 = (𝑝 ∗ 𝑟) ∗ 𝑞 = (𝑞 ∗ 𝑟) ∗ 𝑝 (10)
Jitter Probability Density Function (PDF)
Histograms, probability density functions (PDF) or Cumulative density functions
(CDF) are used to analyze jitter in the statistical domain. Histograms are formed by plotting
the frequency of occurrence versus the range of values for a specific parameter of interest.
21
The occurrences that fall within a particular unit interval (UI) are represented by the height
of the histogram.
Linear Time Invariance (LTI)
A system is said to be linear if the output of the system is directly related to its
input. In other words, a linear system must satisfy the property of superposition. For
instance, if a linear system is fed with an input signal ‘𝑥(𝑡)’consisting of two components
‘𝑥1(𝑡)’ and ‘𝑥2(𝑡)’ with corresponding constants ‘𝑎1’ and ‘𝑎2’,
𝑥(𝑡) = 𝑎1𝑥1(𝑡) + 𝑎2𝑥2(𝑡) (11)
then the output ‘𝑦(𝑡)’ is represented as,
𝑦(𝑡) = 𝑎1𝑦1(𝑡) + 𝑎2𝑦2(𝑡) (12)
The general form of a linear system with input
𝑥(𝑡) = ∑ 𝑎𝑛𝑥𝑛(𝑡)
𝑛
(13)
will have output
𝑦(𝑡) = ∑ 𝑎𝑛𝑦𝑛(𝑡)
𝑛
(14)
for any constant 𝑎𝑛; where ‘𝑦𝑛(𝑡)’ is the output resulting from the input ‘𝑥𝑛(𝑡)’ [3].
If the time delay at the input of a system causes a corresponding time delay at the
output, then the system is said to be time-invariant. Time invariance implies that the
22
output response of the system is definite for every specific input signal, irrespective of the
time this input is applied. Consequently, whether an input is applied at 𝑡 = 0 or 𝑡 = 𝜏, the
output will be identical except for the time delay of 𝜏 [3]. The LTI property is a fundamental
requirement for most jitter analysis techniques.
Dual-Dirac Model
The Dirac delta function, 𝛿(𝑥 − 𝑥0) is initialized to have a value of infinity at 𝑥 =
𝑥0, and 0 elsewhere, such that it is spike centered at 𝑥 = 𝑥0 [28]. This infinite value makes
the integral equal to 1.
𝛿(𝑥 − 𝑥0) ≡ {
0, 𝑥 ≠ 𝑥0
∞, 𝑥 = 𝑥0 (15)
∫ 𝛿(𝑥 − 𝑥0)𝑑𝑥
+∞
−∞
= 1 (16)
Based on the figure above, a dual-Dirac DJ model consists of two logic-transition
trajectories, such that its crossing points are at 𝜇𝐿 and 𝜇𝐻. This dual-Dirac model is
Figure 2-8. Convolution of RJ and Dual-Dirac DJ = Dual-Dirac Representation for TJ
23
convolved with a Gaussian RJ PDF having a standard deviation of 𝜎, such that the resultant
is the combination of two Gaussian PDFs with their mean values equivalent to 𝜇𝐿 and 𝜇𝐻.
A limitation of the dual-Dirac model is that the component corresponding to
deterministic jitter “DJ(δδ)” is not equal to its peak-to-peak value “DJ(pk-pk)”. As explained
in [15],
𝐷𝐽(δδ) <= 𝐷𝐽(𝑝𝑘 − 𝑝𝑘) (17)
Need for Jitter Measurement
In order to realize the significance of jitter measurements, the relationship
between output jitter, jitter tolerance, and jitter transfer must be identified. These three
measurements define the jitter performance in a transmission system, and are shown in
the figure below.
Figure 2-9. Jitter Measurement categories for a simple Transmitter and Receiver System [29]
24
Output Jitter
Output jitter is the amount of jitter generated by the device under test (DUT), and
received at the output of the system. Based on ITU-T, which regulate standards such as
SONET/SDH in the field of telecommunications, the jitter produced by devices and
equipment is defined as jitter generation [8], [29]. This jitter is either generated within a
single piece of equipment known as intrinsic jitter, or it accumulates as the signal traverses
a large network known as network jitter [30]. It is specified in terms of unit intervals (UI)
and defined as root mean square (RMS) or peak-to-peak values. RMS values give
information about the total amount of average jitter present, while peak-to-peak results
describe the effect on performance due to extremes that can cause errors [29].
Jitter Tolerance
Jitter tolerance quantifies the ability of a link to withstand jitter without dropping
below a particular BER. The phase of data signal is modulated with a specific frequency and
magnitude; for each modulation, the frequency of interest and the jitter amplitude are
increased until the link BER drops below the specified threshold [31]. As the jitter value
exceeds the jitter tolerance of the receiver, an error is observed in the communication
system. Therefore, the cumulative jitter generated in the transmitter and transmission line
should be less than the jitter tolerance of the receiver in order to avoid the occurrence of
errors.
25
The clock data recovery (CDR) circuit mainly influences the jitter tolerance of the
receiver [8]. A signal with sinusoidal jitter is generated and transmitted through the
channel, such that the jitter amplitude is preserved so as to avoid the detection of
transmission errors at the receiver. Clock jitter is not sinusoidal in reality; however, its ease
of generation, ability to reproduce results, and the capability of comparing results of
different system specifications in the form of a jitter tolerance mask, make sinusoidal jitter
suitable for analysis [30]. A point on the jitter tolerance curve is indicated by the maximum
amplitude at which the BER requirement is met.
Jitter Transfer
The amount of jitter transferred between input and output of a network is known
as jitter transfer. This jitter is a function of jitter modulation frequency and the type of
clock data recovery (CDR) approach implemented [30]. It is expressed in terms of dB units.
The CDR circuit in a receiver plays the vital role in recovering the clock pulses from data
signals received at the receiver. A phase locked loop (PLL) circuit is employed to restore
data re-timed according to the recovered clock [8]. A PLL is basically a feedback system
consisting of a voltage-controlled oscillator (VCO), phase detector, and low pass filter, as
shown in the diagram below. The role of the PLL is to force the VCO to reproduce and track
the frequency and phase at the input, under lock mode. This in turn, helps the PLL recover
the clock pulses for data signals arriving at the receiver.
26
In figure 2-10, φin and φout represent the input and output phase respectively, ωin
is the input frequency whereas ωout is the output frequency. Vcont is the VCO control
voltage and it provides a baseband PLL output that tracks the phase variation at the output
[32]. As a signal passes through a network, the jitter generated at each piece of equipment
turns into the input jitter to the following equipment. This jitter is further amplified as the
signal continues to traverse through the network, which may exceed the jitter tolerance of
subsequent equipment. In order to avoid this condition, a jitter transfer function is
specified for the equipment with a 0.1 dB of maximum permissible jitter gain. In the
frequency domain, it appears as spurs around the fundamental frequency of the device
under test (DUT). The relative magnitude of these spurs normalized to the input magnitude
is the jitter transfer magnitude at the modulation frequency [31]. The jitter transfer plot is
generated by reiterating this measurement for an array of modulation frequencies.
Figure 2-10: Functional blocks in a Phase Locked Loop (PLL) Circuit [32]
27
Types of Jitter Measurements
There are many methods for measuring jitter in a single waveform. The three most
common methods include period jitter, cycle-to-cycle jitter, and time interval error (TIE).
Based on the figure 2-11, these three approaches are related to one another. This figure
depicts a clock signal influenced by timing jitter.
Period Jitter (JPER)
This is the simplest and most straight-forward form of measurement. Period jitter
is defined as the deviation in cycle time of a clock signal with respect to the ideal period
over a number of randomly selected cycles [33]. Period jitter measures the period of each
clock cycle in the waveform. In figure 2-11, P1, P2, and P3 denote the measurements of
period jitter. A note-worthy advantage of period jitter measurements is that the ideal edge
locations of the reference clock is not required for measurements. However, if only JPERis
employed in the calculation, the result is often too conservative [34].
Figure 2-11. Types of Jitter Measurements [35]
28
In the equation and figure below, 𝑇0 represents the ideal clock period of the signal,
𝐽𝑃𝐸𝑅 is the calculated period jitter, 𝑉𝑇𝐻 is defined as the threshold voltage which
determines the bit’s logic-level based on its position at 𝑇𝑃𝐸𝑅(𝑛).
𝐽𝑃𝐸𝑅 = 𝑇𝑃𝐸𝑅(1) − 𝑇0 (18)
Cycle-to-Cycle Jitter (JCC)
The cycle-cycle jitter is indicated by C2 and C3 in Figure 2-11. It measures the
difference between clock periods of any two adjacent cycles. The difference in period jitter
that is measured between two adjacent clock cycles is defined as cycle-to-cycle jitter. This
measurement can be of interest because it shows the instantaneous dynamics a clock-
recovery PLL might be subjected to. For digital circuits, JCC is more useful than 𝐽𝑃𝐸𝑅 because
JCC calculates the essential receiver margins of setup time and hold time. Just like period
jitter, the ideal edge locations of the reference clock is not needed for cycle-to-cycle jitter
measurements. JCC is measured by its Peak-to-Peak value in a given time period [77]. It can
represented as:
Figure 2-12. Measurement of Period Jitter [34]
29
𝐽𝐶𝐶 = max {𝑇𝑃𝐸𝑅(𝑛) − 𝑇𝑃𝐸𝑅(𝑛 + 1)} (19)
Time Interval Error (TIE)
TIE is defined as the phase difference of the positive and negative maximum phase
shifts with respect to the phase at the start of the measurement. It is a measurement of
the time difference between the reference edge and the signal’s edge. It measures the
signal against a reference clock to distinguish the distance of signal’s active edge locations
with respect to the ideal edge locations of a reference clock. Hence, TIE measurements
require information of ideal edge locations of the reference clock which makes them
significantly different from period jitter measurements. Therefore, an oscilloscope is not
capable of performing TIE measurements, without the application of CDR circuits or certain
post-processing techniques [35]. In figure 2-11, TIE measurements are denoted by TIE1,
TIE2, TIE3, and TIE4.
𝑇𝐼𝐸 = 𝑀𝑒𝑎𝑠𝑢𝑟𝑒𝑑 𝐴𝑟𝑟𝑖𝑣𝑎𝑙 𝑇𝑖𝑚𝑒 − 𝐸𝑥𝑝𝑒𝑐𝑡𝑒𝑑 𝐴𝑟𝑟𝑖𝑣𝑎𝑙 𝑇𝑖𝑚𝑒 (20)
Figure 2-13. Measurement of Cycle-to-Cycle Jitter [77]
30
TIE measurements can be also be performed by integrating the period jitter. TIE is
capable of determining the mean value, peak value, and standard deviation. TIE is very
useful in real-time instruments, as it maintains a record of error versus time [36]. TIE is
very efficient in displaying the effect that very small amounts of period jitter can
accumulate over time.
Sources of Jitter
Jitter disturbs the edges of data transmitted as well as the recovered clock.
Therefore, jitter causes bit errors in a signal and it directly affects the bit error rate (BER)
of a link. In order to achieve a steadfast link performance, jitter in the link must be
minimized. In addition, it is imperative to identify and understand prevailing sources of
jitter in the transmitters and channels of high-speed interfaces.
The physical nature of various noise and jitter sources for a communication system
can be classified into two major classes: non-intrinsic and intrinsic [37]. The intrinsic type
deals with the physical properties of semiconductor devices such as electrons and holes,
while the non-intrinsic type is design related. Intrinsic sources are random in nature and it
Figure 2-14. Measurement of TIE [80]
31
includes thermal noise, shot noise, and flicker noise, whereas non-intrinsic sources
contribute to deterministic jitter such as periodic noise, duty cycle distortion (DCD),
crosstalk, and inter-symbol interference (ISI).
Intrinsic Sources
Intrinsic noise is caused by the randomness and fluctuation of electrons and holes
in semiconductor devices. The thermal vibrations of semiconductor crystal structure
change the mobility based on the instantaneous temperature of material [38]. This type of
noise is caused by imperfections due to the variations in semiconductor process such as
the non-uniform doping density. This noise can be minimized but not completely
eliminated and hence, it places a fundamental limit on system performance and dynamic
range [37]. Thermal, shot, and flicker noise are typical examples of intrinsic noise.
Thermal Noise
The noise caused by random motion of charge carriers under thermal equilibrium
condition is called thermal noise. The kinetic energy of these random charge carriers is
proportional to their mean-square velocity and temperature. The power spectrum density
(PSD) of thermal noise is white.
Thermal noise affects limit on the SNR in devices with non-zero absolute
temperature. John Bertrand Johnson, former physicist at Bell Laboratories, discovered that
in thermal equilibrium state, noise in a conductor is dependent on the temperature and
resistor. Moreover, an American physicist named, Harry Nyquist, developed a similar
32
theory to explain Johnson’s discovery based on the second law of thermodynamics [37].
Hence, it is also known as Johnson noise, Nyquist noise or Johnson-Nyquist noise.
Shot Noise
The noise introduced by individual quantized carrier current in a potential barrier
with spatial distribution is known as shot noise. Shot noise is due to the random flow
fluctuation and it is directly proportional to the DC bias current, as well as the charge of
the carrier. Typically, shot noise is larger than thermal noise [37].
Flicker Noise
Flicker noise is observed in all active devices and some passive devices, such as
carbon resistors [37]. The noise power spectrum of flicker noise is inversely proportional
to the frequency over a wide range of frequencies and this is known as the 1/f power law.
Therefore, the quantitative measure of flick noise is empirical in nature.
𝐹𝑙𝑖𝑐𝑘𝑒𝑟 𝑛𝑜𝑖𝑠𝑒 𝑃𝑆𝐷 ∝ 1/𝑓𝛼 (21)
The PSD of flicker noise is directly proportional to the inverse of frequency raised
to the factor of α, where α is approximately equal to 1. Therefore, flicker noise is also
known as 1/f noise [37]. Flicker noise is associated with DC current, such that the flow of
charge carriers tends to get trapped due to device defects and contamination. Flicker noise
is evaluated on its noise power which is directly proportional to the current fluctuation
[39]. This is called the “trap and release” theory of flick noise [37]. The “trap and release”
method is random in nature, and significantly substantiates flicker noise at low
33
frequencies. In complementary metal-oxide semiconductor (CMOS) devices, the square of
current fluctuation is determined by:
𝑖𝑛
2 =𝐾
𝑊𝐿.𝛥𝑓
𝑓 (22)
where K represents a constant, Δf denotes the range of frequencies while f is the frequency
value, W and L specify the width and length of the CMOS channel respectively [39].
Non-Intrinsic Sources
The design-related deviations observed in a system are known as non-intrinsic jitter
sources. This type of jitter is caused by discernible interference signals and can be
accounted for by appropriately improving designs. Some common examples of non-
intrinsic jitter sources include crosstalk, periodic modulation, DCD, ISI, undesired
interference such as electromagnetic interference (EMI) due to radiation, and reflection
caused by unmatched media [37]. The magnetic field from an EMI source such as power
supplies, AC power lines, and RF signal sources, tend to affect a sensitive signal path which
thereby modulates the voltage and timing levels of a signal. One of the most common
sources of EMI is the switching-type power supplies as they can radiate strong, high
frequency electric and magnetic fields along with the ability to conduct large amounts of
electrical noise into a system provided they lack shielding and output filtering capabilities.
EMI corrupts the signal by inducing noise currents in a conductor and thereby, alters the
bias of the conductor [39].
34
Crosstalk and ISI are the two largest noise sources in serial digital multi-gigabit
communication systems [40], [41]. All non-intrinsic sources combine and form the basis of
deterministic jitter.
Components of Jitter
The approach involving separation of jitter into its constituents, deterministic jitter
(DJ) and random jitter (RJ), followed by its recombination to form total jitter (TJ) is known
as jitter analysis. DJ is bounded in nature while RJ is unbounded. In other words, the
probability of DJ can be determined, whereas that of RJ cannot be estimated due to its
uncontrolled PDF edges.
Based on the figure shown below, TJ consists of two broad types: random jitter (RJ)
and deterministic jitter (DJ). Deterministic jitter is further classified as periodic jitter (PJ),
data dependent jitter (DDJ), and bounded uncorrelated jitter (BUJ). Data dependent jitter
(DDJ) comprises of duty cycle distortion (DCD) and inter-symbol interference (ISI). Each of
these jitter components has a particular root cause.
35
DJ is caused by non-intrinsic jitter sources such as reflection, crosstalk, EMI, ground
bouncing, periodic modulations, or pattern dependency. Crosstalk is the most common
source for BUJ. On the other hand, RJ is caused by intrinsic factor of semiconductor devices
such as thermal noise, shot noise, flick noise, non-stationary interference, or random
modulation [37].
Random Jitter (RJ)
Random jitter is caused by several sources in the transmitter and channel and as
the name suggests, it is random in nature [21]. In simpler words, there is no distinct pattern
Figure 2-15. Various Types of Jitter [81]
36
to accurately perceive its variation in timing, voltage, and noise. The amplitude distribution
of RJ is random and uncorrelated.
The primary source of RJ in the transmitter is the voltage controlled oscillator (VCO)
in the phase-locked loop (PLL) oscillator circuit, whereas external factors such as thermal
noise gives rise to RJ in the channel. The voltage level fluctuates intermittently due to such
noises. This leads to variations in the occurrence of voltage level feedback to the VCO [13].
The power supply noise induces random PLL jitter which causes the RJ probability
distribution to spread infinitely and thus, RJ is unbounded in nature.
The timing uncertainty of these unbounded sources represents a Gaussian
distribution such that
𝑅𝐽 (𝑡) =
1
√2𝜋𝜎𝑅𝐽
𝑒−
(𝑡−𝜇)2
2𝜎𝑅𝐽2
(23)
where RJ(t) is the probability of having a timing jitter of t picoseconds (ps) due to random
source, μ is the mean value of the distribution (μ = 0) and σRJ is the root-mean-square
timing uncertainty (jitter) [3]. RJ has a flat PSD across relevant frequencies with ripples as
data is being accumulated [42]. Tails of the Gaussian PDF extend very far, making it very
difficult to spot them. This is due to their small occurrence probability, requiring a very
long observation time to capture them. This illustrates that the probability of occurrence
of an event in the tail region away from the mean are not quite frequent. Such samples are
only observed after the collection of many samples. RJ is specified by RMS values due to
its unbounded nature. This is because jitter peak-to-peak values are based on the sample
size and the measurements require a longer duration in the presence of random noise. On
37
the other hand, a fast peak-to-peak measurement is extremely vague unless some
boundary condition in specified [25]. A bounded peak-to-peak value can be defined for
unbounded RJ, if there is a set peak-to-peak value that can exceed a particular level of
probability
The cumulative density function (CDF) of random jitter is
𝐶𝐷𝐹𝑅𝐽(𝑡) =
1
2(1 + erf (
𝑡
𝜎√2)) (24)
where erf is a sigmoid-shaped error function such that
erf(𝑡) =
2
√𝜋∫ 𝑒−𝑡2
d𝑡
𝑡
0
(25)
In a Gaussian distribution, extremely large uncertainties also possess a very small
non-zero probability of occurrence. This implies that the worst-case timing analysis has no
significance and in reality it is used to design immeasurably low BER systems [3]. Timing
measurement in terms of bit error rate tends to be more reliable as it provides the
probabilities of timing uncertainty exceeding the width of a UI. Hence, high-speed links are
adapting to BER-based approach for jitter budgeting [3]. This is depicted in the figure 2-16
below:
38
RJ is characterized by a Gaussian distribution based on the Central Limit Theorem
[3], [12], [16].
The Gaussian distribution is described by a mean value (typically equal to 0) and a
standard deviation, σRMS [3]. Even large uncertainties have a non-zero probability of
occurrence. It is also termed as “Gaussian jitter,” because it is typically modeled as a
Gaussian (normal) distribution and can be used to estimate the peak-to-peak jitter as a
function of BER. In other words, for a BER of 3 x 10-3, 6σ provides the peak-to-peak range
that excludes only 0.0013 samples [39]. Random jitter is the product of thermal noise,
which itself has a Gaussian distribution.
Deterministic Jitter (DJ)
Deterministic jitter is bounded, which implies that the probability of exceeding the
peak-to-peak maximum value is 0. It has components that are correlated with the serial
data carried by the waveform and components that bear no such correlation [23].
Sometimes, deterministic jitter is also known as systematic jitter.
Figure 2-16. Gaussian distribution representing Random Jitter PDF [44]
39
Periodic Jitter (PJ)
As the name suggests, periodic jitter (PJ) corresponds to the periodic variations in
the edge position of a signal over time such that its data edges swing back and forth [25].
In other words, the occurrence of data edges is higher at the extremes of the swing as
compared to the middle. PJ is a timing error such that the amplitude variation with respect
to time forms a sinusoid. Thus, PJ is also known as sinusoidal jitter (SJ). Sometimes, PJ may
be a result of unwanted modulation like EMI. In such cases, PJ can comprise of more than
one sinusoid. This type of jitter is typically the outcome of PLL circuitry oscillations or the
ripple created by switching power supply. Even a basic signal generator is capable of
producing PJ [8]. PJ is classified as uncorrelated jitter because it is not synchronized with
the data bits of a signal.
𝐽𝑃𝐽(𝑥) = ∑ 𝐴𝑖cos (𝜔𝑖𝑡 + 𝜃𝑖)
𝑁
𝑖=0
(26)
where 𝐽𝑃𝐽 corresponds to the total is periodic jitter, 𝑁 is the number of cosine components,
𝑡 is the time, 𝜔𝑖 is the angular frequency, 𝜃𝑖 is the phase and 𝐴𝑖 is the amplitude [43].
Figure 2-17. Deterministic Jitter PDF [44]
40
𝑃𝐷𝐹𝑃𝐽(𝑥) = {1
𝜋√𝐴2 − 𝑥2 0
; A > |x| (27)
As shown in the figure below, PJ possesses characteristic peaks at both ends of the
histogram.
Figure 2-18. Periodic Jitter PDF [44]
Data-Dependent Jitter (DDJ)
Data-dependent jitter (DDJ) is the most common type of deterministic jitter (DJ)
and as the data rates approach multi-Gb/s range, it serves as the dominant limiting factor
for system performance. DDJ is a component of DJ and is also known as pattern-dependent
jitter.
DDJ corresponds to a variable jitter that is reliant on the data transmitted through
the link under test [25]. The common causes of DDJ are inadequate bandwidth and
reflections observed in the data being transmitted. DDJ is further divided into two sub-
components, duty-cycle distortion (DCD) and inter-symbol interference (ISI).
41
Duty-Cycle Distortion (DCD)
If a signal has unequal pulse-widths for high and low logic levels, then the jitter
resulting from it is known as duty-cycle distortion (DCD). DCD is produced as a result of the
erratic leading and trailing edges of data bits in a signal. DCD can be ignored if the signal
crossing occurs at the threshold level [8].
𝐽𝐷𝐶𝐷(𝑥) =
1
2∗ [𝛿 (𝑥 −
𝑊
2) + 𝛿 (𝑥 +
𝑊
2)] (28)
where 𝑊 is the peak-to-peak DCD magnitude and 𝑥 is the time displacement relative to
the ideal position [43].
In the equation above, the two 𝛿 functions represent rising and falling edges of the
signal. Each of these 𝛿 functions are halved because it is assumed that the number of rising
edges are the same as falling edges.
Figure 2-19. PDF for Duty-Cycle Distortion [44]
Inter-symbol Interference (ISI)
ISI is a result of channel frequency-dependent loss and reflections. ISI occurs due
to insufficient bandwidth and reflections triggered by impedance mismatch. ISI is not an
42
independent noise source and is dependent on the patterns that are transmitted over the
same trace.
Bit patterns comprise of different frequency components. Consequently, they tend
to disperse differently in a channel with limited bandwidth, thereby leading to timing
inaccuracies. The time delays and advances in rising and falling edges of data bits play a
significant role in contributing to ISI. For instance, signals having many successive bits at
the same logic-level (such as 01111110...) will cause an increase in voltage amplitude. This
in turn, will delay the falling edge. Contrarily, a data stream consisting of alternating ones
and zeros (such as 01010101…) will lower the voltage amplitude, thereby resulting in a
rapid falling edge.
Bounded Uncorrelated Jitter (BUJ)
The most common source of bounded uncorrelated jitter is crosstalk. As the name
suggests, it is classified as an uncorrelated form of jitter. BUJ is not aligned in time with the
signal’s bit stream. Despite its random characteristics, it is quantifiable in terms of its peak-
to-peak value. This is mainly due to its controlled spreading.
Figure 2-20. Inter-Symbol Interference PDF [44]
43
BUJ is typically caused by the coupling between adjacent links or an on-chip logic
switching [44]. The exact model of BUJ depends on the data pattern, coupling signal, and
coupling mechanism [25].
Crosstalk is defined as the interference from other signal traces, and is the main
source of BUJ. The injected crosstalk noise travels in both directions, forward towards the
far end as well as backward towards the near end. Crosstalk affects the edge transition
timing by altering the voltage values of the signal, thereby resulting in jitter.
Total Jitter (TJ)
In order to gain a better understanding of jitter, it is essential to evaluate different
components incorporated in TJ. As the name suggests, total jitter is the algebraic sum of
various types of jitter. TJ is a peak-to-peak value specified for a given bit error rate (BER).
TJ is the convolution of all independent jitter component probability density functions
(PDFs) [19]. In other words, TJ is a combination of RJ interacting with DJ [38]. A PDF is
generally illustrated as a normalized histogram and it represents the likelihood of a given
measurement relative to all other possible measurements.
𝑃𝐷𝐹𝑇𝐽(𝑡) = 𝑃𝐷𝐹𝑅𝐽(𝑡) ∗ 𝑃𝐷𝐹𝐷𝐽(𝑡) (29)
where, 𝑃𝐷𝐹𝐷𝐽(𝑡) = 𝑃𝐷𝐹𝑃𝐽(𝑡) ∗ 𝑃𝐷𝐹𝐼𝑆𝐼(𝑡) ∗ 𝑃𝐷𝐹𝐷𝐶𝐷(𝑡) ∗ 𝑃𝐷𝐹𝐵𝑈𝐽(𝑡) (30)
44
Figure 2-21. Total Jitter (TJ) PDF [44]
Four-Level Pulse Amplitude Modulation (PAM-4)
The growing demand for instant multimedia access in an ever-increasing number
of digital devices has continued to push the need for higher aggregate bandwidth in
modern communication hardware [45]. PAM-4 or 4-level pulse amplitude modulation is a
multi-level signaling scheme that comprises of four voltage levels. Each of these four
distinct amplitude levels of PAM-4 represents a combination of two binary bits. In other
words, it is a four-level code that transmits two bits per baud, as opposed to 1 bit per baud
for NRZ, a two-level code [46]. Therefore, the four possible combinations are ‘00’, ‘01’,
‘11’, and ‘10’ and each of these levels are clocked on a rising or falling edge of a clock signal
[47]. The pair of binary bits represents a ‘symbol’ [48].
45
Although, PAM-4 reduces the bandwidth (BW) requirement by half as compared to
the NRZ scheme, the signal to noise ratio (SNR) is severely hampered due to smaller level
changes in the signal levels. The additional voltage levels reduce the spacing between them
by a factor of 3 which makes PAM-4 more susceptible to noise than a NRZ signal, thereby
degrading the SNR of the signal, and leading to more bit errors than the NRZ signaling
scheme. Hence, PAM-4 is preferred over NRZ for short-haul systems [48].
Non-return to zero (NRZ) is the most widely used signaling scheme for legacy
systems operating up to a few Gb/s. However, due to its physical limitation of channel
attenuation at higher data rates, the attention has now started to drift towards PAM-4.
The implementation of PAM-4 promises to achieve the ever increasing demand of
bandwidth and higher data transfer rates. PAM-4 also potentially offers the benefit of more
relaxed equalization as compared to standard NRZ signaling at the cost of increased
integrated circuit (IC) complexity [49]. Contrarily, the possible move to PAM-4 signaling
Figure 2-22. Sequence of data bits for NRZ and PAM-4 signaling schemes [73]
46
would bring about the need to modify several important features of legacy systems. These
features include the need to use updated simulation algorithms, new test equipment,
newly defined test protocols, and higher complexity equalization [45].
Baud-rate of PAM-4 is reduced by half than that of NRZ and therefore, multi-level
transmitter uses less frequency spectrum than that of NRZ. The signaling frequency of
PAM-4 being half of NRZ, explains the lower channel loss. It is observed that for a data rate
of 10 Gb/sec, the unit interval for NRZ scheme is 10 ps, whereas for PAM-4 it is 20 ps. In
principle, this permits the use of existing channel designs [46].
The left side of the figure above represents the eye diagram for an NRZ signaling
scheme, while the right side shows the four digital levels of PAM-4 combining to form three
eye diagrams for each individual unit interval (UI). In this figure, the horizontal axis
represents time expressed in terms of UI, whereas the vertical axis represents the signal
amplitude.
Figure 2.23. Eye diagram for NRZ and PAM-4 signaling schemes [47]
47
As channel loss increases with frequency, PAM-4 offers less channel loss as
compared to the NRZ scheme. However, as there are four voltage levels in PAM-4, there
tends to be three eyes for each unit interval (UI), whereas NRZ has only one eye. If the two
systems are compared with the same transmitter voltage swing, the vertical eye opening
in the PAM-4 system is 9.5 dB less than in the NRZ system [46]. Therefore, in order to help
PAM-4 achieve a larger vertical eye opening, a difference of at least 9.5 dB in channel losses
is required at the receiver, as compared to NRZ.
As the signaling frequency of PAM-4 is half of NRZ, the horizontal eye opening for
PAM-4 is twice that of NRZ. DJ and RJ contribute prominently that to narrow the opening
of the eye. The effects of DJ and RJ are twice as evident in PAM-4 as in NRZ, which
consequently results in a relatively narrower PAM-4 eye opening [46].
Power consumption is also an important factor in the selection of a signaling
scheme [50]. Baud-rate (signaling frequency) is directly related to the power consumption
in digital systems. As the baud-rate is lower for PAM-4, there exists a lower power
consumption in these systems.
Crosstalk and system complexity are other factors that influence the performance
of PAM-4. For the same transmitter voltage swings, PAM-4 vertical eye opening is only 33
percent of NRZ. This makes it more susceptible to crosstalk and other noise sources.
However, crosstalk generally decreases by only about 3 dB between the NRZ and PAM-4
signal frequencies [46]. As a result, the sensitivity of PAM-4 systems to crosstalk is still
about 6.5 dB more than NRZ. Finally, a more complex encoding and decoding circuitry is
48
required to implement PAM-4 transceivers. This brings about an increase in the chip’s
surface area for the extra circuitry, which increases the overall cost for their
implementation.
A few challenges that designers come across while implementing a multi-level PAM
are:
1. Clock data recovery (CDR) displays more jitter due to multiple zero crossings
2. Sensitivity to crosstalk is incredibly higher due to maximum transition
3. Advanced equalization reduces performance of multi-level PAM signaling
technique
4. The receiver’s complexity seems to increase significantly, as the number of
comparators or analog to digital converters (ADC) get tripled and these
comparators must be 2-bit ADC [51].
Receiver’s Non-Linearity
Although, characterizing the input threshold parameters in a receiver are
important for digital I/O interfaces, they are often disregarded because of the ambiguity in
values.
The receiver circuit’s duty is to interpret incoming signal and translate it into digital
format so that it can be construed by a chip [9]. Traditional as well as modern jitter analysis
approaches have been designed for linear receiver models [7], [30], [52], [53]. This is
because linear models are extremely useful in initial design stages [3]. However, in reality,
49
receivers are non-linear in nature. Receiver’s non-linearity is a crucial factor to be taken
into consideration so as to improve the accuracy of jitter measurements provided by state-
of-the-art jitter modeling techniques. Therefore, the receiver’s non-linearity significantly
impacts the performance of these approaches in terms of accuracy in design. Complex
non-linear behavioral receiver models provide improved accuracy over linear models by
comprehending the non-linear relationship between the input/output (I/O) voltages and
parasitic capacitance [3].
The setup and hold parameters along with logic thresholds that influence system’s
noise margin and immunity are the most vital factors that define a receiver’s functionality.
The non-linear behavior in a system can be modeled by concatenating a linear
system with a polynomial function. This polynomial function represents the non-linearity
in a system and is typically based on Taylor series.
According to Taylor series of expansion, the input (𝑋) to the non-linear block can
be associated with the output (𝑌) such that,
𝑌 = ∑ 𝛼𝑛𝑋𝑛
𝑛
(31)
where αn are the respective coefficients of nth order non-linearity [14]. Even-order non-
linearity components are absent in differential signaling, thus, 𝑛 is generally odd. Thus, the
above expression reduces to:
𝑌 = 𝛼1𝑋1 + 𝛼2𝑋2 + 𝛼3𝑋3 + ⋯ (32)
50
This method is used to model static, time-invariant non-linearity in high-speed
links. This is mainly due to its close resemblance to actual receiver circuits, such as the
continuous time linear equalizer (CTLE) [14].
The simulation methods used for jitter modeling are based on assumption that the
analog channel is both linear and time-invariant. The linear time-invariant (LTI) premise
allows accurate and efficient conversion between the channel’s impulse response and
frequency response through the fast Fourier transform (FFT) [54]. In an LTI system, the
transmitted bit stream is convolved with the channel’s impulse response to estimate the
bit stream recovered at the receiver. In other words, the input to output transfer function
may be derived from the impulse response through the convolution process 𝑦(𝑡) =
𝑥(𝑡) ∗ ℎ(𝑡) [54].
CMOS Receivers
Early works on high-speed links were focused towards building CMOS components
that could generate, receive, and recover timing of high-speed data [55]. For inter-chip
communication circuits, CMOS inverter is the simplest form of receiver. Its simplicity, low
power consumption, and ease of implementation make it an exceptional receiver for full-
swing CMOS-based interfaces. CMOS receiver tends to provide better noise margins at
data rates in the range of multi-Mb/s [3]. If the n-channel and p-channel transistors have
appropriate dimensions and input attains a voltage of VDD/2, then both n-channel and p-
channel have equal resistance and this causes the inverter to change its state. However,
the receiver does not entirely switch states in a vertical line at VDD/2; there is a region of
51
uncertainty called threshold window [9]. The boundaries of this threshold window are
demarcated using unity gain points. The unity gain points are established where a line of
slope equal to 1 is tangential to the transfer characteristic curve. The input voltages that
correspond to these two points of tangency are the unity gain points [9].
Figure 2-19 illustrates the voltage transfer characteristic for an inverting receiver
where the output signal is a function of the input. The unity gain points (slope = −1) of
transfer characteristic determine the input thresholds ‘vil’ and ‘vih’. Output signal is very
sensitive to variations in the input, between vil and vih. This is a prohibited region for steady-
state signals and is known as a high-gain region [3].
Figure 2-24. CMOS Voltage Transfer Characteristic and noise margin [3]
52
CHAPTER 3. EXISTING TECHNIQUES FOR ESTIMATING JITTER
With communication rates increasing tremendously in the last two decades, a
variety of techniques have been introduced to evaluate the performance of a system or
component. The predominant method involves the use of an oscilloscope capable of
displaying eye-diagrams. An alternative to this method is the bit error ratio tester (BERT)
which provides statistical information about the data transmission quality [19].
Traditionally, these tools were used to characterize communication systems, however,
these processes were not only tedious to set up but they also proved to be inadequate in
terms of diagnosis, based on their wavering results. Another important technique known
as the time-interval analyzer (TIA) facilitates jitter measurements by determining the
fundamental metric of the eye opening as a function of BER. Additionally, TIA provides
excellent diagnostic tools such as jitter deconvolution, wherein jitter is divided into its
deterministic and random components [19].
This chapter elucidates various jitter measurement techniques used for analysis of
system performance along with their respective strengths and weaknesses. This is done by
introducing a recognized random bit stream into a device under test (DUT) followed by
comparison of the output received from DUT with the original bit pattern. Thus, the BER
can be acquired by calculating the ratio of number of bit errors observed to the total
number of bits transmitted.
The equipment required for this measurement is extremely expensive and
sophisticated due to its capability of comparing each bit’s amplitude and transition timing
53
at very high data speeds and relatively low signal levels, along with its ability to regulate
propagation delay of the signal that is entailed with the DUT. These tools include high-end
oscilloscopes and bit error rate testers (BERT) which measure the length of each bit of a
data stream at the same timing instant and thus, facilitate the demonstration and analysis
of eye diagrams. Ideally, unit interval (UI) serves as the reference for jitter related
measurements, and 1 UI is equivalent to the time duration of 1 symbol. Therefore, an UI
represents an ideal shape of 1 data bit, in terms of both amplitude and time.
Today’s high-speed connectors facilitating multi-Gb/s data rates are designed for a
particular jitter budget, which results in a specific BER value. This BER governs the voltage
and timing noise restrictions on a specific link. An eye diagram is essentially formed by
overlaying sliced fragments of the time-domain signal waveform of small number of
symbols in length. Eye diagrams are used to analyze the performance of a signaling
interface, with eye width and eye height as the crucial parameters. The communication
eye provides a good visual illustration of the BER.
54
Figure 3-1. Eye Diagram and its significance [57]
The methodology used to estimate the likelihood of error in a complete system is
known as BER analysis. This approach accounts for jitter in the transmitter and receiver of
a system. Additionally, it forms the basis of modeling techniques for jitter measurements.
A major drawback of the jitter method specifying the BER is that it assumes bit
errors only occur on bits undergoing a transition to a different logic-level. There must be
some probability assigned for a bit transitioning to the same logic-level and also for a bit
with no transitions on either side of it, even though the probability is small. The other
drawback is that the probability for transition of the data is assumed to be 0.5. This might
vary in physical systems.
55
Traditional Techniques
Real-time Oscilloscope
A fast real-time oscilloscope obtains many samples of a signal in one pass and
reconstructs the signal waveform by interpolation. The data acquired from these samples
is analyzed with respect to the data recovered by a CDR circuit in order to assess the timing
error of each edge. The resulting set of error values is used for spectrum analysis [25].
Real-time oscilloscopes can compute many sequences of adjacent bit lengths. The
difference in a bit’s duration from its adjacent bits, makes it possible to detect timing
variations at any instant. Real-time oscilloscopes are capable of constructing waveform eye
diagrams. The advantage of this method is that the behavior of each edge transition can
be individually analyzed and constructed. Therefore, it serves as a great analysis tool for
DJ. Contrarily, a major drawback of real-time oscilloscope is that it does not have a high
frequency bandwidth.
Time Interval Analyzers (TIA)
A Time interval analyzer (TIA) uses many single-shot edge-to-edge timing
measurements to acquire the timing information, rather than extrapolating the signal
samples picked up. TIA has the ability to operate with or without the presence of a pattern
marker (or clock). Spectrum analysis can be performed on the data set acquired by a TIA
[25]. TIA is known for its fast operation as it only requires edge timing information. Jitter
components can be reliably separated with the help of a hardware-based pattern marker.
56
TIA is also known as counter timers and signal integrity analyzers that measure jitter
using a statistical approach. By measuring hundreds, thousands or even millions of signal
periods, or the time between the signal and some reference, TIAs have the ability to
measure jitter with a fair amount of accuracy, depending on the quality of the time-base,
and the resolution of the counters used. This is mainly because it measures millions of
signal periods to calculate the time between data signal and reference clock signal.
A major drawback of TIA is that it tends to under-sample the signal and therefore,
it is not capable of measuring cycle-to-cycle period or phase change over time [36]. Jitter
having lower frequencies can more than likely appear as jitter frequencies of higher
magnitude, which could possibly lead to an improper inference about jitter sources. The
other drawback is the aliasing caused at frequencies below 1 MHz due to under-sampling
makes it a bigger problem as compared to 20 GHz (Nyquist for current 40GSa/s
oscilloscopes) [36].
Bit Error Ratio Tester (BERT)
BERT is commonly used to produce modulated data patterns, validate these data
patterns, and compute errors. BERTs are known for their accurate timing circuits which
gives them the ability to measure very small amounts of jitter with reasonable accuracy. It
measures the bit error-rate of a signal at a specific point in the signaling interface. BERT
comprises of both source and measurement modules. It sends data packets through a
device under test (DUT), and compares it to the data received at the receiver. The source
57
unit is known as the “Pattern generator” while the measurement hardware is termed as
the “Pattern detector”. The pattern generator can achieve data rates ranging from kilobits
per second (kb/s) to hundreds of gigabits per second (Gb/s). The errors detected are
recorded in reference to the total number of bits generated.
For a known bit pattern, the pattern detector is solely capable of monitoring data
signals coming from a transmitter under test, provided a synchronization signal is available.
In some BERTs, the synchronization can be via encoded header data [25].
BERT uses a bathtub plot for measuring jitter. The BER thresholds of a bathtub
curve are related to the Q-factor. The Q-factor decides the amount of RJ that spreads into
the eye diagram from both sides and it is represented as:
𝑄(𝑡) =
𝜇 − 𝑡
𝜎 (33)
where t is the random variable, µ is the mean, and σ is the standard deviation [56]. The
BER, Q-factor and Gaussian PDF can be related as shown below:
𝐵𝐸𝑅 = ∫ 𝑔(𝑡)
𝑡
−∞
dt =1
2𝑒𝑟𝑓𝑐(
𝑄
√2) (34)
In the above equation, erfc() is the complementary error function.
As Q-factor is a function of BER, and as BER decreases, the bathtub opening
becomes narrower. The flat region in the bathtub plot represents DJ, while the slope of
the bathtub is caused by the Gaussian RJ.
58
BERT measures the BER by varying the sampling instant with respect to the clock
edges over the bit period. BERT moves the sample point in fixed steps in order to perceive
the position of the signal with respect to a threshold. The position of signal above or below
this threshold signifies the presence of jitter. Measuring many thousands of edges this way
builds a substantial sample set on which statistics are used to determine the standard
deviation and peak to peak changes in edge timing. BERT needs significantly long test times
to measure a low BER (up to hours for 10-12). It may take hours to measure for a 10-12 BER.
Therefore, better accuracy is achieved when measurements are performed for longer
durations as it yields lower BER.
One drawback of BERT is that the practical test time constraint often confines its
performance. BERTs tend to have large price tags, and test times are typically on the order
of dozens of minutes for scans, and hours for true measurements. Although BERT is
beneficial at performing the task of BER tests, it does not match the versatility offered by
Figure 3-2. Bathtub Curve in reference to DJ, RJ and Eye Diagram [58]
59
real-time oscilloscopes. Extrapolation of RJ and DJ from TJ is only possible with dual-Dirac
assumption of DJ PDF. Due to this approximation, DJ results are generally pessimistic.
Recent Techniques
Tail fit Algorithm
Deterministic jitter is bounded and beyond a certain jitter range; the PDF solely
corresponds to random jitter process [57]. Previously, it was extremely difficult to calculate
the RJ in complicated histograms. It was mainly due to the complex shapes of TJ histogram.
Hence, it is imperative to identify and isolate the different components contributing to
total jitter for efficient jitter analysis [25]. The portion of total jitter PDF where Gaussian
process is most dominant is typically the tail regions. Tail fit algorithm is one of the earlier
algorithms that is effective in measuring RJ because it successfully manages to segregate
the Gaussian tails of RJ from complicated, non-Gaussian distributions. [58].
Typically, a generic Gaussian form is used to match the tail portion of a PDF with
the help of some optimization technique like the least-square fit method which helps in
determining the parameters (mean and standard deviation) defining a Gaussian
distribution. The quality of the tail fit is evaluated by chi-squared (χ2) which is used as a
gauge. χ2 is a robust iterative process which requires some suitable initial parameter values
in order to converge after the iterations [58].
60
Peak Distortion Analysis (PDA)
Peak distortion analysis is a technique used to evaluate the peak jitter and noise
caused by deterministic sources such as crosstalk and ISI [2], [3]. In this analysis, the peak
distortions caused by interference sources gives rise to worst-case values, voltage, and
timing margins. These values are estimated using the principle of superposition [13]. The
worst-case values are then used to extract a worst-case eye representation [16], [59], [60],
[61], [62]. This representation further enables the extraction of the peak sampling
boundary. PDA estimates
Considering the interconnect system to be linear time-invariant (LTI), the
superposition property can be employed in this case. Based on superposition property, a
train of pulses representing a system input in the time domain can be expressed as the
sum of its individual input components in the time domain. This is denoted as:
𝑥(𝑡) = ∑ 𝑥𝑗(𝑡)
∞
𝑗=0
(35)
Similarly, the system output is the algebraic sum of output values for each
particular input component. This is shown below as:
𝑦(𝑡) = ∑ 𝑓[𝑥𝑛(𝑡)] = ∑ 𝑦𝑛(𝑡)
∞
𝑛=0
∞
𝑛=0
(36)
The equation above is used to calculate the received signal waveform for an
arbitrary bit pattern using only the response of the system to a single pulse enabled by the
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concept of superposition [3]. 𝑥(𝑡) over a unit interval (UI) is represented as 𝑥𝑗(𝑡), where j
signifies the index number of UI and UI is equal to the width of each data interval [3], [13].
An example to illustrate the application of superposition is presented below. This
example involves the summation of two pulse responses, each of them consisting of the
same number of data bits, such that each data bit of the first pulse response is added to
the respective data bit of the second response.
Thus, a cumulative waveform pattern of 001010000 is formed, based on the
principle of superposition, wherein the two pulses (001000000 and 000010000) are
summed at respective data points.
For a transmitted pulse at 𝑗th bit position having a pulse shape of 𝑝(𝑡), is expressed
as,
𝑥𝑗(𝑡) = 𝑥(𝑡 − 𝑗. 𝑈𝐼)𝑝(𝑡) (37)
This equation can be rewritten for an n-bit data sequence of the transmitted
signal with 𝑏𝑗 representing the logical value of the bit in jth location of the data sequence
as shown below,
𝑥′(𝑡) = 𝑏𝑗𝑥(𝑡 − 𝑗. 𝑈𝐼)𝑝(𝑡) (38)
Therefore, the mathematical model of the received signal for the same n-bit data
sequence using the superposition principle is defined as,
𝑦′(𝑡) = 𝑏𝑗𝑦(𝑡 − 𝑗. 𝑈𝐼)𝑝(𝑡) (39)
The equation above represents the response of an individual bit shifted in time by
an equal amount of its respective bit position multiplied by the UI. This, in turn,
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represents the cumulative response of the waveform observed at the receiver’s output,
by theory of superposition.
63
CHAPTER 4. EFFICIENT IMPLEMENTATION OF LINK ANALYSIS
The term, jitter is used for digital signal waveforms; however, its causes and effects
are analog in nature. The transmitter sends out information in the form of binary data bits
as a stream of random 1s and 0s. Ideally, these bits should exist for a strict predetermined
period, at an exact timing instant. They should also have uniform levels of high and low.
However, designers are working very hard to overcome the factors impacting the signal
quality of transmitted data, which leads to the source of this high frequency quantity,
known as jitter [6].
Jitter analysis is all about bit errors. It is analogous to signal to noise ratio (SNR),
where SNR defines the result of voltage noise on a signal. Voltage noise causes bit errors
when there are fluctuations in signal voltage, vertically across the sampling point.
Correspondingly, jitter causes errors when there is fluctuation in the timing instants,
horizontally across the sampling point.
In a system, there must be no more than one error for every trillion bits
transmitted. This basically indicates that the BER must be below 10-12. Then, the cumulative
effect of all sources of jitter in the system should be evaluated such that the total jitter at
a BER 10-12 is less than the bit period of the data stream [11].
Traditionally, link analysis was based on empirical simulations and worst-case
analysis. Peak Distortion Analysis (PDA) is a worst-case link analysis method, which helps
in determining the worst-case eye from the channel response systematically, bypassing
the need for time intense simulations.
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However, with the strong interaction between various link components
(transmitter, channel and receiver), the link complexity tends to increase which makes it
unfeasible to use SPICE-like time domain simulators to model the entire system. In high-
speed links, the outcomes of a worst-case analysis observed due to worst-case effects of
several noise and interference sources are merely superimposed and they tend to be
exceedingly distrustful, especially for PAM-4 and Duo-binary modulation schemes.
Therefore, to overcome the drawbacks of empirical-based and worst-case analysis
methods, researchers have been increasingly using statistical tools to analyze links [7].
This analytical approach gives the statistical performance metrics by accounting for
all significant interference and noise sources. Even for extremely low target BERs, statistical
analysis facilitates computationally efficiency in validation and performance
characterization for models of various key components in a link.
HashMap is a data structure that facilitates data access and retrieval using a
corresponding key. It is a key-value data structure. Keys and values can both comprise of
real numbers, text strings and several other data types [63]. Each value in a HashMap is
associated with a particular key, whereas in case of arrays, each value is associated to its
index in the array. HashMaps provide an advantage over arrays for cases where a value
needs to be accessed by its key, rather than by its position. Therefore, for a key-value pair,
HashMaps offer an average runtime complexity of constant time 𝑂(1) to access its
individual values. Conversely, for an unordered array, sequential search has a worst-case
running time that is linear 𝑂(𝑁) in the size of the array. Furthermore, if the unordered
array pairs are sorted, a binary search can be applied instead of a sequential search. This
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would significantly improve the worst-case running time complexity from linear to
logarithmic 𝑂(𝑙𝑜𝑔𝑁).
In this methodology, HashMaps are employed after each convolution. These
HashMaps assimilate new voltage values so as to filter out repeated values and maintain
uniqueness. This uniqueness in voltage values is extremely crucial before probability values
are assigned to each of these voltage values, so as to maintain a one-to-one
correspondence and avoid ambiguity. Under the laws of probability, a quantity ‘x’ cannot
have a more than one probability assigned to it.
Along with exclusion of repeated voltage values, HashMap simultaneously adds up
probabilities of these voltage values and assigns it to the first occurrence of each voltage
value formed as a result of the convolution. For example, consider two arrays ‘A’ and ‘P’
such that each element of ‘A’ represents a voltage value while each element of ‘P’
represents corresponding probabilities for the occurrence of each voltage value.
𝐴 = [2, −3, 2, 0, 3, 4, −3, 2, 4]
𝑃 = [0.125, 0.125, 0.125, 0.125, 0.125, 0.125, 0.125, 0.125, 0.125]
With the help of HashMaps, elements in ‘A’ that appear more than once are eliminated
and their corresponding probability values are added and linked to the first occurrence of
each element. The structured array represents ‘A’ and ‘P’:
𝐻𝑀. 𝐴 = [2, −3, 0, 3, 4]
𝐻𝑀. 𝐵 = [0.375, 0.25, 0.25, 0.125, 0.125, 0.25]
This contribution of HashMaps to this algorithm can be evaluated by comparing it
to an implementation involving the use of loops to perform the same task. Initially, a couple
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of nested for-loops are required to parse through each element of the voltage array and
to compare it with every other element of that array in order to detect duplicity of values.
Additionally, the position of occurrence of each elements has to be taken into
consideration such that the probability values can be computed correspondingly.
The “Bin Multiplication” implementation [13], [17] encompasses five additional
intermediary steps, thereby, increasing the lines of code significantly. The first of these
steps is the formation of bins by rounding off each voltage value within a fixed range. The
next step involves assignment of probabilities to the bins. This is followed by the extension
of each bin such that the voltage value is located in the center of every bin. The next step
involves truncation of leading and trailing zeros in a probability array. The final additional
step is storing the elements of these truncated voltage and probability arrays from the
previous step into new arrays.
None of the steps mentioned above are required in the HashMap implementation.
In this implementation, each voltage value has a quantifiable probability value. Voltages
having zero probability of occurrence are not considered in the computation. Therefore,
the use of HashMaps avoids redundancy and provides compactness in this portion of the
code.
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CHAPTER 5. HASHMAP METHODOLOGY
This section describes the implementation of a statistical based approach so as to
quantify the prevailing interference and noise sources. This analysis will help us depict the
performance of a link in terms of a statistical eye diagram. The eye diagram represents
BER of the link with respect to its corresponding sampling offset in voltage and time
domains. In addition to linear time-invariant (LTI), there are some other significant
assumptions that should be considered for this analysis. They are listed below:
A) The data transmitted as a binary bit sequence must be independent as well as identically
distributed. It must also be independent of the data being sent over other channels. In
other words, there must be no correlation or periodicity within individual bits and
subsequent sequence of bits. At the same time, both 0s and 1s must be well-distributed
across the entire bit sequence [7].
B) Distributions of jitter must be stationary as well as independent of the data sequence.
The flow diagram for this analysis is outlined in the figure 5.1. The first step involves
the determination of distributed probability samples at the receiver. This receiver
distribution is a combination of transmitter jitter and ISI in the link. These two signaling
impairment quantities are taken into consideration as they cannot be tracked by the
receiver [30]. Therefore, segment-based analysis can be applied to acquire receiver jitter
samples described in [7], [30].
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Inter-Symbol Interference (ISI) Recursive Convolution
A Simulink based model was used to generate a distorted pulse response with ISI
induced for high and low transition. The inputs with high and low edge were formed using
components of a Fourier series [13]. These inputs further underwent quantization followed
by sifting with multiple pole-zero all-pass filter. This produces an ISI distortion by injecting
significant delays to certain frequencies, without attenuation. The filtered outputs were
then stored in the MATLAB workspace. Based on the received output, the deviation
observed in samples, from the ideal values of 0 and 1, are considered as ISI distortions.
Figure 5-1. Statistical Signaling Analysis Flowchart [7]
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Figure 5-2 above gives rise to simulated ISI pulse response with voltage in Volts (V)
for low and high signal values, for a total of five segments, with each segment having five
sample points. In order to form the ISI PDF, these voltage values are converted from Volts
(V) to millivolts (mV) for every sample point of their respective segments. The process of
ISI PDFs modeling is based on a commonly used convolution technique. This method of ISI
distribution is derived from a sampled single-bit pulse response, and it is computed on the
basis of recursive convolution of individual ISI PDFs. Recursive convolution is a valid
approach provided that the data in ISI PDFs is random and uncorrelated [3], [30].
The ISI PDF is computed for the binary levels, high and low, of each segment.
𝑇𝑜𝑡𝑎𝑙 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑠𝑒𝑔𝑚𝑒𝑛𝑡𝑠 = 5
Figure 5-2. Simulink diagram for generation of ISI pulse response [11]
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These PDFs are formed by a technique of progressive convolution of the PDFs for all ISI
cursors in a given segment. In other words, the PDF of each ISI cursor is convolved with the
PDF of its neighboring ISI cursor.
The aggregate PDF then convolves with the PDF of succeeding ISI cursors. This
process concludes when all the ISI cursor PDFs have been convolved with each other to
form a final ISI PDF for that particular segment, and transition state. This process does not
include the main cursor’s PDF, as the main cursor is devoid of ISI.
Figure 5-3. ISI cursors and Main cursor
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Figure 5-4. Recursive Convolutions of ISI PDFs
Here is an example to elucidate this technique of progressive convolutions for ISI
cursor PDFs. Consider figure 5.5 (ISI cursors and a main cursor) for Segment 1, high
transition state. Initially, each ISI cursor forms a PDF with a 50 percent probability for
positive voltage and the remaining 50 percent for negative voltage, based on the
assumption of equal probability [2]. In this example, the voltages for ISI cursors are -3.3671
mV, 7.7217 mV, 26.7407 mV, and 34.3529 mV respectively.
In the figure below, the PDF of ISI cursor 1 has probabilities of 0.5 at -3.3671 mV
and 3.3671 mV each. On the other hand, ISI cursor 2 has a PDF with probabilities of 0.5 at
-7.7217 mV as well as 7.7217 mV each.
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These two ISI cursor in the figures above convolve with each other to form a four
ISI cursors, that is 1st cursor * 2nd cursor, as shown in the figure below. This process
assumes a random bit pattern, and therefore there is an equal probability that any
individual bit is either 0 or 1.
The four resultant ISI cursors convolve with the 3rd cursor’s ISI PDF. The 3rd cursor
has occurrence of equal probability at -26.7407 mV and 26.7407 mV, as shown in the figure
5.10. The resultant of this convolution yields eight ISI cursors, each having the same
Figure 5-6. ISI Cursor 2 PDF Figure 5-5. ISI Cursor PDF 1
Figure 5-7. PDF of 1st Cursor * 2nd Cursor
Figure 5-8. ISI Cursor PDF 3
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probability of 0.125. The same procedure of convolution follows for resultant ISI cursors
with 4th cursor (figure 5.11) and this gives the final ISI distribution shown in the figure 5.12.
Figure 5-11. PDF of 1st Cursor * 2nd Cursor * 3rd Cursor * 4th Cursor
Figure 5-10. ISI PDF Cursor 4 Figure 5-9. PDF of 1st Cursor * 2nd Cursor * 3rd Cursor
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This process is generally time-consuming with large number of cursors [2].
However, employing well-organized functions along with divide-and-conquer approach
[64] helps achieve optimum performance, in terms of timing and computations.
Transition PDF (TPDF)
This section involves the interaction between ISI and transmitter (TX) jitter with
random and uncorrelated distributions. At higher frequencies, TX jitter modulates the TX
symbol-widths, which tends to increase the amount of ISI in the links. ISI further combines
with the TX jitter to form a damaging signal impairment that is generally not perceived by
the receiver, and this causes a detrimental effect on the BER performance of the link [7].
This implementation involves the computations of individual UIs contributing to the
signal’s impairment, followed by their amalgamation in order to realize the cumulative PDF
at the receiver’s end. This approach of segment-based analysis involves the division of
transmitted data streams into segments such that they are centered on transitions as
shown in the figure below:
Figure 5-12. Flow chart of TX Jitter and Channel ISI Combining to Form RX Distribution [7]
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The cue is to compute the contributions of each UI and have their aggregate
distribution combined with samples at the receiver end [7]. The contribution of each
segment to the cumulative sample forms a PDF. This combined PDF is known as the
Transition PDF (TPDF) in [30]. Using this procedure, transition PDF (TPDF) of all pre-cursor
and post-cursor segments is sequentially calculated to acquire a cumulative receiver PDF.
Figure 5-15. Jittery Transitions within Each UI [30]
Figure 5-13. Jitter PDF * ISI PDF = TPDF [7] Figure 5-14. UI-based analysis - ISI and TX jitter computation to form Transition PDF [7]
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As shown in the figure 5-14, the UIs considered for this analysis contain a significant
amount of edge jitter for transitions occurring from one binary logic level on the left half
of unit interval (UI) to the opposite level on the right half of UI.
In order to aptly account for TX jitter, adjacent segments are combined to form a
composite PDF which includes the effects of both ISI and TX jitter. The four possible
transitions in a binary NRZ signaling scheme and their respective PDFs are illustrated in
figures 5-15 and 5-16. Transitions that involve different bit levels, such as 0 – 1 and 1 – 0,
are assigned a TX jitter PDF of five samples, based on figure 5-17. On the other hand,
transitions between the same logic levels such as 0 – 0 and 1 – 1 are assumed to be free
from TX jitter [12], [30]. By the definition of PDF, area under the curve must have a
probability of unity. Therefore, same logic level transitions are assigned a sample value
having a probability equal to 1, at center of the plot. This is displayed in the figure 5-18.
Figure 5-16. Transitions between Different Logic Levels
Figure 5-17. Transitions between Same Logic Levels
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At segment #2, the ISI PDF for bit level - 0 (figure 5-19) is convolved with TX jitter PDF
transitioning to the same bit level, such as 0 - 0 or 1 - 1 (figure 5-18), to form a resultant
TPDF as shown in figure 5-20.
Figure 5-18. TX Jitter PDF for 0 - 1 and 1 - 0 Transitions
Figure 5-19. TX Jitter PDF for 0 - 0 and 1 - 1 Transitions
Figure 5-20. ISI PDF for Segment #2 and Bit level - 0
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Correspondingly, when the same ISI PDF (figure 5-18) is convolved with TX PDF such
that it transitions to the opposite bit level, 0 – 1 or 1 – 0, then the intermediate TPDF
Figure 5-21. TPDF for Segment #2, Transition level - 00
Figure 5-22. TPDF for Segment #2, Transition level - 01
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formed is displayed in figure 5-21. On comparing figures 5-20 and 5-21, it can be deduced
that the PDFs tend to have a wider spread in the presence of TX RJ PDF consisting of 5
samples (figure 5-17).
Mean – Convolve Algorithm
The figure above thoroughly explains each step of the segment combination. There
are four transition levels, 0 to 0, 0 to 1, 1 to 0, and 1 to 1, for all pre-cursor and post-cursor
segments of a binary non-return to zero (NRZ) signal, without transmitter pre-emphasis.
The algorithm starts from the last post-cursor segment and at every step, the transition
PDFs of that particular segment are averaged as shown above, followed by a convolution
with TPDFs of the neighboring segment. For instance, the TPDFs of the last (Post-cursor
#2) segment corresponding to ‘00’ and ‘10’ are averaged with each other and similarly, ‘01’
Figure 5-23. Mean - Convolve Algorithm for RX PDFs [7], [30]
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and ‘11’ follow suit. These two averaging steps form two intermediate TPDFs named as
‘X0’ and ‘X1’ in [7], [30].These two TPDFs, ‘X0’ and ‘X1’ are then convolved with
corresponding TPDFs of Post-cursor #1, such that, ‘X0’ convolves with ‘00’ and ‘01’ while
‘X1’ convolves with ‘10’ and ‘11’ respectively. Similarly, the same amalgamations take place
for pre-cursor segments. This course of alternatively averaging and convolving converges
at post-cursor’s segment #0 and pre-cursor’s segment #-1 just before the combination of
TPDFs approach with the cursor position on either side (pre-cursor and post-cursor). The
next step involves the convolution of intermediate TPDFs ‘X0’ on the post-cursor’s side
with ‘0X’ at pre-cursor’s side resulting in a PDF of receiver’s bit ‘0’, at the cursor position.
On the other hand, convolution of TPDFs ‘X1’ with ‘1X’ gives rise to receiver’s bit ‘1’ PDF,
at the cursor position. The two TPDFs possess the contributions of each segment in the
analysis that will tend to have an effect on the cursor position [7], [12].
As shown in the figure 5-23, each segment (post-cursors and pre-cursors) has four
transition-levels: 00, 01, 10, and 11. Each of these transition-levels corresponds to a TPDF
which comprises of their discrete voltage and probability values. These values are stored
as structure arrays.
Structure array also known as ‘struct’, is a MATLAB data type commonly used to
store heterogeneous data. A structure array is a container that groups related data using
smaller data containers called fields. Each field can contain any type of data. It consists of
multiple fields of the same dimension such that the properties of each field in the structure
array are linked to one another. A structure array facilitates a direct correlation between
each element of two or more cell arrays having the same dimension. In this section, each
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PDF corresponds to list of voltages with a probability value associated with each of them.
In structure arrays, data is accessed using a dot operator. For example,
RJ − PDF (1). Voltage = [−2, −1, 0, 1, 2]
𝑅𝐽 − 𝑃𝐷𝐹 (1). 𝑃𝑟𝑜𝑏𝑎𝑏𝑖𝑙𝑖𝑡𝑦 = [0.1, 0.2, 0.4, 0.2, 0.1]
RJ-PDF is the name of ‘struct’, Voltage and Probability are field names and 1 is the
location of ‘struct’ that is being accessed.
Mean of TPDFs
At the post-cursor’s end, the first stage of the algorithm involves the averaging of
TPDFs transitioning to the same bit-level in order to the form intermediate levels for the
next stage of the algorithm. In other words, transition-levels having the same successive
bit are averaged to form two new TPDFs. For instance, 00 is averaged with 10 to form a
TPDF ‘X0’ while 01 is averaged with 11 to form ‘X1’. Contrarily, on the pre-cursor’s end, the
TPDFs of a particular segment having the same preceding bit are averaged with each other
to form intermediate stage TPDF. For example, 00 is averaged with 01 leading to the
formation of ‘0X’, whereas 10 is averaged with 11 to give rise to ‘1X’.
The procedure of averaging two TPDFs implies that probability values undergo
averaging while their corresponding voltage values are retained. In this process of
averaging, probabilities that are associated with common voltage values are added to each
other such that these common subset of voltage values are retained. This is a vital step to
avoid duplication of voltages in the intermediate PDF. All other probability values and their
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accompanying voltage values are included in the intermediate TPDF probability and
voltage arrays respectively. These probability values are then averaged, whereas the
voltage values are sorted ascendingly along with their respective probabilities.
This can be better explained with the help of an example. Consider two PDFs, ‘A’
and ‘B’ such that each of these include a list of probability and voltage values. If these
datasets have the following values: probabilities of A = [0.3333, 0.3333, 0.3333], voltage
(in mV) values of A = [-1, 0, 1], probabilities of B = [0.3333, 0.3333, 0.3333] and voltage
values of B = [-2, 0, 2], then the two TPDFs are displayed in the figures 5-20 and 5-21.
Figure 5-24. TPDF of A Figure 5-25. TPDF of B
Figure 5-26. Intermediate PDF
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When TPDFs of A and B are averaged with each other, the resultant PDF is an
intermediate stage having probabilities = [0.1666, 0.1666, 0.3333, 0.1666, 0.1666] and
corresponding voltage values = [-2, -1, 0, 1, 2].
Convolution of TPDFs
Convolution plays a significant role in combining the cumulative signal distortion
effects observed in two or more PDFs. It is extremely useful in gathering the cumulative of
distortion contributed by the bits neighboring the cursor. The concept of convolution is
often explained as a “flip” and “shift” operation. However, a more analytical way to
comprehend convolution involves the use of two basic arithmetic operations of
multiplication and summation. Convolution is a process between two arrays of multiple
elements wherein each element of an array is multiplied with every element of the other
array and the position of each element of one array is summed with the position of every
element in the other array.
In this research, arrays correspond to PDFs, elements of the array correspond to
probability values encompassed in the PDF and the position of these probabilities
corresponds to voltage values. The multiplication of probabilities is performed using
Kronecker tensor product. In MATLAB, Kronecker tensor product can be performed with
the help of “kron” function [63]. This method is the most efficient way of complete
multiplication of two arrays such that each element of the first array is multiplied with
every element of the second.
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After multiplication of probabilities, the next step of convolution involves the
summation of all corresponding voltage values present in these two arrays. For summation
of voltage values, Kronecker tensor product is used after the application of some basic
calculus. The calculus applied comprises of an exponential identity and the duality property
of natural logarithms.
The exponential identity used in this section is the product of two exponential
values is the sum of their powers. For example:
𝑒𝑎. 𝑒𝑏 = 𝑒𝑎+𝑏 (40)
By means of this exponential identity, the exponential values of voltage for both
arrays are taken into consideration. The exponential values are then multiplied such that
each element of one array is multiplied with every element of the other array with the help
of “kron”. The resultant array contains the exponential values of the summation of both
arrays. This step is followed by the duality property which is better known as, canceling
exponential property, wherein the natural logarithm of an exponential value results in the
cancelation of logarithmic and exponential terms, leaving behind the value itself. For
instance:
log𝑒 𝑒𝑥 = 𝑥 (41)
Therefore, the natural logarithm of the exponential resultant leaves behind the
summation of the initial two voltage arrays.
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MATLAB also has a direct function for convolution called ‘conv’ [63]. This function
performs a similar task, however, it does not retain the x-axis values corresponding to each
amplitude (or y-axis value). MATLAB’s ‘conv’ performs convolution between elements of
two arrays, based on their respective index locations in the array. Therefore, ‘conv’ was
not a preferred option for this operation.
While carrying out the process of convolution, it is extremely critical to eliminate
duplicity of voltage values in an array. This issue of duplicate voltages can lead to erroneous
computations because duplicate voltages will have multiple probability values associated
with it which is not possible according to the rules of probability. For instance, if the two
voltage arrays are A=[-15,-5,5,15] and B=[-20,-10,10,20], then the summation of each
element of A with every element of B would result in an array, C = [-35,-25,-5,5,-25,-15,-
5,15,-15,-5,15,25,-5,5,25,35].
As observed, C has several repeated terms such as, -25,-15,-5, 5, 15, and 25. This
issue of duplicity can be resolved by combining the probabilities of their respective
duplicate voltage values such that only unique voltages persist with a corresponding
probability value. From the previous example, after combining the probabilities, the
resultant array should be Resultant-C = [-35, -25,-5, 5,-15, 15, 25, 35].
This elimination of redundant voltage values is achieved with the help of Java
HashMaps in MATLAB. HashMaps possess the property of relating data to corresponding
keys. The voltages correspond to keys of the HashMap. Each voltage value is accessed for
its uniqueness verification. If a voltage value is unique, it is stored as the key along with its
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corresponding probability value. On the other hand, if a voltage value is being repeated,
its probability is added to the probability corresponding to the key with the same voltage
value. Hence, repeated voltages are eliminated and their probabilities are added to the
probability of the original element (key) having the same voltage value.
The next step in the algorithm includes a function that maps data into smaller
buckets, without loss of information. This method is known as the tuning portion of the
algorithm due to its ability to define the accuracy required. After undergoing numerous
computations, the size of PDFs increases exponentially. This makes future computations
very cumbersome and time consuming. Mapping reduces the length of PDFs to a fixed
number of buckets with the help of an array. This implementation involves the use of arrays
over HashMaps, based on its computational simplicity and speed of execution.
Mapping function is invoked when the size of a particular PDF exceeds a set number
of buckets. In such circumstances, the large-sized PDF is mapped to a PDF having a set
number of buckets. The equation representing bucket size is:
𝐵𝑢𝑐𝑘𝑒𝑡 𝑠𝑖𝑧𝑒 =
𝑀𝑎𝑥(𝑉𝑜𝑙𝑡𝑎𝑔𝑒) − 𝑀𝑖𝑛(𝑉𝑜𝑙𝑡𝑎𝑔𝑒)
𝑇𝑜𝑡𝑎𝑙 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑏𝑢𝑐𝑘𝑒𝑡𝑠 (42)
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The maximum and minimum voltage values of a PDF are extracted, so as to find the
range of the PDF. This range is divided by the total number of buckets to find the size of
buckets. Each bucket corresponds to a probability as well as a voltage value. The probability
value is the summation of all probabilities that fall within the bucket size range.
Correspondingly, the voltage value of a bucket is acquired by averaging all voltages that
fall within the scope of that bucket.
Figure 5-27. RX PDF for Bit-0 (Blue) and Bit-1 (Red)
The figure 5-27 represents resultant RX jitter PDFs for bit ‘0’ (blue) and bit ‘1’ (red).
These receiver jitter distributions are formed as a result of the mean-convolve
computations (in figure 5-23) that is contained within this Link analysis implementation.
These PDFs comprise of the aggregate contributions of TX RJ PDFs and channel’s ISI
distributions for neighboring segments, as part of this segment-based statistical approach.
These RX probability distributions for bits ‘0’ and ‘1’ denote the probabilities of detection
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for each of these bits at the receiver’s end. The overlap between these two distributions is
the region where the probability of an erroneous bit being detected is the highest.
Detailed Comparison with Bin Multiplication Approach [13], [17]
The HashMap-based implementation is compared with “Bin Multiplication”
algorithm [13], [17] as both these implementations are based on Intel’s link analysis
methodology [7], [30] for modeling and analyzing jitter in high-speed I/O links.
HashMap-based Technique Bin Multiplication Technique
The first step of this approach involves the
formation of ISI PDFs for all segments by
recursive convolution of individual ISI PDFs
for every sample [3]. This ISI distribution
represents the DJ in the channel. Therefore,
the probabilities contained in these ISI PDFs
contribute to the transmitter’s jitter and
thereby, receiver’s jitter as well. This step is
coherent to Intel’s link analysis algorithm
[7], [30].
The first step of link analysis methodology
is not incorporated in this
implementation. In order words, this
implementation does not form ISI PDFs
with the help of recursive convolutions as
explained in [3]. The ISI voltage samples
are directly used to form bins during
computations, while ISI probabilities are
neither a part of the transmitter’s jitter
nor receiver’s jitter.
The bin range is dynamically determined
during run-time, based on the probability of
occurrences of voltage values.
The bin range is hard-coded to a value of
1.4.
The array consisting of probability values for
a transition taking place between bits on the
same logic-level (high-high or low-low) is
considered ideal (as per link analysis [7],
[30]), such that the transition edge crosses
Same logic-level transition array does not
seem to satisfy the law of PDF, viz.
summation of all probabilities in a PDF
must be equal to unity. It is assumed as an
array having all occurrences having zero
probabilities.
89
the center with the PDF having highest
probability at 0 voltage.
As explained in link analysis [7], [30], a
cursor position must be selected so as to
facilitate pre-cursor and post-cursor
computations for segment analysis.
No cursor position is selected in this
implementation.
PDFs of each segment are convolved with
PDFs of neighboring segments to estimate
the cumulative effect of jitter by both these
segments.
This implementation takes a deviation
from link analysis [7], [30], as the PDFs of
each segment are convolved with PDFs of
every other segment.
Transition PDF convolutions consists of
transition between same-level as well as
different-levels. In other words, jitter
resulting from 0-0, 0-1, 1-0, and 1-1
transitions are considered in this analysis.
Same-level transitions are not considered
in this analysis. This is another aberration
from link analysis’ method [7], [30].
Therefore, there is no computation
between segments having bits
transitioning from 0-0 or 1-1.
Number of functions involved in every
convolution = 3
Each function is crisp, concise, and tidy,
however, the execution time increases as
the number of functions increase.
Number of functions involved for every
convolution = 1
This function is quite lengthy, however, it
saves a lot of execution time due to fewer
function calls and a confined movement
of control between the main script and
function alone.
Execution time of complete algorithm
(including recursive convolution of ISI PDFs)
= 1.20 s
An implementation comparable to Bin
Multiplication approach (without recursive
convolutions) takes around 0.20 s, as most
of the computations are bypassed with the
elimination of ISI’s recursive convolutions.
This approach deviates from Link Analysis,
as it does not take into account the ISI
probabilities assigned to respective
voltage values.
Therefore, the recursive convolution of ISI
PDFs is not a part of this implementation.
This reduces a lot of computation time,
90
however, it significantly undermines the
accuracy of results.
Execution time for this implementation =
0.3125 s.
Table 1: Comparison of jitter analysis methodologies
Non-Linearity in CMOS Receivers
Non-linearity behavior modeling of a system seems to closely match the non-
linearity observed in actual receiver circuits, such as the continuous-time linear equalizers
(CTLE) in high-speed links. Therefore, non-linear modeling is a feasible option to improve
the accuracy of an actual receiver.
A random variable ‘X’ represents the output of a linear system which has a
probability density function of FX(x). If there exists a non-linear function having an input ‘x’
and output ‘y’ such that y = g(x), then the PDF of y can be defined in terms of the FX(x) as
presented in the equation below [14], [65]:
𝐹𝑦(𝑦) =
𝐹𝑥(𝑥1)
|𝑔′(𝑥1)|+
𝐹𝑥(𝑥2)
|𝑔′(𝑥2)|+ ⋯ +
𝐹𝑥(𝑥𝑛)
|𝑔′(𝑥𝑛)| (43)
where g’(x) is the derivative of g(x) and x1, x2,… xn are the n roots of y = g(x), therefore, y =
g(x1) = g(x2) = … = g(xn).
Figure 5-28. Block Diagram of Non-linearity function
91
The block diagram above characterizes a high-speed serial link where x represents
the input signal, y is the output of a non-linear function g(x). FX(x) and FY(y) are the PDFs of
x and y respectively. There are several ways to model non-linearity in circuits. The two most
common approaches include, Volterra series and Power series. Volterra series is more
precise in modeling frequency dependent non-linearity as compared to the power series
method.
Most of the impairments in a typical high-speed serial interface are contributed by
background noise, ISI and jitter in the sampling clocks at the transmitter and receiver. At
the receiver’s end, the signal goes through an analog front end (AFE). The AFE neutralizes
the effect of ISI, however, it boosts the noise and enhances the non-linearity in the system.
The type of receiver considered for this research is CMOS-based. CMOS receivers
are practically used in most high-speed serial interfaces and they play a significant role in
contributing to the non-linearity quotient of the system. Based on the voltage transfer
characteristic of a CMOS receiver, a non-linear model for CMOS receiver’s output voltage
is plotted against the input voltage. This non-linear model is represented by the equation:
𝑌 = −0.7 ∗ tanh (7𝑋) (44)
such that ‘Y’ represents the output of the non-linear CMOS receiver, while ‘X’ represents
the input.
92
In high-speed links, functions are generally monotonic [14]. Monotonic functions
are those that are either always increasing or decreasing.
The shortened PDF of output (𝐹𝑌(𝑦)) is:
𝐹𝑦(𝑦) = |
𝑑𝑥
𝑑𝑦| 𝐹𝑋(𝑥) (45)
With the help of this equation, the output PDF can be estimated based on the information
of input PDF and transfer function of the system. This is because the output PDF is the
cumulative effect of the input PDF and the transfer function (|𝑑𝑥
𝑑𝑦|).
For non-linear CMOS receiver model, 𝑌 = −0.7 ∗ tanh (7𝑋) is given as:
|𝑑𝑥
𝑑𝑦| = |
1
4.9 ∗ sech2(7𝑥)| (46)
Figure 5-29. CMOS receiver’s input–output characteristics
93
𝐹𝑌(𝑦) = |
1
4.9 ∗ sech2(7𝑥)| 𝐹𝑋(𝑥) (47)
such that 𝐹𝑋(𝑥) =1
𝜎√2𝜋𝑒
−(𝑥−�̅�)2
2𝜎2 ; representing Gaussian distribution of AWGN channel.
In figure 5-30, it is prominent that for smaller values of input, the output non-linear
PDF remains unchanged. However, as the input values go on increasing, the ‘companding’
effect of non-linearity is observed towards ± 1 [14].
Implementation of NRZ
In case of linear systems, the output PDF can be calculated by the PDF of the input
and the transfer function of the system. Therefore, the PDF of signal in the presence of
non-linearity is estimated by calculating the PDF of the linear system followed by
concatenation of the linear system with the non-linearity block(s) for the application of
Figure 5-30. Non-Linear PDF Modification |dx/dy|
94
PDF modification formula. The linear system chosen for this research is the Additive white
Gaussian noise (AWGN) channel because of two main reasons:
Once the PDF of the signal which has passed through a combination of linear &
non-linear elements is known, the BER can be determined using tail probability methods
such as Monte Carlo simulations or minimum distance detection rule [14].
The formulation above is validated by using a Simulink model for NRZ (𝑑𝑘 =
[−1 1]) with AWGN channel followed by the non-linearity function.
Figures 5-32 and 5-33 represents the constellation points and PDF plot for NRZ
respectively. These two plots are formed by extracting the output of AWGN and non-linear
model from the Simulink block to the MATLAB workspace using variables ‘simout3’ and
‘simout’ respectively. In figure 5-32, red points indicate output from AWGN while blue
Figure 5-31. Simulink Diagram for modeling Non-linearity in NRZ Signaling Scheme
95
points indicate output from non-linear model. Similarly in figure 5-33, red lines represent
PDF of AWGN channel while blue lines are the PDF of the non-linear model.
Implementation of PAM-4
In recent years, multi-level modulation has been acquiring much attention because
of its superior performance in bandwidth-limited chip-to-chip links. Theoretically, multi-
level signaling or N-level pulse amplitude modulation (PAM) promises to improve spectral
efficiency within a bandwidth constrained channel [7]. Previously, PAM-4 has been
successfully employed in wireless, Ethernet, digital subscriber line (DSL) and backplane
links [66], [67].
Figure 5-32. Data points for NRZ with Non-linearity (Blue)
Figure 5-33. PDF for NRZ with Non-linearity correction (Blue)
96
The formulation above is validated by a Simulink model for NRZ (𝑑𝑘 = [−1 1]) and
PAM-4 (𝑑𝑘 = [−1 −1
3
1
3 1 ]) with AWGN channel followed by the non-linearity function.
Figures 5-35 and 5-36 represents the constellation points and PDF plot for PAM-4
respectively. These two figures below are constructed by isolating the output of AWGN
and non-linear model from the Simulink block to the MATLAB workspace using variables
‘simout3’ and ‘simout’ respectively. In figure 5-35, red points indicate output from AWGN
while blue points indicate output from non-linear model. Similarly in figure 5-36, red lines
represent PDF of AWGN channel while blue lines represent the PDF of the non-linear
model.
Figure 5-34. Simulink Diagram for modeling Non-linearity in PAM-4 Signaling Scheme
97
Consolidation of Receiver PDFs with CMOS Non-Linearity
The previous section dealt with modeling of NRZ and PAM-4 PDFs in the presence
of non-linearity with the help of Simulink blocks. The theory of analyzing effects of non-
linearity is further substantiated in this section. The RX jitter PDFs (figure 5-27) obtained
from the HashMap-based technique are further evaluated to analyze the effect on jitter
distributions in the presence of a non-linear CMOS receiver model.
In Link analysis methodology, one of the basic requirements for the analysis is that
all the components of the system are assumed to be LTI. Therefore, the RX jitter PDFs
acquired from the analysis assumes linearity of receivers. However, in the real world,
Figure 5-35. Data points for PAM-4 with Non-linearity (Blue)
Figure 5-36. PDF for PAM-4 with Non-linearity correction (Blue)
98
receivers are highly non-linear. This non-linearity severely impact the BER and jitter
distribution in high-speed links, thereby, affecting the overall accuracy of the system.
Therefore, it is essential to account for the variations in jitter distributions in the presence
on non-linearity in order to maintain the precision of results obtained from Link analysis.
The non-linearity of CMOS receiver having input-output characteristics shown in
figure 5-29, is considered for this exploration. In this execution, the results of linear RX are
directly linked to non-linear CMOS receiver model. This method of modeling non-linear
behavior in a system is called the power series approach because the linear RX distributions
are concatenated to a polynomial function representing the non-linear model.
The RX distributions that are obtained as outputs after linear system modeling
using the HashMap-based approach are considered for analysis, in terms of probabilities
and their respective voltage values. The output of linear system’s modeling is the input to
the non-linear system 𝑔(𝑋) and it is represented as a random variable ‘X’. Similarly, output
of the non-linear model is a random variable 𝑌 = 𝑔(𝑋), where 𝑔(𝑋) = −0.7 ∗ tanh (7𝑋).
The PDF of input to the non-linear function is 𝐹𝑋(𝑥), while the modified PDF
obtained at the output of the non-linear model is 𝐹𝑦(𝑦). The relationship between the
adjusted PDF that is observed at the output and the linear receiver’s input PDF is
comprehended using the equation (45):
𝐹𝑦(𝑦) = |
𝑑𝑥
𝑑𝑦| 𝐹𝑋(𝑥) (48)
Therefore, the results obtained from HashMap-based implementation are
multiplied to the absolute value of the derivative of non-linear polynomial in terms of the
99
output. The equation (48) facilitates the calculation of modified jitter PDFs in the presence
of receiver’s non-linearity. These altered PDFs are further compared to the original input
PDFs in figures 5-37 and 5-38 so as to assess the difference as a result of this non-linearity.
Figure 5-37. RX PDF for Bit-0 in the presence of non-linearity correction
Figure 5-38. RX PDF for Bit-1 in the presence of Non-linearity correction
100
The effect of this non-linear receiver model is observed on the probability
distributions of bits ‘0’ and ‘1’ in figure 5-37 and figure 5-38 respectively. The original
receiver PDFs are depicted in blue, whereas the corrected PDFs in the presence of non-
linearity are shown in red.
As observed in figures 5-37 and 5-38, the results of modified RX jitter PDFs in the
presence of non-linearity are a replica of the results obtained from simulations in figure 5-
33. Therefore, it can be seen that in the presence of receiver’s non-linearity the PDF of bit
‘0’ and bit ‘1’ have a larger portion of overlap. This increased overlap region in jitter
distributions increases the probability of occurrence of an erroneous bit being detected.
This significantly lowers the BER of the system, thereby, degrading its performance.
101
CHAPTER 6. CONCLUSION AND FUTURE SCOPE
This research offers a robust implementation for modeling jitter in high-speed
serial links with the help of statistical signaling technique. This algorithm statistically
comprehends all the dominant noise and interference sources that detriment the
performance of high-speed links. This analysis provides a statistical approach to account
for the jitter contributed by each and every bit in a signal in a timely manner. The
distributions of each transition in all segments were involved in the computations and the
resultant RX PDF successfully satisfied the property of PDFs, wherein all the discrete
probability values in a PDF, added up to unity.
The efficiency of HashMap-based approach is assessed in terms of the time
required for its execution, inclusion of ISI distributions, and dynamic bucket allocations.
This technique requires only two-thirds of the run-time required by the previous
implementation of Link analysis. The recursive convolution of individual ISI PDFs that is
derived from a sampled single-bit pulse response has been considered for calculating the
ISI distributions for each segment. In the final stages of this implementation, the bucket
positions are dynamically determined at run-time by averaging all the PDF samples
encompassed within each bucket. With all these factors taken into consideration, the
results of RX PDFs obtained are well-defined.
The effect of receiver’s non-linearity was studied in NRZ and PAM-4 schemes. The
non-linear model considered for this simulation was CMOS receiver’s voltage transfer
characteristic preceded by an AWGN channel. The PDFs and constellation points were
102
plotted for NRZ and PAM-4 schemes and the output of AWGN was compared with the
output of non-linearity following it. Having prior knowledge of AWGN’s PDF, the resultant
PDF gives a clear understanding of the modification in PDF introduced by the non-linear
model. Comparing figures 5-32, 5-33, 5-35, and 5-36, it was observed that non-linearity
severely impacts the performance of PAM-4 more than NRZ. Hence, it can be concluded
that non-linearity tends to affect higher order modulations more.
The results from HashMap-based technique were further extended to the CMOS
receiver model for analysis of jitter in the presence of non-linearity. The outcome exhibited
a RX PDF adjustment for bits ‘0’ and ‘1’, are in-sync with the results obtained from
simulations. This PDF alteration in the presence of non-linearity illustrates a larger overlap
in the PDFs bit ‘0’ and bit ‘1’, thereby, increasing the chances of detection of an erroneous
bit at the receiver’s end.
There are several directions to steer this research. This total jitter modeling
algorithm can be implemented for PAM-4 and Duo-binary signaling schemes. Most high-
speed serial links necessitate the use of transmitter pre-emphasis and hence, its presence
can be included in the analysis. Most DJ models are not easily available due to the difficulty
in isolation from other noise sources. More research can be done to extract these PDF
models. These DJ PDF models can then be included in the analysis.
The same RJ PDF is assumed for all different-state transitions (0-1 and 1-0) in each
segment. In reality, the RJ contributed by each transition is dissimilar. Therefore, dissimilar
RJ models can considered for every transition so as to achieve more realistic results.
103
Additionally, RJ PDFs corresponding to same level transitions (0-0 and 1-1) are assumed to
be jitter-free. However, in practice, even same level transitions possess some jitter. Even
though this jitter might be relatively negligible as compared to the jitter contributed by
different level transitions, it must still be considered for more precision in analysis.
The non-linearity correction can be applied to the RX PDFs acquired from the
algorithm. These RX PDFs can be further used to characterize the performance of a link in
terms of a statistical BER eye diagram. This method can be extended to TX pre-emphasis.
Frequency dependent non-linearity in high-speed systems can be tackled in order to
improve the accuracy of analysis. This type of non-linearity can be modeled with the help
of either Volterra series or power series. Besides, the outcomes of static non-linearity can
be used to characterize frequency dependent non-linearity as well.
104
References
[1] G. E. Moore, "Cramming more components onto integrated circuits," Electronics
Magazine, 1965.
[2] Kyung Suk (Dan) Oh, Xingchao (Chuck) Yuan, High-Speed Signaling: Jitter Modeling,
Analysis, and Budgeting, Boston: Prentice Hall, 2011.
[3] Stephen Hall, Howard Heck, Advanced Signal Integrity for High-Speed Digital
Designs, Hoboken, New Jersey: John Wiley & Sons, 2009.
[4] A. Agrawal, "Design of High Speed I/O Interfaces for High Performance
Microprocessors," Harvard University, Cambridge, Massachusetts, October 2010.
[5] Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi, "8Gb/s Capacitive Low Power
High Speed 4-PWAM Transceiver Design," in GLSVLSI, Rhode Island, 2010.
[6] W. Damm, "Jitter – An Introduction," Wireless Telecom Group (www.wtcom.com).
[7] Ganesh Balamurugan, et al., "Modeling and Analysis of High-Speed I/O Links," IEEE
Transactions on Advanced Packaging, 2009.
[8] Anritsu, "Jitter Analysis, Basic Classification of Jitter Components using Sampling
Scopes".
[9] G. Edlund, Timing Analysis and Simulations for Signal Integrity Engineers, Boston:
Prentice Hall, 2008.
[10] Patrick Trischitta, Eve Varma, Jitter in Digital Transmission Systems, Artech House,
1989.
[11] M. Schnecker, "Jitter Measurements in Serial Data Signals," LeCroy Corporation.
[12] Paul Huray, Adam Norman, Bryan Casper and Pelle Fornberg, Jitter and BER Analysis,
University of South Carolina, 2012.
[13] D. Waltman, "Random Jitter Analysis Through the Direct Computation of
Probabilities," The Pennsylvania State University, Middletown, PA, 2010.
[14] Gaurav Malhotra, "Method for analytically calculating BER (bit error rate) in
presence of non-linearity," in DesignCon, 2014.
105
[15] K. B. Nitin Kumar Chhabra, "Mitigating the Impact of Sinusoidal Jitter and Duty
Cycle Distortion on Random Jitter estimation by Tailfit Algorithm," in IEEE, 2013.
[16] Bryan Casper, Matthew Haycock, Randy Mooney, "An Accurate and Efficient
Analysis Method for Multi-Gb/s Chip-to-chip Signaling Schemes," in IEEE
Symposium on VLSI Circuits Digest of Technical Papers, 2002.
[17] Don Waltman, Aldo Morales, Sedig Agili, "A Novel Random Jitter Algorithm for High
Speed Links," in IEEE 15th International Symposium on Consumer Electronics, 2011.
[18] Pavan Kumar Hanumola, Brandy Casper, et. al., "Jitter in High-Speed Serial and
Parallel Links," in IEEE ISCAS, 2004.
[19] John Patrin, Mike Peng Li, "Design and Test for Multiple Gbps Communication
Devices and Systems," International Engineering Consortium, 2005, pp. 411-429.
[20] Teledyne LeCroy, "The History of Jitter,"
http://blog.teledynelecroy.com/2015/03/the-history-of-jitter.html, 2015.
[21] J. Bennett, "Implications of Jitter on a High Speed Serial Interface Standards,
Simulation, and Design," 2004.
[22] A. Healey, C. Morgan, M. Shanbhag, "Beyond 25 Gbps: A Study of NRZ & Multi-
Level Modulation in Alternative Backplane Architectures," in DesignCon, 2013.
[23] Dennis Derickson, Marcus Muller, Digital Communications Test and Measurement,
Prentice Hall, 2008.
[24] Hamed Sanogo, "A Proposed Framework for Measuring, Identifying, and
Eliminating Clock and Data Jitter on High-Speed Serial Communication Links,"
Maxim Integrated Products Inc., 03 March 2010. [Online]. Available:
http://www.maximintegrated.com/en/app-notes/index.mvp/id/4613. [Accessed 19
June 2015].
[25] A. Kuo, T. Farahmand, N. Ou, S. Tabatabeaei, A. Ivanov, "Jitter Models and
Measurement Methods for High-Speed Serial Interconnects," IEEE Test Conference,
ITC, pp. 1295 - 1302, 2004.
[26] IDT, "Understanding Jitter Units - Application note, AN-815," San Jose, 2014.
[27] Rohde, Schwarz, "Phase Noise and Jitter Measurements," in DesignCon, Santa
Clara, 2013.
106
[28] Maxim Integrated, Tutorial 3631, "Random Noise Contribution to Timing Jitter—
Theory and Practice," 25 September 2005. [Online]. Available:
http://disp01.maximintegrated.com/en/app-notes/index.mvp/id/3631. [Accessed
29 June 2015].
[29] "TUTORIAL 3631: Random Noise Contribution to Timing Jitter—Theory and
Practice," 25 September 2005. [Online]. Available:
http://disp01.maximintegrated.com/en/app-notes/index.mvp/id/3631. [Accessed
29 June 2015].
[30] Ransom Stephens, Tektronix Jitter 360° Knowledge Series, "The Meaning of Total
Jitter," [Online]. Available:
http://www.ransomsnotes.com/index_htm_files/RansomStephensAndTektronixJitt
er360.PDF. [Accessed 24 June 2015].
[31] Ronnie Neil, "Understanding Jitter and Wander Measurements and Standards -
Technical Note No. 5988-6254EN," Agilent Technologies, 2003.
[32] B. Casper, G. Balamurugan, J. Jaussi, J. Kennedy, M. Mansuri, F. O'Mahony, E.
Mooney, "Future Microprocessor Interfaces: Analysis, Desing and Optimization," in
IEEE Custom Intergrated Circuits Conference (CICC), pp. 479 - 486, Hillsboro, 2007.
[33] Bryan Casper, Frank O’Mahony, "Clocking Analysis, Implementation and
Measurement Techniques for High-Speed Data Links—A Tutorial," IEEE
Transactions on Circuits and Systems, vol. 56, no. 1, pp. 17-39, January 2009.
[34] Prof. Steve Long, "Phase Locked Loop Circuits," University of California ECE Dept.,
Santa Barbara, 2005.
[35] SiTime Corporation (SiT- AN10007 Rev 1.2), "Clock Jitter Definitions and
Measurement Methods," January 2014. [Online]. Available:
www.sitime.com/support2/documents/AN10007-Jitter-and-measurement.PDF.
[Accessed 9 July 2015].
[36] Maxim Integrated Products, Inc, "Application Note 2744: Jitter Measurements for
CLK Generators or Synthesizers," 26 Sep 2003 . [Online]. Available:
http://www.maximintegrated.com/en/app-notes/index.mvp/id/2744. [Accessed 10
July 2015].
[37] National Instruments, "Understanding and Characterizing Timing Jitter," White-
paper 14227, 17 April 2013.
107
[38] Tektronix, "Jitter Analysis: A Brief Guide to Jitter," September 2005. [Online].
Available:
http://anlage.umd.edu/Microwave%20Measurements%20for%20Personal%20We
b%20Site/Tek%20Intro%20to%20Jitter%2061W_18897_1.PDF. [Accessed 28 June
2015].
[39] Mike Peng Li, Jitter, Noise and Signal Integrity at High-Speed, Westford,
Massachusetts: Prentice Hall, 2007.
[40] "MtronPIT's Oscillator Jitter Basics," MtronPTI.
[41] Mike Peng Li, Design and Test for Multiple Gbps Communication Devices and
Systems, Chicago, Illinois: IEC Publications, 2005.
[42] B. Ahmad, "Performance Specification of Interconnects," in IEC DesignCon, 2003.
[43] D. Carney, E. Chandler, "Error Correction Coding for a Serial Digital Multi-Gigabit
Communication System," in EIT IEEE, Milwaukee, 2004.
[44] Daniel Chow , "Jitter's faces: Random, periodic, and ISI," 13 October 2013. [Online].
Available: http://www.edn.com/design/test-and-measurement/4423552/See-
jitter-s-faces--Random--periodic--and-ISI. [Accessed 13 July 2015].
[45] Nelson Ou, Touraj Farahmand, Andy Kuo, Sassan Tabatabaei, and André Ivanov,
"Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects," Design
& Test of Computers, IEEE (Volume:21, Issue: 4 ), pp. 302 - 313, 26 July 2004.
[46] S. Palermo, "ECEN720: High-Speed Links Circuits and Systems - Lecture 10: Jitter,"
Analog & Mixed-Signal Center, Texas A&M University, Spring 2015. [Online].
Available:
http://www.ece.tamu.edu/~spalermo/ecen689/lecture10_ee720_jitter.PDF.
[Accessed 19 June 2015].
[47] Maxim Integrated Products, Application Note HFAN-04.0.3, "Jitter in Digital
Communication Systems, Part I," April 2008. [Online]. Available:
http://PDFserv.maxim-ic.com/edad5hfan403.PDF. [Accessed 23 June 2015].
[48] Adam Healey, Chad Morgan, "A Comparison of 25 Gbps NRZ & PAM-4 Modulation
Used in Legacy & Premium Backplane Channels," TE Connectivity, 2012. [Online].
Available: http://www.te.com/documentation/electrical-
models/files/papers/DC2012_CM.PDF. [Accessed 19 June 2015].
[49] D. McCallum, "UXPi favors NRZ signaling scheme," EE Times, 2004.
108
[50] Martin Rowe, "The next generation's modulation: PAM-4, NRZ, or ENRZ?," EDN
Network, 2014.
[51] Winston Way, "PAM-4: A Key Solution For Next-Generation Short-Haul Optical
Fiber Links," Neophotonics, 2015 .
[52] Ed Frlan, "OIF Next Generation Interconnects - a Semiconductor Perspective,"
Semtech, 2013.
[53] A. Deas, "A Comparison of NRZ and PAM-4 for 11Gbps+ Data," Acuid Corporation
White Paper, 2004.
[54] S. Palermo, "ECEN689: Special Topics in High-Speed Links Circuits and Systems -
Lecture 9: Modulation Schemes," Analog & Mixed-Signal Center, Texas A&M
University, Spring 2010. [Online]. Available:
http://www.ece.tamu.edu/~spalermo/ecen689/lecture9_ee689_modulation.PDF.
[Accessed 19 June 2015].
[55] M. R. a. J. D. A. Sanders, "Channel compliance testing utilizing novel statistical eye
methodology," in IEC DesignCon, Santa Clara, CA, 2004.
[56] Bryan Casper, "Peak Distortion Analysis ISI," Circuits Research Lab, Intel
Corporation, Oregon.
[57] B. Sullivan, M. Rose, J. Boh, "Simulating High-Speed Serial Channels with IBIS-AMI
Models - Application Note," Keysight Technologies, 2014.
[58] Vladimir Stojanovic, Marc Horowitz, "Modeling and Analysis of High-Speed Links,"
in Research Laboratory of Electronics at MIT, Los Altos.
[59] ON Semiconductor, "Understanding Data Eye Diagram Methodology for Analyzing
High Speed Digital Signals," AND9075/D.
[60] Y. Cai, S. A. Werner, G. J. Zhang, M. J. Olsen, R. D. Brink , "Jitter Testing for Multi-
Gigabit Backplane SerDes - Techniques to Decompose and Combine Various Types
of Jitter," IEEE INTERNATIONAL TEST CONFERENCE (ITC), pp. 700-709, 2002.
[61] Mike Li, Jan Wilstrup; Wavecrest corportation, "Statistical and System Transfer
Function Based Method For Jitter and Noise In Communication Design and Test," in
DesignCon, 2004.
[62] Mike Peng Li, J. Wilstrip, D. Petrich, "A New Method for Jitter Decomposition
Through its Distribution Tail Fitting," in ITC Proceedings, 1999.
109
[63] J. G. Proakis, M. Salehi, Digital Communications, New York: McGraw Hill High
Education, 2008.
[64] F. Lambrecht, C. Huang and a. M. Fox, "Techniques for determining performance
characteristics of electronic systems". United States of America Patent 6775809,
14 Mar. 2012.
[65] H.-J. Liaw, X. Yuan and M. Horowitz, "Techniques for determining performance
characteristics of electronic devices and systems". United States of America Patent
6920402, 7 March 2001.
[66] M. Shimanouchi, M. P. Li, H. Wu, "Comparison of Two Statistical Methods for High
Soeed Serial Link Simulations," in DesignCon, 2013.
[67] The MathWorks, Inc., Natick, Massachusetts: www.mathworks.com.
[68] A. Sanders, M. Resso, J. D'Ambrosia, "Channel Compliance Testing Utilizing Channel
Compliance Testing Utilizing," in International Engineering Consortium Designcon,
Santa Clara, 2004.
[69] S. Pillai, A. Papoulis, Probability, Random Variables, and Stochastic Processes, 2002:
McGraw-Hill.
[70] J. Zerbe, C. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, "Equalization and clock
recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell," in IEEE
International Solid-State Circuits Conference ( ISSCC) , Los Altos, 2003.
[71] Jeff Sonntag, John Stonick, et. al., "An Adaptive PAM-4 5 Gb/s Backplane
Transceiver in 0.25 um CMOS," in IEEE CUSTOM INTEGRATED CIRCUITS
CONFERENCE , Oregon, 2002.
[72] Ransom Stephens, PhD, "The Rules of Jitter Analysis," Agilent Technologies.
[73] Jonathan Abel and Julius Smith, "Robust Design of Very High-Order Allpass
Dispersion Filters," in Proceedings of the 9th International Conference on Digital
Audio Effects, Montreal, Sept. 2006.
[74] David Brown, Semtech, "NRZ vs. PAM-N for 400GbE in the Data Center," Ethernet
Technology Summit, Santa Clara, 2013.
[75] R. Zarr, "NRZ Vs. Multi-Level Signaling: Which Is More Efficient For Moving Bits?,"
Electronic design, 2013.
[76] Dr. Eric Bogatin, "Essentials of Jitter," Santa Clara, 2014.
110
[77] Agilent Technology, Inc., "Introduction to Jitter and Jitter Analysis Techniques for
Transmitter Signals at High Data Rates," 2004.
[78] Wavecrest Corporation, "Jitter Fundamentals," 2005.
[79] "The History of Jitter (Part III)," 2 April 2015. [Online]. Available:
http://blog.teledynelecroy.com/2015/04/the-history-of-jitter-part-iii.html.
[Accessed 24 June 2015].
[80] TeleDyne LeCroy, "Back to Basics: Jitter," 23 December 2013. [Online]. Available:
http://blog.teledynelecroy.com/2013/12/back-to-basics-jitter.html. [Accessed 10
July 2015].