modeling, design, and optimization design space explorationese370/fall2019/handouts/lec... · 2019....

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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

Lec 19: October 18, 2019 Design Space Exploration (con’t)

Pass Transistor Logic

Penn ESE 370 Fall 2019 - Khanna

Design Space Exploration

3 Penn ESE 370 Fall 2019 - Khanna

Design Problem

!  Function: Identify equivalence of two 32bit inputs !  Optimize: Minimize total energy !  Assumptions: Match case uncommon

"  Ie. Most of the time, the inputs won’t be matched

!  Deliberately focus on Energy to complement project "  …but will still talk about delay


Problem Solvable

!  Is it feasible? "  First, make sure we have a solution so we know our main

goal is optimization

!  How do we decompose the problem?

!  What look like built out of nand2 gates and inverters?


Problem Solvable






Problem Solvable






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Single Gate Match Condition

!  Design a single gate for match comparison

Penn ESE 370 Fall 2019 - Khanna 8

Goal: Minimize Total Power

!  Static CMOS: "  Ptot ≈ a(Cload+2Csc)V2f+VI’

s(W/L)e-Vt/(nkT/q)

!  Ratioed Logic: "  Ptot ≈ a(Cload+2Csc)V2f

+p(Vout=low)V2/Rpon

+(1-p(Vout=low))VI’s(W/L)e-Vt/(nkT/q)

!  What can we do to reduce power?


Knobs

!  What are the options and knobs we can turn?


Design Space Dimensions

!  Topology "  (A) Gate choice, logical optimization "  (B) Fanin, fanout, "  (C) Serial vs. parallel

!  Gate style / logic family "  (D) CMOS, Ratioed (N load, P load), Pass

!  (E) Transistor Sizing !  (F) Vdd !  (G) Vth


Gate Choice

!  (A) What gates might we build?


Gate Choice

!  (A) What gates might we build?


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Gate Fan-in

!  (B) High fan-in?


Gate Fan-in

!  (B) High fan-in?


Gate Topology

!  (C) Serial-Parallel?


Gate Topology

!  (C) Serial-Parallel?


(D) Logic Family

!  Considerations for each logic family?


(D) Logic Family

!  Considerations for each logic family? "  CMOS "  Ratioed with PMOS load "  Ratioed with NMOS load

!  Ratioed Logic "  Reduced Cloads result in lower switching power (Pdyn #) "  Increased static power


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(E) Sizing

!  How do we want to size gates?


(E) Sizing

!  How do we want to size gates? "  Sizing transistors up will reduce delay $

"  Reduces short circuit power

"  Increases dynamic power


€

E =Vdd × Ipeak × tsc ×12#

$ % &

' (

#

$ %

&

' (

(F) Reduce Vdd

!  What happens as reduce V? "  Energy?

"  Dynamic # "  Static #

"  Switching Delay? %

&  τgd=Q/I=(CV)/I &  Id=(µCOX/2)(W/L)(Vgs-VTH)2

&  τgd impact?&  τgd α 1/V

&  Limit on Vdd?


(G) Increase Vth?

!  What is impact of increasing threshold on "  Dynamic Energy? # "  Leakage Energy? # "  Delay? %

&  τgd=Q/I=(CV)/I &  Ids=(νsatCOX)(W)(Vgs-VTH-VDSAT/2)


Ideas

!  We know many things we can do to our circuits !  Design space is large !  Systematically identify dimensions !  Identify continuum (trends) tuning when possible !  Watch tradeoffs

"  …don’t over-tune


Identify Function

!  What function is this?


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Pass Transistor Logic

!  What does this do?


A B Y

0 0

0 1

1 0

1 1

Area

!  Compare PT with CMOS circuit?


Output

!  Is this a regenerating/restoring gate?

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A B Y

0 0 0

0 1 1

1 0 1

1 1 0


Output

!  What does output look like (DC transfer)? "  (B=1, notB=0, sweep A, notA=CMOS inv(A))


Pass TR transfer (B=1)

30 Sweep A


XOR Output

!  Reasonable Input to CMOS Inverter?


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Pass Transistor xor2 with inv restore


Compare CMOS

!  Is this a fair comparison?


Required to use?

!  What should we add to make suitable comparison with CMOS?


Restore Output


!  What should we add to make suitable comparison with CMOS?

Restore Output

!  Area? (compare to CMOS)


Chain Together


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Analyze Stage


Impact of Capacitance


!  CGS=CGCS+CGSO

!  CGD=CGCD+CGDO

!  CGB=CGCB

!  CSB=Cdiff !  CDB=Cdiff

Today

!  Pass Transistor Circuits "  Case1: Cdiff=0 "  Case2: Cdiff>0


Delay A=1, B=0, Cdiff=0?


2C0


!  What’s the equivalent RC circuit?


2C0




2C0

2C0

8



2C0




2C0 2C0

2C0


!  What’s the equivalent RC circuit? "  What are we ignoring?


2C0 2C0

2C0

Cdiff>0


Contact/Diffusion Capacitance

!  Cj – diffusion depletion !  Cjsw – sidewall capacitance !  LS – length of diffusion

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€

Cdiff = C jLSW +C jsw 2LS +W( )

LS

Cdiff ≈WCdiff 0 =W ⋅γC0

Cdiff 0 ≈ γC0Define:


First Order Model

!  Switch "  Loads all terminals capacitively

"  Draw no steady-state current for a CMOS gate "  Does not impact steady-state output voltage "  Impacts Settling time/Delay

"  Has finite drive strength "  Could form voltage divider with resistive load "  Impacts Settling time/Delay

49 Penn ESE370 Fall2019 – Khanna

C0R0

Cdiff0

Cdiff0

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First Order Delay

!  R0 = Resistance of minimum size NMOS device !  C0 = gate capacitance of minimum size NMOS

device !  Cdiff0 = diffusion capacitance on minimum size

NMOS "  Cdiff0 =γC0

!  Rdrive = R0/W !  Cg = WC0

!  Cdiff = WCdiff0

Penn ESE 370 Fall 2019 - Khanna 50

Inverter Delay

!  Delay driving another (min size) inverter? "  Include Cdiff=γCg=WγC0

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W=1


Delay A=1, B=1, Cdiff=γC0? (W=1)


2C0

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Delay A=1, B=1, Cdiff=γC0? (W=1)

2C0+3Cdiff0 2C0+2Cdiff0

2C0

Bonus


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A

B


A B Y

0 0

0 1

1 0

1 1

Bonus


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A

B

More examples in the text Penn ESE 370 Fall 2019 - Khanna

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

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Idea

!  There are other circuit disciplines !  Can use pass transistors for logic

"  Sometimes gives area or delay win


Admin

!  Project "  Milestone due tonight

"  Will get feedback by Sunday morning

"  Can’t pass the class if you don’t turn in projects "  Can’t do project last minute

"  Really should be into exploring optimizations now


Logic Types

!  CMOS Gates "  Dual pull-down and pull-up networks, only one enabled at a time "  Performance of gate is strong function of the fanin of gate

"  Techniques to improve performance include sizing, input reordering, and buffering (staging)

!  Ratioed Gates "  Have active pull-down (-up) network connected to load device "  Reduced gate complexity at expense of static power asymmetric transfer

function "  Techniques to improve performance include sizing to improve noise margins and reduce

static power

!  Pass Gates "  Implement logic gate as switch network for reduced area and load

capacitance "  Long cascades of switches result in quadratic increase in delay "  Also suffer from reduced noise margins (VT drop)

"  Use level-restoring buffers to improve noise margins

!  Dynamic logic … coming up soon 58 Penn ESE 370 Fall 2019 – Khanna

modeling, design, and optimization design space explorationese370/fall2019/handouts/lec... · 2019....

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