modeling and parameter extraction technique for hv … driven cad a journal for circuit simulation...

TCAD Driven CAD A Journal for Circuit Simulation and SPICE Modeling Engineers

1. IntroductionWe have developed several kinds of HV MOS deviceswhose device structures and doping levels in the offsetregions differ depending on the specifications of thedevices. We have developed the bi-directional HVMOS device (e.g., it can be used as a bi-directional MOSswitch) with both drain and source offset regions, andwe previously described its SPICE model [4] – [5] based onBSIM3v3 [1] – [3]. On the other hand, the uni-directionalHV MOS device has only a drain offset region. That is,it does not have a source offset region withcorresponding source resistance.

In this paper, I have used the same technique to modeluni-directional HV MOS devices as previously reportedfor bi-directional HV MOS devices [4] – [5] while adopt-ing a new parameter extraction technique. With thenew uni-directional HV MOS modeling technique, thesimulated I-V characteristics of the uni-directional n-channel HV MOS device match the measured charac-teristics well, which confirms its effectiveness.

2. Uni-directional HV MOS Device TechnologyFigure 1 shows the structure of our 45 V n-channel HVMOS device, with a gate-oxide film thickness (Tox) of1350Å, channel length (L) of 3.2µ m and offset of 3.2µ m.A n-offset region of low doping concentration is used inthe drain region, in order to realize high uni-directionaldrain-source breakdown voltage. Based on our devicesimulations, we consider that the basic operation of thebi-directional HV MOS device is as explained below ,and this is also valid for the uni-directional HV MOSdevice. When drain-source voltage (Vds) is applied tothe HV MOS device, a depletion region grows in then- offset. The effect of the electric field from the gateelectrode on the depletion region causes the drain-sidechannel terminal voltage to saturate at a low voltage.This reduces the voltage across the channel, and henceincreases the breakdown voltage between the drain andsource. Moreover, as the drain-side channel terminalvoltage saturates in the triode region, gm is reduced.

3. Application of Bi-directional HV MOSModel to Uni-directional HV MOS DeviceIn this section, I directly apply the bi-directional HVMOS model and its parameter extraction technique tothe uni-directional HV MOS device, and investigate theresults. The bi-directional HV MOS model parameterextraction technique is outlined below [4] – [5]:

1) First, extract all BSIM3v3 parameters by thestandard method.

2) Then set the value of VSAT to a large value (e.g.,1x109 m/sec) assuming a long-channel device.

Volume 12, Number 7, July 2000

Modeling and Parameter Extraction Technique for HV MOS Devices with BSIM3v3

Takao Myono, SANYO Electric Co., Ltd.

INSIDE

New RF MOSFET Small Signal SPICE Model Part 2 . . . 5

UFSOI: Process-Based Compact SOI MOSFET Models. . . . 8

Calendar of Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Continued on page 2....

n+

p-well

L=3.2µm

Tox=1350Å

n+

2µm 3.2µm

gatedrainsource

n- offset-region

Figure 1. Schematic structure of the uni-directional n-channel HVMOS device.

SILVACOINTERNATIONAL

3) Optimize AGS and DELTA at the sametime. This is to optimize the saturationvoltage of the drain-side channel terminalVdsat and the source resistance due to theoffset region.

Using the above procedure for the bi-directionalHV MOS device, the parameter AGS optimizesVdsat and source resistance in a well-balancedmanner, and the measured and simulated I-Vcharacteristics match well. Furthermore, thismethod can precisely reproduce the gm-reductionphenomenon, which is inherent to HV MOSdevices. On the other hand, step II in Table 1shows the parameters obtained by directlyapplying the bi-directional HV MOS devicemodel and parameter extraction technique tothe uni-directional HV MOS device, and Figure 2shows a comparison of the measured andsimulated I-V characteristics. In Figure 2 largediscrepancies are observed between themeasured and simulated I-V characteristics.

4. Proposed Uni-directional HV MOSDevice Modeling TechniqueIn this section I propose a uni-directional HVMOS modeling technique: I use the bi-directional HVMOS model in [4] – [5] as a basis, and the mainequations are as follows:

Here, W is the channel width, µeff is the effective mobili-ty, εox is the permitivity of the silicon-oxide film, Vth is

the threshold voltage, AGS is the gate bias coefficient ofthe Abulk, Vdsat is the saturation value of the drain-sidechannel terminal, Vdseff is the effective drain-source volt-age and DELTA is the effective drain voltage smoothingparameter of Vdseff. Where, V’ds is the drain-side channelterminal voltage, which is equivalent to the Vdseff of BSIM3v3.

Vrs is voltage drop across the source resistance in the offsetregion. It cannot be eliminated from equation (1) as Vrs

is inherent for the bi-directional HV MOS model withBSIM3v3. Hence, it is necessary to compensate for partof the drain current component by Vrs in equation (1)for the uni-directional HV MOS model. Here, I define thedrain current Idrs0 in which the voltage Vrs in equation (1)is eliminated as shown below. Idsr0 is a model equationfor the uni-directional HV MOS device model.

Further, by defining Ivrs as the variable component ofdrain current due to Vrs, I obtain the following expression:

The above expression indicates that the way tocompensate for Ivrs in the uni-directional HV MOSmodel is to optimize Idsr0 by making it larger than Ids bythe value of Ivrs. Here it can be assumed that the valueof Ids is equivalent to the measured data. Suppose theparameter AGS is set to a large negative value, thevalue of Abulk in equation (4) increases, which in turndecreases the value of Vdsat in equation (5) and results in

The Simulation Standard July 2000

Vgs=1.93V to 45V stepped by 3.08V measured

simulated

0

5

10

15

20

25

30

0 10 20 30 40

Vds(V)Id

s(m

A)

Figure 2. Comparison between measured and simulated. (with the bi-direc-tional HV MOS model) I-V characteristics of the 45V HV MOS device.

−−−=

20ds

thrsgsox

oxeffds

VVVV

LW

TG

εµ ,

( )2

1 dsbulkrs

VAV −= ,

IG V

G Rdsds ds

ds ds=

+0

01,

( )gsbulk VAGSfA ,1≡ ,

( )gsbulk

thgsdsat VAGSf

A

VVV ,2≡

−≈ ,

( )gsdsdseffds VVDELTAAGSfVV ,,,3≡= .

(1)

(2)

(3)

(4)

(5)

(6)

−−=

20ds

thgsox

oxeffdsr

VVV

LW

TG

εµ ,

IG V

G Rdsrdsr ds

dsr ds0

0

01=

+ .

(7)

(8)

I I Ids dsr vrs= -0 . (9)

decreasing the value of Idsr0. At the same time,Abulk increases the value of Ivrs larger. So, AGS

cannot optimize Vdsat correctly, and Ids cannotrepresent the gm-reduction (refer to section 7.).In addition, the value of Ivrs cannot be obtaineddirectly by calculation; instead use thefollowing equation:

I propose the following model which canexpress the gm-reduction.

1) BSIM3v3 SPICE model combines the sourceand drain resistance with Rds (whose valuedepends on Vgs) as follows:

where RDSW is the source and drain resis-tance per unit channel width and PRWG is a Vgs

coefficient. Rds is incorporated in the drain currentexpression of the simplified model as an explicitfunction of Gds0 shown in equation (3), and Rds hard-ly affects the saturation voltage (Vdsat) of BSIM3v3.Note that Gds0 has Rds in its denominator, and bymaking Rds a function of Vgs, it is possible to accu-rately express the gm-reduction for Idsr0 and Ids

mathematically.

2) Rds provides the gm-reduction for Idsr0 and Ids, butthey are not the same. Idsr0 with a larger absolute

value has larger gm-reduction, so that it can givemost appropriate gm-reduction in order to compensatethe value of Ivrs, which is Idsr0 – Ids.

3) Rds has little influence on Vdsat, and it can be utilizedindependently of AGS.

4) AGS can be used to optimize the absolute value ofIds, through Vdsat.

5) For HV MOS devices, both Vgs-caused mobilitydegradation effect and gm-reduction occur at thesame time and influence of the latter is morepredominant. So in the HV MOS model, it ispossible to ignore the mobility degradation effect.By defining µeff as a constant regarding to Vgs, wecan obtain about five times faster optimization ofthe parameters for the parameter extraction tool.

5. Proposed Parameter ExtractionTechnique for Uni-Directional HV MOSDevice ModelingIn this section I describe the proposed parameterextraction technique for the uni-directional HV MOSmodel which can be implemented by using a SPICE modelparameter extraction system, such as UTMOST [6].

1) First, extract all BSIM3v3 parameters by the standardmethod (step I in Table 1).

2) Then set the value of VSAT to a large value (e.g.,1x109) assuming the long channel model.

3) Optimize the parameters of U0, RDSW, PRWG,AGS, and DELTA together in all the triode region(up to close to the saturation region) i.e., from(Vds=0V, Vgs=1.93V) to (Vds=20V, Vgs=45V). RDSW

July 2000 The Simulation Standard

Vgs=1.93V to 45V stepped by 3.08V measured simulated

0

5

10

15

20

25

30

0 10 20 30 40

Vds(V)

Ids(

mA

)Figure 3. Comparison between the measured and simulated (with the uni-directional model) I-V characteristics of the 45V n-channel HV MOS device.

Vgs=1.93V to 45V stepped by 3.08V

measured simulated

0

5

10

15

20

25

0 5 10 15 20

Vds(V)

Ids(

mA

)

Figure 4. Comparison between the measured and simulated (withthe uni-directional HV MOS model and PCLM=0) I-V characteristicsin the triode region.

dsdsrvrs III −= 0 . (10)

( )R

RDSW PRWG V

Wdsgs

=+ ⋅1

,(11)

and PRWG have to be optimized such that Rds

expresses gm-reduction of Idsr0 while AGS has to beoptimized such that Abulk and Vdsat compensate for Ivrs.

4) Optimize PDIBLC1 and PDIBLC2

Since optimization of the absolute value of Ids and gm

interact with each other, it is necessary to optimize themsimultaneously. Step III in Table 1 shows extractedparameter values based on the above procedure, andFigure 3 shows a comparison between the measured andsimulated I-V characteristics. I see that good agreementis obtained between the measured and simulated results(except for the region where negative gds appears.).

In Figure 3, accuracy of simulation decreases in the linearregion with higher value of Vgs. This is because Rds providesthe gm-reduction in all the region. However, gm-reductiondue to the drain-side offset region appears only in thesaturation region. To compensate for the worseningaccuracy, it is effective to implement Step III again bysetting the channel length modulation parameter

PCLM=0 (or optimize). The 0 value ofPCLM amplifies the gm-reduction in thesaturation region, so that Vgs dependenceof Rds is optimized smaller (Step IV intable 1). As a result of this, gm-reductioncaused by Rds in the linear region getssmaller. Step IV in Table 1 shows theparameters with PCLM=0 and Figure 4shows the comparison between the mea-sured and simulated I-V characteristicsin the triode region. Figure 5 shows Ids-Vgs characteristics in triode region. Notethat Ids monotonically increases under thecondition of Vgs ≥ 40V, however, Idsslightly decreases when Vgs ≥ 40V, andthis phenomenon is more predominantwhen Vds = 1V than Vds = 2V. This is dueto the decrease of the channel voltage ofthe drain terminal by the influence of thegate electric field.

References[1] Y. Cheng, M.-C. Jeng, Z. Liu, J. Hubg, M. Chen, P. K. Ko and C.

Hu, "A Physical and Scalable I-V Model in BSIM3v3 forAnalog/Digital Circuit Simulation, " IEEE Electron Devices, vol.44,no.2, pp.277-284 (Feb. 1997).

[2] J. H. Huang, Z. H. Liu, M. C. Jeng, K. Hui, M. Chan, P. K. Ko andC. Hu, BSIM3 Manual (version 2.0), University of California,Berkeley, (1994).

[3] BSIM3v3 Manual (f inal version), University of California,Berkeley,(1995).

[4] T. Myono, S. Kikuchi, K. Iwatsu, E. Nishibe, T. Suzuki, Y. Sasaki,K. Itoh and H. Kobayashi, "High-Voltage MOS Device Modelingwith BSIM3v3 SPICE Model, "IEICE TRANS. ELECTRON,vol.E82-C, No.4, pp630-637, (April 1999).

[5] T. Myono, E. Nishibe, S. Kikuchi, K. Iwatsu, T. Suzuki, Y. Sasaki,K. Itoh and H. Kobayashi, " Modeling and Parameter ExtractionTechnique for High-Voltage MOS Device", Proc. of InternationalSymposium on Circuits and Systems, pp.230-233, Orlando Florida(June 1999).

[6] UTMOST III Extraction manual,vol.1, ver. 12.03, SILVACO

International, Santa Clara, C


Vds=1V

Vds=2V

0

1

2

3

4

5

6

7

0 10 20 30 40

Vgs(V)

Ids(

mA

)measuredsimulated (step III)simulated (step IV)

Figure 5. Comparison between the measured and simulated (with the uni-directionalHV MOS model) Ids-Vgs characteristics in triode region.

AGS U0 UA RDSW PRWG

Step I 0.084 616 0.7x10-8 3.8x103 0.0

Step II -0.049 520 0.4x10-8 3.8x103 0.0

Step III -0.076 463 0.0 1.9x103 0.092

Step IV -0.077 588 0.0 5.5x103 0.018

Table 1. Extracted BSIM3v3 Parameter Values for each step.

Parameter Extraction Procedure

RF MOSFET Small –Signal Model andParameters

Small-signal equivalent circuit of MOSFETafter de-embedding parasitics is shown inFigure 1 and small-signal model parametersare listed in Table 1.

Parameter Extraction Strategy

Parameter extract ion is performedfrom real and imaginary parts of theY-parameters. Each parameter is extractedfrom the Y-parameter equations whichcontain frequency terms.

To fit a straight line to the data plot, linear regression is used.

With the X data, the independent variable, and the Ydata, the dependent variable, the estimated linearregression model is stated;

Yi = A + BXi

where the parameters, A and B, are estimated by themethod of least squares.

A is the intercept :

B is the slope :

The standard deviation is defined as

Where (Xi,Yi) are the data points, N is the number ofdata points,

Parameters such as Cgd, Cgs, Rg, Cdg, Cjd, and Cds areextracted as a function of frequency and in these casesthe extracted values are determined by their meanvalue. The mean of parameter is calculated by

where Pi are the extracted parametervalues as a function of frequency.

Extraction Routine

* Note that, ω = 2 <–> π <–> .

Step 1.

gm is obtained from y-intercept of Re[Y21]versus ω2 .


New RF MOSFET Small Signal SPICE Model Part 2

Ickjin Kwon, Minkyu Je, Kwyro Lee, and Hyungcheol ShinDepartment of Electrical Engineering, Korea Advanced Institute of Science and Technology

GATE

SOURCE = BODY

DRAINRg

Cgs

Cgd / Cdg

gm gds Cds

Cjd

Rsubd

ds

dds

dg

ddg

gd

ggd

gs

ggs

VQ

CVQ

C

V

QC

V

QC

∆∆

=∆∆

=

∆∆

=∆∆

=

,

,

Figure 1. Common-source equivalent circuit of a MOSFET after de-embeddingparasitics of on-wafer pads and interconnection lines.

Small Signal Model Parameters Physical Meaning Unit

gm Transconductance A/V(S)

gds Drain Conductance A/V(S)

Cgd Gate-to-Drain Capacitance F

Cgs Gate-to-Source Capacitance F

Rg Gate Resistance Ω

Cdg Drain-to-Gate Capacitance F

Rsubd Substrate Resistance ΩCjd Drain Junction Capacitance F

Cds Drain-to-Source Capacitance F

Table 1. Small-signal parameters of RF MOSFET and their physical meaning andunit of parameters.

A= Y - BX

N

Σ(Xi – X)(Yi– Y)i=1B=

N

Σ(Xi – X)2

i=1

N

Σ(Yi – (A+BXi ))2

i=1

N– 2

1 N 1 N

X= Σ X i , and Y= Σ YiN i=1 N i=1

1 N

P= Σ P i N i=1

Step2.

gds is obtained from y-intercept of Re[Y22] versus ω2 .

Step 3.

* Extracted Cgd is the mean value as a function offrequency.

Step 4.

* Extracted Cgs is the mean value as a functionof frequency.


Extracted Parameter Required Equation

gm

Y = Re (Y21)X = ω2

Y = A1 + B1 Xgm = Re [Y21]|ω

2 =0 =A1

W / L = 100 / 0.35V = 1V, V = 2Vgs ds

ω [x10 rad ]2 21 2

0.0 0.5 1.0 1.5 2.0 2.5 3.0

17

16

15

14

13

Re(

Y21

) [m

S]

g = 16.6 mSm

Figure 2. Extraction results of gm.


gds

Y = Re (Y22)X = ω2

Y = A2 + B2 Xgm = Re [Y22]|ω

2 =0 =A2

W / L = 100 / 0.35V = 1V, V = 2Vgs ds

ω [x10 rad ]2 21 2

0.0 0.1 0.2 0.3 0.4 0.5 0.6

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Re(

Y22

) [m

S]

g = 0.31 mSds

Figure 3. Extraction results of gds.


Cgd–Im[Y12] Cgd = ω

Frequency [GHz]C

[fF

]gd

W / L = 100 / 0.35V = 1V, V = 2Vgs ds

0 2 4 6 8 10

70

60

50

40

30

20

10

0

Figure 4. Extraction results of Cgd.


CgsIm[Y11]+Im[Y12] Cgs = ω

Frequency [GHz]

C

[f

F]

gs

W / L = 100 / 0.35V = 1V, V = 2Vgs ds

0 2 4 6 8 10

200

180

160

140

120

100

80

60

40

20

0

Figure 5. Extraction results of Cgs.

Step 5.

* Extracted Rg is the mean value as a functionof frequency.

Step 6.

* Extracted Cdg is the mean value as a functionof frequency.

Step 7.

Rsubd and Cjd are obtained from linear regressionusing the following relation.

Rsubd is determined from slope of Y as a function of ω 2 .

Step 8.

* Extracted Cjd is the mean value as a functionof frequency.


Continued on page 10....


RgRe[Y11]Rg =

(Im[Y11]) 2

Frequency [GHz]

R

[Ω

]g

W / L = 100 / 0.35V = 1V, V = 2Vgs ds

0 2 4 6 8 10

70

60

50

40

30

20

10

0

Figure 6. Extraction results of Rg.

Frequency [GHz]

W / L = 100 / 0.35V = 1V, V = 2Vgs ds

0 2 4 6 8 10

100

80

60

40

20

0

C

[f

F]

dg

Figure 7. Extraction results of Cdg.


Cdg = –Im[Y21]/ω – gmRg(Cgs=Cgd)Cdg

ω2 1Y= =ω2Rsubd+

Re[Y22] - gds - ω2 CgdCdgRg - ω2 gmR2gCgd(CgsCgd) Cjd

2 Rsubd

Extracted Required EquationParameter

W / L = 100 / 0.35V = 1V, V = 2Vgs ds

ω [x10 rad ]2 21 2

0 1 2 3 4 5

1.5

1.0

0.5

slope : R = 200Ωsubd

Y [x

10

]24

Figure 8. Extraction results of Rsubd.

ω 2Y =

Re[Y22] -gds -ω2 CgdCdgRg -ω2 gmR2gCgd(Cgs+Cgd)


Cjd Cjd = [(Y - ω2 Rsubd)Rsubd]-1/2

IntroductionSOI technology appears now to have become anadvantageous, viable option for low-voltage andhigh-performance CMOS integrated circuits indigital, analog, and mixed-signal applications.The thin-film nature of the SOI MOSFET, however,can underlie physical mechanisms that complicatecircuit simulation and portend equivocation indesign. For example, floating-body (FB) effects[1], which in fact are obtained even in body-tieddevices due to unavoidable high resistance [2],render empirical compact models like those usedfor designing bulk-Si CMOS circuits inadequatefor reliable SOI circuit simulation. Furthermore,such models cannot be easily calibrated usingcommon parameter-optimization techniquesbecause of ambiguous data acquisition impliedby SOI device self-heating in DC measurementsand/or FB charge dynamics in pulse measurementsdesigned to avoid self-heating; such optimization,because of the complex body charging dynamics,does not and cannot cover the large range ofoperational conditions that obtain in actual SOICMOS circuits. Consequently, Silvaco hasincorporated the physical process-based UFSOIMOSFET models [3] into SmartSpice andUTMOST.

Model DescriptionThe UFSOI implementation includes options for boththe partially, or non-fully depleted (NFD) model [4] andthe fully depleted (FD) model [5]. As illustrated by thenetwork representation in Fig. 1, the models are charge-based with five terminals, and they have the FB option.The NFD model physically accounts for dynamic as wellas DC FB effects in all regions of operation. The FDmodel physically accounts for the charge couplingbetween the front gate and back gate (substrate). Bothcompact models account for all the important featuresand mechanisms prevalent in scaled SOI MOSFETs,which include polysilicon-gate depletion, quantizationdue to quantum-mechanical carrier confinement, non-localcarrier temperature-dependent impact-ionizationcurrent (I Gi ) [6] and velocity overshoot, and the par-asitic bipolar transistor (BJT) currents and charges [7],which are properly coupled to the MOS currents andcharges; the BJT base (body) current can comprise ther-mal generation, GIDL, junction tunneling, and impact-ionization currents. The noise (thermal, flicker, andshot) modeling accounts for hot-carrier effects on the

channel thermal noise, important at high frequencies,and, with the implicit transimpedances, has beenshown to predict the low-frequency Lorentzian excessnoise component well [8]. The temperature modeling istruly physical [9], involving no extra parameters, and itis the basis of the self-heating option which uses asingle-pole thermal subcircuit for each device. The FDmodel further accounts for the 2D source/drain fieldfringing in the back oxide (BOX), and the inducedback-channel current (in weak/moderate inversion) [5].The NFD model further accounts for nonuniform channeldoping (e.g., via retrograde [4] and halo options), andits control of short-channel and parasitic BJT effects.

All currents and charges and their derivatives, whichform the basis of the UFSOI quasi-static formalism,are continuous in all regions of operation [10]. Thecharacterization of body charge (QB) in the FD modelaccounts for accumulation charge, which means thatthe model is hybrid-FD/NFD with regard to chargedynamics; in the FD (on) state, dQB /dt 0, which meansthat most FB effects are suppressed. In the NFD model,QB is defined by neutrality, which means that thecharge dynamics properly reflects all the intrinsictranscapacitances. The FB effects are implicitly accountedfor in the UFSOI models by proper merging of the carrier


UFSOI: Process-Based Compact SOI MOSFET ModelsJerry G. Fossum, Mario M. Pelella, and Meng-Hsueh Chiang

Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611, U.S.A.

ICH

IBJT

-IRGt(VB’D’) (w/ ITUN)(w/ -ITUN) IRGt(VB’S’)

D’S’

B’

Gf

Gb B

DS

IGi (w/ IGIDL)

RS+RLDS

RB

dQGfdt

-------------

dQSdt

----------

dQDdt

-----------

dQBdt

-----------

dQGbdt

--------------

RD+RLDD

Figure 1. Network representation of the processed-based UFSOI (NFD andFD) MOSFET models.

generation/recombination currents, the BJT and channelcurrents, and the charging, or transcapacitance currents.The merging, which is unified for DC, AC, or transientsimulations, is reflected by the floating-body (B’) nodalequation indicated in equation 1:

where neutrality implies

The combination of (1) and (2) defines VBS and VBD forany condition, and thereby describes how the intrinsiccapacitive coupling and/or the recombination/genera-tion in the device govern the FB effects as usuallyreflected by ICH (VBS ) and/or IBJT (VBS).

The truly physical nature of the UFSOI models renderstheir formalisms implicit, meaning that Newton-likeiterative solutions have to be derived. Further, thederivatives (transconductances and transcapacitances)needed for the nodal analysis have been computed viadifference approximations, necessitating five passesthrough the model routine for each call by SmartSpice.Recently, however, the use of approximate analyticalderivatives for the NFD model in DC and transientsimulations has been incorporated in UFSOI, with theexception the critical VBS -derivatives; differenceapproximations still have to be used in AC simulations.The result of this NFD speed-up is a physical yetcomputationally efficient model, requiring run-timesthat are not much longer than thoserequired by empirical counterparts.

Process-Based ModelCalibration and UtilityWhat makes the UFSOI models reallyunique, and, in our opinion, essentialfor reliable SOI circuit simulation, istheir process basis. Key (~20) UFSOImodel parameters are either structuralor physics-based, and hence they areproperly correlated and theirevaluation can be done unequivocallyin a straightforward manner, usingdevice-structure data and measureddata taken only in low-power regionswhere self-heating is negligible [11].Such structure-dependent calibrationrenders the UFSOI models predictive,and useful for sensitivity analyses andnext-generation performance projec-tions [12], as well as reliable circuitsimulation with devices in all possibleregions of operation.

We exemplify this UFSOI utility by considering FBhysteresis in PD/SOI CMOS inverter-based circuits [13].This hysteresis, first noted via UFSOI model predictions [14],is reflected by history-dependent propagation delaysthat are due to slow carrier recombination/generationprocesses superimposed on the fast body chargedynamics driven by the intrinsic capacitive coupling.The hysteresis is thus quite sensitive to the device structureas well as physics-based parameters such as carrier lifetimes.For example, Figure 2 shows a UFSOI-predicted “fast”open-inverter-chain delay in time (from DC to thedynamic steady state) for L eff = 145nm PD/SOI CMOSfor two different SOI film thicknesses (tSOI ). The “fast”delay is the one corresponding to initially (t = 0)body-charged (VDS =VDD = 1.8V VBS > 0 for thenMOSFETs, VBS < 0 for the pMOSFETs) active devicesin the inverter chain; whereas the “slow” delay wouldcorrespond to initially uncharged (VDS =0 VBS = 0)active devices. Note that reducing tSOI decreases thedelay, but alters the hysteretic variation to an increasingdelay with time. These results are due to the varyingratio of the gate-body capacitance to the drain-bodycapacitance, which increases with decreasing tSOI andtends to increase V BS (t). Thus, early in time, the“current overshoot” in the active device is enhanced;and later in time, a “dynamic strengthening” of the loaddevice occurs. These results, which are consistent withexperimental ones, clearly reflect the complexity ofdynamic FB effects, and imply why a predictive(process-based) compact model is needed for reliableSOI circuit simulation.


10-9 10-8 10-7 10-6

Time (s)

24.5

25.0

25.5

26.0

26.5

27.0

Del

ay/S

tage

(ps

)

tSOI = 150nm

100nm

EnhancedOvershoot

EnhancedDynamicLoading

Figure 2. Network representation of the process-based UFSOI (NFD and FD) MOS-FET models.

dQBGi RGt B’S’ RGt B’D’dt

= I - I (V ) - I (V ) (1)

B S S Gf GbQ = -(Q +Q +Q +Q ). (2)

SummaryThe process-based UFSOI models have been released tomore than 100 companies and universities throughoutthe world, in addition to the SmartSpice releases. Bothmodels are continually upgraded as the SOI technologiesadvance. In fact, the UFSOI/ NFD model is now beingevolved into a unified process-based compact model forbulk-Si as well as PD/SOI MOSFETs; and theUFSOI/FD model is being upgraded for possible near-50nm node application and is the basis for a process-based model for double-gate MOSFETs now beingdeveloped at the University of Florida.

AcknowledgmentsThe development of UFSOI models at the University ofFlorida have been supported mainly by theSemiconductor Research Corporation. Many graduatestudents have made key contributions to the developmentover several years. The students include D. Chang, J. Y.Choi, L. Ge, K. Kim, H.-K. Lim, D. Suh, S.Veeraraghavan, G. O. Workman, and P. C. Yeh, inaddition to coauthors Chiang and Pelella.

References1. S. Krishnan and J. G. Fossum, IEEE Circuits & Devices, vol. 14, p.

32, July 1998.

2. G. O. Workman and J. G. Fossum, IEEE Trans. Electron Devices,vol. 45, p. 2138, Oct. 1998.

3. J. G. Fossum, “UFSOI MOSFET Models (Ver. 5.0) User’s Guide,”SOI Group (http://www.soi.tec.ufl.edu), Univ. of Florida,Gainesville, Nov. 1999.

4. D. Suh and J. G. Fossum, IEEE Trans. Electron Devices, vol. 42, p.728, Apr. 1995.

5. P. C. Yeh and J. G. Fossum, IEEE Trans. Electron Devices, vol. 42,p. 1605, Sept. 1995.

6. S. Krishnan and J. G. Fossum, Solid-State Electron., vol. 39, p. 661,May 1996.

7. S. Krishnan, Ph.D. Dissertation, Univ. of Florida, Gainesville, 1996.

8. G. O. Workman and J. G. Fossum, IEEE Trans. Electron Devices,vol. 47, p. 1192, June 2000.

9. G. O. Workman, J. G. Fossum, S. Krishnan, and M. M. Pelella, Jr.,IEEE Trans. Electron Devices, vol. 45, p. 125, Jan. 1998.

10. D. Chang, Ph.D. Dissertation, Univ. of Florida, Gainesville, 1997.

11. M.-H. Chiang and J. G. Fossum, SOI Group Report, Univ. ofFlorida, Gainesville, Nov. 1998.

12. M. M Pelella and J. G. Fossum, Preprint for IEEE Electron DeviceLett., June 2000.

13. M. M. Pelella, J. G. Fossum, M.-H. Chiang, G. O. Workman, and C.R. Tretz, Tech. Digest Internat. Electron Devices Meeting, p. 831,Dec. 1999.

14. D. Suh and J. G. Fossum, Tech. Digest Internat. Electron DevicesMeeting, p. 661, Dec. 1994.

Step 9.

* Extracted Cds is the mean value as a function offrequency.


...continued from page 7

Frequency [GHz]

W / L = 100 / 0.35V = 1V, V = 2Vgs ds

0 2 4 6 8 10

C

[f

F]

jd

160

140

120

100

80

60

40

20

0

Figure 9. Extraction results of Cjd.

Extracted Required EquationParameter

Cds

–Im[Y22] CjdCds = Cgd – gmRgCgdω 1 + ω2 Cjd2 Rsubd

2

+ ω2 Cgd Cdg(Cgs+Cg)R2g

Frequency [GHz]

W / L = 100 / 0.35V = 1V, V = 2Vgs ds

0 2 4 6 8 10

C

[f

F]

ds

60

50

40

30

20

10

0

-10

-20

Figure 10. Extraction results of Cds.


Calendar of Events

12345 10th Fine Process

Technology - Tokyo 6 10th Fine Process

Technology - Tokyo 7 10th Fine Process

Technology - Tokyo 89101112 7th Intl w/s on Active Matrix

and TFT Tech - Tokyo13 7th Intl w/s on Active Matrix

and TFT Tech - Tokyo14 7th Intl w/s on Active Matrix

and TFT Tech - Tokyo15161718192021222324 NSREC - Reno, NV25 NSREC - Reno, NV26 NSREC - Reno, NV27 NSREC - Reno, NV28 NSREC - Reno, NV2930

July1234567891011121314151617181920 2000 Topical on Hetro

Structure Microelectronics – Kyoto, Japan

21 2000 Topical on HetroStructure Microelectronics – Kyoto, Japan



2425262728 Intl Conf on Solid State Devices

and Materials, Sendai, Japan29 Intl Conf on Solid State Devices

and Materials, Sendai, Japan30 Intl Conf on Solid State Devices

and Materials, Sendai, Japan31

August

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