modeling and parameter extraction for the series resistance in thin film transistors

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009 431

Modeling and Parameter Extraction for the SeriesResistance in Thin-Film Transistors

Keum-Dong Jung, Student Member, IEEE, Yoo Chul Kim, Student Member, IEEE,Byung-Gook Park, Member, IEEE, Hyungcheol Shin, Senior Member, IEEE, and Jong Duk Lee, Member, IEEE

Abstract—A new parameter extraction method is proposed forthe series resistance of thin-film transistors (TFTs). By analyz-ing the gate–source overlap region of staggered structure TFTs,the model for the series resistance is derived and utilized forthe parameter extraction. To verify the extraction method, thecharacteristics of amorphous silicon TFTs obtained from TCADsimulation are used. For the devices with different overlap lengths,the extracted parameters are identical to each other, althoughthe series resistances are different due to the narrow overlaplength. When the actual channel length is different from the mask-specified length, the offset length can be effectively corrected bythe new method, so that accurate parameters can be obtained. Be-cause the new method has several advantages such as the accuracyand generality over the conventional method, it can be used forfurther analysis of TFT characteristics.

Index Terms—Channel length offset, contact resistance,modeling, overlap length, parasitic resistance, series resistance,thin-film transistors (TFTs), transfer length.

I. INTRODUCTION

THIN-FILM transistors (TFTs) had been considered to besuitable for large-area switching devices because of their

low fabricating cost compared to the single-crystalline metal–oxide–semiconductor field-effect transistors (MOSFETs). Thepotential capacities of TFTs are recently proven by the successof amorphous silicon (a-Si) TFTs in the liquid crystal displays.Nowadays, the superb uniformity of a-Si TFTs enables morethan 80-in panel [1], and even the driving circuits using a-SiTFTs are commercially integrated into the panel. Following thesuccess of a-Si TFTs, many novel TFTs are being developed forusage in new applications such as active-matrix organic light-emitting diodes and flexible displays [2]–[9].

Concerning the characteristics of TFTs, it is well knownthat not only the mobility of the material but also the series(parasitic) resistance is very important. Contact-limited behav-ior of TFTs has been reported continuously regardless of thesemiconductor materials [10]–[12], so that reducing the seriesresistance is one of the important topics in this area [13]–[16].Various experiments have been conducted to analyze the originand properties of the series resistance [17]–[21], and severalphysical models for the series resistance have been suggested

Manuscript received August 12, 2008. Current version published February 25,2009. This work was supported by the Brain Korea 21 (BK21) program. Thereview of this paper was arranged by Editor C. McAndrew.

The authors are with the Inter-University Semiconductor Research Centerand School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea (e-mail: [email protected]).

Digital Object Identifier 10.1109/TED.2008.2010579

[10], [27], [28], [31]–[33]. In addition, in the TFT compactmodels, the series resistances are always included because theireffects are not negligible for the modeling of I–V charac-teristics [22]–[25].

For the extraction of the series resistance, the total resistanceversus the channel length plot, which is similar to the channelresistance method for silicon MOSFETs [38], has been widelyused. The advantage of the method is that the principle issimple, the fabrication is not hard, yet it gives a lot of usefulinformation. However, looking into the method in detail, theexplanations for the extracted parameters have been slightly dif-ferent from one researcher to another, so it is hard to understandthe physical meaning of the extracted parameters. Moreover,the change of the channel length during the fabrication hasbeen rarely considered for TFTs, while it is closely related tothe extraction of the series resistance. Therefore, the extractionmethod and related models need to be reconsidered to obtainmore accurate series resistance and more physically meaningfulparameters.

In this paper, a new series resistance model and related para-meter extraction method are proposed. First, in Section II, theconventional extraction method is reviewed and its limitationsare examined. The new model for the series resistance is pro-posed in Section III, and the extraction method for the modelingparameters is described in Section IV. For the verification of themethod, some extraction examples with the amorphous siliconTFTs are provided in Section V, and finally, the conclusion isgiven in Section VI.

II. CONVENTIONAL METHOD

For the conventional method, the total resistance Rtot isplotted as a function of the TFT channel length L, and theseries resistance Rsd is found at the point of L = 0 as shownin Fig. 1 [12], [14], [17]–[19], [23], [26]–[30]. The value ofRsd changes with the gate voltage VG, which is typical forTFTs. From the common crossing point which usually existsin the second quadrant, the modeling parameters, such as theempirical parasitic resistance Rp and empirical channel lengthoffset ΔLp, are obtained. From the slope of the graph, theintrinsic semiconductor parameters, such as intrinsic mobilityμi and intrinsic threshold voltage VTHi, can be obtained. For themodeling of Rsd, the following equation [17], [26], [28], [29]or its derivatives [14], [23] are used in various publications:

Rsd = Rp +ΔLp

μiCiW (VG − VTHi)(1)

0018-9383/$25.00 © 2009 IEEE

432 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009

Fig. 1. Typical Rtot−L plot from the conventional parameter extractionmethod.

where W and Ci represent the TFT channel width and theinsulator capacitance per unit area, respectively.

One major limitation of the conventional method is that thereshould be a crossing point in the second quadrant. Although,in many publications, a common crossing point is shown intheir Rtot−L plots [17], [18], [23], [26], [28], [29], lots of otherRtot−L plots seem not to have the common crossing point [12],[27], [30], [36]–[37]. If there is no crossing point, (1) is notapplicable, so that another more complex equation should beused for the modeling of the series resistance.

Even if the common crossing point can be found, the physicalmeaning of the point is not clear, particularly for the empiricalchannel length offset ΔLp. Kanicki et al. insist that ΔLp isassociated with the effective channel length longer than themask-specified channel length in [35], while Luan and Neudeck[26] explain that ΔLp is an empirical parameter which can beconsidered as the length of the accumulation channel resistancein series with Rp. In the a-Si TFT modeling by Servati et al.[23], the obtained ΔLp for TFT set II is observed to be largerthan the total overlap length, so the authors explain that thephenomenon is possibly due to the expansion of channel byvirtue of a highly resistive contact layer. Gundlach et al. [30]comment that ΔLp is twice the transfer length which gives anestimate of the contact area participating in charge injection.In summary, the meaning of ΔLp is uncertain and has beeninterpreted as the mixture of the effective channel length, thechannel length offset during the fabrication, and the transferlength.

III. ANALYSIS OF SERIES RESISTANCE

Previous analyses on the gate–source overlap region havederived the analytic equations for the series resistance [27],[35]. This section briefly revises the equation and expands itto describe the I–V characteristics of the TFTs.

The cross section of an inverted-staggered TFT, also knownas a top-contact TFT, is shown in Fig. 2(a). An n-type TFT isassumed because a-Si TFTs are n-type. However, the followinganalysis can be applied to any kind of TFTs, such as organicTFTs or amorphous oxide TFTs, as far as it has the staggeredstructure. The TFT consists of one channel region at the centerand two overlap regions at each side. It is assumed that thesource voltage VS is zero while the gate voltage VG is largerthan the threshold voltage VTH. Not to break the symmetryof the device, the drain voltage VD is assumed very small,e.g., 0.1 V.

Fig. 2. (a) Inverted-staggered TFT is composed of one channel region andtwo overlap regions. Bias conditions for the source, drain, and gate electrodesare VS = 0 V, VD = 0.1 V, and VG > VTH, respectively. (b) In the overlapregion, Ix(x) flows through the accumulation layer and Jy(x) flows from theaccumulation layer to the source electrode.

Under this bias condition, the accumulation layer is inducednot only in the channel but also at the bottom of the overlapregion. Because of the small VD, the accumulation layer isalmost uniform, so that the sheet resistance Rsh (in ohms persquare) along the accumulation layer can be considered as aconstant. The relation between Rsh and VG is approximatelygiven as

Rsh ≈ 1μiCi(VG − VTHi)

(2)

where the intrinsic mobility μi is also a function of VG inTFTs [22].

The series resistance Rsd is related to the overlap region inFig. 2(b). Ix(x) and V (x) represent the x-direction current andelectric potential of the accumulation layer, respectively. Out-side of the accumulation layer, the current is assumed to flowonly in y-direction, which can be represented by the currentdensity Jy(x). Ry represents the apparent y-direction resistancenormalized with the area (in ohms square centimeter), and itincludes all resistive components existing in the contact andbulk semiconductor. By using this apparent resistance Ry , thefollowing analysis becomes more simple and intuitive withoutlosing the generality.

JUNG et al.: MODELING AND PARAMETER EXTRACTION FOR THE SERIES RESISTANCE IN TFTs 433

By using these quantities and assumptions, one can obtain thefollowing expressions for Jy(x), Ix(x), and V (x), respectively:

Jy(x)= Jy0

[cosh

(− x

L0

)+ tanh

(Lov

L0

)sinh

(− x

L0

)](3)

Ix(x)= WL0Jy0

[sinh

(− x

L0

)+ tanh

(Lov

L0

)cosh

(− x

L0

)]

(4)

V (x)= RyJy0

[cosh

(− x

L0

)+ tanh

(Lov

L0

)sinh

(− x

L0

)](5)

L0 =√

Ry

Rsh(6)

where Jy0 is the maximum current density at x = 0, Lov is thelength of the overlap region, and L0 is the effective overlaplength given by (6). Here, L0 has the same physical meaningwith the transfer length [34] or the characteristic length [27],[35] in the literature. A detailed derivation procedure is sum-marized in Appendix A.

With the aforementioned equations, Rsd can be derived fromthe total resistance of the overlap region by dividing the totalpotential drop V (x = 0) by the total current Ix(x = 0)

Rsd = 2Rs = 2V (x = 0)Ix(x = 0)

=2Ry

WL0 tanh(Lov/L0)(7)

where the source resistance Rs is the half of Rsd due to thesymmetry. Equation (7) well explains the characteristics of theseries resistance of TFTs. First, Rsd is a function of VG becauseL0 is dependent on VG. Usually, Rsd decreases with largerVG because L0 increases with larger VG. Second, the equationcan account for the effects of the narrow overlap length whichare known to increase Rsd [10], [17]. If Lov � L0, the hyper-bolic tangent term becomes one, so Rsd becomes its minimumvalue. For Lov comparable to L0, Rsd increases because thehyperbolic tangent term becomes less than one. If Lov � L0,L0 is canceled in the denominator because tanh(Lov/L0) ≈Lov/L0, so Rsd is determined only by Lov. Third, as Rsd isproportional to Ry , it can be directly deduced that the badcontact or thick bulk semiconductor would increase Rsd.

Since the current should be continuous at the boundary of thechannel and the overlap region, one can find the following I–Vequation:

IDS = WVD

LRsh + 2Ry

L0 tanh(Lov/L0)

. (8)

In addition, the equation of Jy0 is given by

Jy0 =VD

RshL0L tanh(Lov/L0) + 2Ry. (9)

Therefore, all the electrical quantities in (3)–(9) can be de-termined analytically if L0, Rsh, and Ry are obtained. Adetailed derivation procedure for IDS and Jy0 is summarizedin Appendix B.

IV. PARAMETER EXTRACTION METHOD

Similar to the conventional method, the Rtot−L plot is usedfor the new parameter extraction method. However, the major

Fig. 3. For the parameter extraction, x-intercept, slope, and triangular area areused from the Rtot−L plot.

TABLE IPARAMETERS FROM THE Rtot−L PLOT ARE EXPRESSED WITH Rsh, L0,Ry , AND Lov. WHEN Lov � L0, THE EXPRESSIONS ARE MUCH SIMPLER

difference is that the x-intercepts are used for the new methodinstead of the common crossing point in the conventionalmethod. To derive the relation of Rtot and L, (8) is converted to

Rtot =VD

IDS=

Rsh

WL +

2Ry

WL0 tanh(Lov/L0)

=Rsh

W

[L +

2L0

tanh(Lov/L0)

]. (10)

In Fig. 3, the relation of Rtot and L is plotted, which becomesa straight line with the slope of Rsh/W and the y-intercept ofRsd. In Table I, the x-intercept, y-intercept, and the triangulararea are expressed with Rsh, L0, Ry, and Lov. Therefore, bycomparing the Rtot−L plot with Table I, the parameters suchas Rsd, Rsh, L0, and Ry can be extracted.

If Lov � L0, it is quite easy to extract the parameters. L0

can be directly obtained from the x-intercept because L0 =|x-intercept|/2. Rsh can be found from the slope, and Ry alsocan be obtained with (6). It is interesting to notice that the areaof the triangle in the second quadrant corresponds to the Ry

value.However, in most of the cases, the relation between L0 and

Lov is unknown. Therefore, the following equation should besolved for L0:

|x-intercept| =2L0

tanh (Lov/L0). (11)

It is not so difficult to numerically solve (11) for L0, but inthis paper, a graphical solving method is introduced for more


Fig. 4. (a) X−Y plot from (13) gives L0 value at intersection of the straightline and the curve. (b) If the x-intercept increases for the fixed Lov, L0

increases continuously. (c) If Lov increases for the fixed x-intercept, L0

converges to |x-intercept|/2.

qualitative understanding. Equation (11) can be converted to

L0 =|x-intercept|

2tanh

(Lov

L0

)(12)

so that L0 can be considered as the intersection of the followingtwo graphs:

Y = X

Y =|x-intercept|

2tanh

(Lov

X

). (13)

Therefore, by drawing a χ-shaped X−Y plot as shown inFig. 4(a), one can obtain the value of L0. While the formergraph in (13) is a straight line, the latter graph is a curvewhich yields |x-intercept|/2 for small X and decreases whenX > Lov/2. Fig. 4(b) and (c) shows the effect of x-interceptsand Lov on the extraction of L0, respectively. If x-interceptbecomes larger while Lov is fixed, the values of the curveincrease so that the L0 increases. On the other hand, if Lov

becomes larger while x-intercept is fixed, the bending point ofthe curve increases as shown in Fig. 4(c), so that L0 convergesto |x-intercept|/2. This observation corresponds to the previousdiscussion that L0 = |x-intercept|/2 when Lov � L0. Once L0

is found, it is not difficult to find Rsh and Ry. In summary,the parameter extraction procedure is composed of three steps:1) L0 is obtained from the x-intercept using the X−Y graphicalmethod; 2) Rsh is found from the slope; and 3) Ry is obtainedeither by (6) or by the triangular area.

For the new method mentioned earlier, the actual electricalchannel length considering the channel length offset should be

Fig. 5. Cross section of the simulated BCE a-Si TFTs. The channel lengthoffset ΔL affects both the channel length L and the overlap length Lov.

used instead of the mask-specified channel length. In addition,for Lov, the effects of the channel length offset should beconsidered. Otherwise, extracted Rsd, L0, and Ry may includea significant error due to the inaccurate L and Lov.

To obtain the channel length offset ΔL, the following methodcan be used. Because L0 in (3) is independent on Lov, extractedL0 should be the same for the devices which have different Lov.However, if the mask-specified L and Lov are used withoutconsidering ΔL, the obtained L0 would be different at thefirst extraction. Then, until the same L0 is derived for differentLov, ΔL can be found by guessing ΔL and recalculating L0.Although this method requires additional devices with differentLov, the accuracy is much better than the previously reportedmethod [40] or direct measurement of the actual channellength.

The external resistance Rext, which exists outside of thesource and drain contacts, should also be considered. ForRtot−L plot, Rext increases Rtot by its amount, so that wrongparameters can be obtained due to the increased x-intercept andy-intercept values. However, in most TFTs, Rext(∼Ω) is muchsmaller than Rtot(∼MΩ), so the effect is negligible. Eventhough the external resistance is not negligible, the measure-ment of Rext is not difficult if the dedicated dummy patterns forRext measurement are fabricated. Once Rext value is found, theeffects can easily be eliminated by subtracting Rext from Rtot.

V. VERIFICATION AND DISCUSSION

For the verification of the described method, I–V charac-teristics are obtained from the simulation on the a-Si TFTsusing SILVACO TCAD simulator. The TCAD simulation hastwo advantages in this case. First, the channel length offsetcan be virtually controlled from zero to a finite value, so theextraction method can be verified in various conditions. Second,not only I–V characteristics but also the internal parametersin the overlap region such as Jy(x) in (3) can be obtained, sothe series resistance model can be verified more in detail. Thesimulated TFT is a back-channel-etched (BCE) a-Si TFT shownin Fig. 5. For the simulation, the basic a-Si TFT models and thedefault parameter values are used [39].

Assuming that ΔL is zero, the series resistance and relatedparameters are extracted. The channel lengths L’s are changed


Fig. 6. (a) I–V characteristics of TFT set A with different L. (b) I–Vcharacteristics of TFT set B with different L. Due to the large series resistance,the current of TFT set B is smaller than that of TFT set A.

from 2 to 10 μm, and the overlap lengths Lov’s are changedfrom 0.5 to 10 μm. Fig. 6 shows the linear region I–V char-acteristics of two sets of TFTs. TFT set A and B have Lov of10 and 0.5 μm, respectively, so that the current of TFT set Bis smaller than that of TFT set A due to the narrow Lov. Forthe parameter extraction, the Rtot−L plots are shown in Fig. 7.Because ΔL and Rext are assumed to be zero, the x-interceptsin the plot can be directly used for further analysis. In Fig. 8,the χ-shaped graphical solving method is applied to obtain theeffective overlap length L0. The obtained L0 is exactly thesame for the two TFT sets, although the x-intercepts and y-intercepts are different from each other. This confirms that L0

is determined only by Rsh and Ry , as shown in (5), and notrelated to either Lov or Rsd. Fig. 9(a) shows the obtained L0

as a function of VG. Next, the sheet resistance Rsh is obtainedfrom the slopes of Rtot−L plots, and the results are shown inFig. 9(b). There is no difference between the extracted Rsh fordifferent Lov, because Rsh is not related to Lov. Finally, they-direction apparent resistance Ry is obtained in Fig. 9(c). Ry

can be obtained from either the triangular area in Rtot−L plotor (6), and the obtained Ry’s are identical to each other fordifferent Lov. In conclusion, L0, Rsh, and Ry are sequentiallyobtained from the new extraction method and are the same fordifferent Lov. However, if the conventional extraction methodis used, the two Rtot−L plots in Fig. 7 would be analyzeddifferently because of the different common crossing points,i.e., different Rp and ΔLp.

For the verification of the extracted parameters, Jy(x) atVG = 20 V is calculated using (3) for the two sets of TFTs inFig. 10. The calculated Jy(x) fits very well with the simulation

Fig. 7. (a) Rtot−L plot for TFT set A. (b) Rtot−L plot for TFT set B. Thex-intercepts, the y-intercepts, and the triangular area are different for the twosets of TFTs. Also, the common crossing points in the second quadrant aredifferent.

Fig. 8. X−Y plot to obtain L0. The same L0 is obtained for different overlaplengths. For different VG, L0 changes.

result, so that it can be considered that the model for theoverlap region is correctly derived. In addition, in Fig. 11, theI–V characteristics of L = 0.5, 1, and 2 μm devices, whichare more affected by the series resistance, are calculated with(8). The calculation results also show good agreement with thesimulation results, confirming the usefulness of the extractedparameters for the modeling of the series resistance.

Until now, ΔL is thought to be zero. However, for the realcase, positive or negative ΔL originated from various reasonsalways exists. Therefore, the same simulation and parameterextraction are done again assuming nonzero ΔL. For example,in the case of ΔL = −0.2 μm, the channel length L decreasesfrom 10 to 9.8 μm while the overlap length Lov increases from2 to 2.2 μm. However, for the parameter extraction, the mask-specified L and Lov should be used because ΔL is not known


Fig. 9. Parameters are obtained from the Rtot−L plot as a function of VG.(a) L0 is obtained from the x-intercepts. (b) Rsh is obtained from the slope.(c) Ry is obtained from the triangular area.

prior to the parameter extraction. Fig. 12 shows the χ-shapedX−Y plot without considering ΔL, where L0 is not the samefor different Lov due to the incorrect L and Lov. Then, ΔLis guessed from -0.5 to 0.1 μm to revise L and Lov, and thesame extraction process is done again. In Fig. 13, the obtainedL0 curves for different Lov are shown with the presumed ΔLvalues, and the standard deviations of the obtained L0 are alsopresented for each VG. Finally, from Fig. 14, one can obtainthe assumed ΔL of -0.2 μm from the point which gives theminimum relative error for the obtained L0 curves. In thispaper, the sum of the standard deviation is used for the relativeerror estimation. After the accurate ΔL is obtained, L0 and Ry

can be derived with the accurate L and Lov, and the result wouldbe the same with that of Fig. 9.

The new parameter extraction method is applied to the previ-ous experimental I–V curves obtained by Servati et al. [23].The modeling done by Servati et al. is adequate for thecomparison because it uses two device sets ( TFT set I andTFT set II ) which have different series resistance. However,ΔL cannot be obtained because there is no device whichhas different Lov, so that ΔL is assumed to be zero for thefollowing discussion. By applying the new method to the I–V

Fig. 10. (a) Jy(x) for TFT set A decays exponentially with x. (b) Jy(x)for TFT set B. Due to the narrow overlap, less current flows than TFT set Awhile the peak value of Jy(x) is larger. In both graphs, solid line represents thecalculation results with (3) using L0, Rsh, and Ry of 0.684 μm, 1.01 MΩ/sq.,and 470 kΩ · μm2, respectively.

Fig. 11. Comparison of I–V characteristics from the TCAD simulation andthe calculation with (8) using the extracted parameters.

Fig. 12. X−Y plot to obtain L0 using the mask-specified L and Lov. Theobtained L0’s are different for two Lov’s due to the nonzero ΔL.


Fig. 13. Using the presumed ΔL, L0 and standard deviations are ob-tained for four different Lov’s. (a) ΔL = −0.5 μm. (b) ΔL = −0.2 μm.(c) ΔL = 0 μm. (d) ΔL = 0.1 μm.

Fig. 14. By plotting the relative error of L0 curves, the assumed ΔL of−0.2 μm can be obtained from the minimum relative error point. For therelative error, the summation of the standard deviation in Fig. 13 is used.

characteristics in [23], the X−Y plot can be obtained for thetwo sets of TFTs as shown in Fig. 15. For TFT set I, the obtainedL0’s are always smaller than the overlap length Lov(≈2.5 μm),so that the series resistance is not affected by Lov. However, forTFT set II, the obtained L0’s are relatively larger than Lov, sothat the series resistance becomes larger due to the insufficientoverlap length. In Table II, the obtained L0’s, as well as Ry

and Rsh, are summarized for two different gate voltages. Fromthe obtained parameters, it can be recognized that there are tworeasons for the large series resistance of TFT set II: One is Ry,which is 13 times larger for TFT set II, and the other is in-sufficient Lov. Overall, the series resistance of TFT set II is16 times larger than that of TFT set I at VG of 20 V.

VI. CONCLUSION

A new parameter extraction method is proposed for theseries resistance of staggered structure TFTs and applied for theanalysis of a-Si TFTs. Compared to the conventional method,

Fig. 15. X−Y plot obtained by the new method using the I–V characteristicsin [23]. (a) For TFT set I, L0 is obtained for two different VG’s. (b) For TFTset II, larger L0 is obtained for the same VG than TFT set I.

TABLE IIWITH THE CONVENTIONAL METHOD, Rp AND ΔLp COMPARISON OF THE

PARAMETERS OBTAINED IN [23], AND BY THE NEW METHOD.FOR DIFFERENT GATE VOLTAGES, THE NEW METHOD

DERIVES DIFFERENT PARAMETERS

the new method has the following advantages. First, the methodgives more physically meaningful parameters such as the ef-fective overlap length L0 and apparent resistance Ry . Second,the method can derive the channel length offset ΔL whichhas been hard to obtain. Third, not only the effect of narrowoverlap can be predicted but also the current density and electricpotential inside the overlap region can be calculated. Due tothe aforementioned advantages and the ease of usage, the newmethod and the series resistance model can be useful for thedesign, evaluation, and modeling of TFTs.

APPENDIX

A. Derivation of Jy(x), Ix(x), and V (x)

The derivation of Jy(x), Ix(x), and V (x) is almost the sameto the transmission-line model [38]. By using the assumptions


and Kirchhoff’s law, the following three differential equationscan be derived for the overlap region in Fig. 2(b):

V (x + dx) = V (x) − Ix(x)Rsh(dx/W ) (14)

V (x) − (Jy(x)Wdx) (Ry/Wdx) = 0 (15)

Ix(x) = W

Lov∫x

Jy(x)dx. (16)

By eliminating Ix(x) and V (x), one can derive an equationfor Jy(x)

d2Jy(x)dx2

=Rsh

RyJy(x). (17)

The general solution of the differential equation is given as

Jy(x) = Jy0 cosh(x/L0) + Jy1 sinh(x/L0),

where L0 =√

Ry/Rsh. (18)

By using (14), (16), and (18), Jy1 can be obtained as

Jy1 = −Jy0 tanh(Lov/L0). (19)

Therefore, (3) can be derived as

Jy(x) = Jy0 [cosh(−x/L0) + tanh(Lov/L0) sinh(−x/L0)] .(20)

Finally, Ix(x) and V (x) can be obtained from Jy(x).

B. Derivation of IDS and Jy0

The current should be continuous at the boundary betweenthe channel and the overlap region. First, the current at the edgeof the overlap region can be expressed as

Ix(x = 0) = WL0Jy0 tanh(Lov/L0). (21)

Next, the current flowing through the channel can be ex-pressed as

IDS =W

L

1Rsh

ΔV =W

L

1Rsh

[VD − 2V (x = 0)]

=W

L

1Rsh

[VD − 2RyJy0] (22)

where ΔV represents the potential drop in the channel. Fromthe current continuity, Ix(x = 0) in (21) should be equal to IDS

in (22); therefore

Jy0 =VD/ �RshL0L tanh(Lov/L0) + 2Ry� (23)

IDS =WVD/ �LRsh + 2Ry/ (L0 tanh(Lov/L0))� . (24)

REFERENCES

[1] S. S. Kim, “The world’s largest (82-in.) TFT-LCD,” in Proc. SID Symp.Dig., 2005, vol. 36, pp. 1842–1847.

[2] H. Klauk, D. J. Gundlach, J. A. Nichols, and T. N. Jackson, “Pentaceneorganic thin-film transistors for circuit and display applications,” IEEETrans. Electron Devices, vol. 46, no. 6, pp. 1258–1263, Jun. 1999.

[3] Z. Bao, J. A. Rogers, and H. E. Katz, “Printable organic and polymericsemiconducting materials and devices,” J. Mater. Chem., vol. 9, no. 9,pp. 1895–1904, 1999.

[4] M. Stewart, R. S. Howell, L. Pires, and M. K. Hatalis, “PolysiliconTFT technology for active matrix OLED displays,” IEEE Trans. ElectronDevices, vol. 48, no. 5, pp. 845–851, May 2001.

[5] X. Duan, C. Niu, V. Sahi, J. Chen, J. W. Parce, S. Empedocles, andJ. L. Goldman, “High-performance thin-film transistors using semicon-ductor nanowires and nanoribbons,” Nature, vol. 425, no. 6955, pp. 274–278, Sep. 2003.

[6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono,“Room-temperature fabrication of transparent flexible thin-film transistorsusing amorphous oxide semiconductors,” Nature, vol. 432, no. 7016,pp. 488–492, Nov. 2004.

[7] Y.-H. Kim, D.-G. Moon, and J.-I. Han, “Organic TFT array on a papersubstrate,” IEEE Electron Device Lett., vol. 25, no. 10, pp. 702–704,Oct. 2004.

[8] J. H. Cheon, J. H. Choi, J. H. Hur, J. Jang, H. S. Shin, J. K. Jeong,Y. G. Mo, and H. K. Chung, “Active-matrix OLED on bendable metalfoil,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1273–1276,May 2006.

[9] J.-H. Ahn, H.-S. Kim, K. J. Lee, Z. Zhu, E. Menard, R. G. Nuzzo, andJ. A. Rogers, “High-speed mechanically flexible single-crystal siliconthin-film transistors on plastic substrates,” IEEE Electron Device Lett.,vol. 27, no. 6, pp. 460–462, Jun. 2006.

[10] G. E. Possin, D. E. Castleberry, W. W. Piper, and H. G. Parks,“Contact-limited behavior in amorphous-silicon FET for applications tomatrix-addressed liquid-crystal displays,” in Proc. SID, 1985, vol. 26,pp. 183–189.

[11] G. Horowitz, “Organic thin film transistors: From theory to real devices,”J. Mater. Res., vol. 19, no. 7, pp. 1946–1962, Jul. 2004.

[12] M. Kim, J. H. Jeong, H. J. Lee, T. K. Ahn, H. S. Shin, J.-S. Park,J. K. Jeong, Y.-G. Mo, and H. D. Kim, “High mobility bottom gateInGaZnO thin film transistors with SiOx etch stopper,” Appl. Phys. Lett.,vol. 90, no. 21, p. 212 114, May 2007.

[13] G. N. Parsons, “Enhanced mobility top-gate amorphous silicon thin-filmtransistor with selectively deposited source/drain contacts,” IEEE Elec-tron Device Lett., vol. 13, no. 2, pp. 80–82, Feb. 1992.

[14] H.-W. Zan, T.-C. Chang, P.-S. Shih, D.-Z. Peng, P.-Y. Kuo, T.-Y. Huang,C.-Y. Chang, and P.-T. Liu, “A study of parasitic resistance effects in thin-channel polycrystalline silicon TFTs with tungsten-clad source/drain,”IEEE Electron Device Lett., vol. 24, no. 8, pp. 509–511, Aug. 2003.

[15] M. Chikamatsu, S. Nagamatsu, T. Taima, Y. Yoshida, N. Sakai,H. Yokokawa, K. Saito, and K. Yase, “C60 thin-film transistors withlow work-function metal electrodes,” Appl. Phys. Lett., vol. 85, no. 12,pp. 2396–2398, Sep. 2004.

[16] J.-S. Park, J. K. Jeong, Y.-G. Mo, H. D. Kim, and S. I. Kim, “Improve-ments in the device characteristics of amorphous indium gallium zincoxide thin-film transistors by Ar plasma treatment,” Appl. Phys. Lett.,vol. 90, no. 26, p. 262 106, Jun. 2007.

[17] C.-Y. Chen and J. Kanicki, “Origin of series resistances in a-Si:H TFTs,”Solid State Electron., vol. 42, no. 5, pp. 705–713, May 1998.

[18] E. J. Meijer, G. H. Gelinck, E. Van Veenendaal, B.-H. Huisman,D. M. De Leeuw, and T. M. Klapwijk, “Scaling behavior and parasiticseries resistance in disordered organic field-effect transistors,” Appl. Phys.Lett., vol. 82, no. 25, pp. 4576–4578, Jun. 2003.

[19] G. B. Blanchet, C. R. Fincher, M. Lefenfeld, and J. A. Rogers, “Contactresistance in organic thin film transistors,” Appl. Phys. Lett., vol. 84, no. 2,pp. 296–298, Jan. 2004.

[20] P. V. Pesavento, R. J. Chesterfield, C. R. Newman, and C. D. Frisble,“Gated four-probe measurements on pentacene thin-film transistors: Con-tact resistance as a function of gate voltage and temperature,” J. Appl.Phys., vol. 96, no. 12, pp. 7312–7324, Dec. 2004.

[21] K. P. Puntambekar, P. V. Pesavento, and C. D. Frisbie, “Surface potentialprofiling and contact resistance measurements on operating pentacenethin-film transistors by Kelvin probe force microscopy,” Appl. Phys. Lett.,vol. 83, no. 26, pp. 5539–5541, Dec. 2003.

[22] M. S. Shur, H. C. Slade, M. D. Jacunski, A. A. Owusu, andT. Ytterdal, “SPICE models for amorphous silicon and polysilicon thinfilm transistors,” J. Electrochem. Soc., vol. 144, no. 8, pp. 2833–2839,Aug. 1997.

[23] P. Servati, D. Striakhilev, and A. Nathan, “Above-threshold parame-ter extraction and modeling for amorphous silicon thin-film transis-tors,” IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2227–2235,Nov. 2003.

[24] M. Estrada, A. Cerdeira, J. Puigdollers, L. Resendiz, J. Pallares,L. F. Marsal, C. Voz, and B. Iniguez, “Accurate modeling and parameter


extraction method for organic TFTs,” Solid State Electron., vol. 49, no. 6,pp. 1009–1016, Jun. 2005.

[25] D. Natali, L. Fumagalli, and M. Sampietro, “Modeling of organic thin filmtransistors: Effect of contact resistances,” J. Appl. Phys., vol. 101, no. 1,p. 014 501, Jan. 2007.

[26] S. Luan and G. W. Neudeck, “An experimental study of the source/drainparasitic resistance effects in amorphous silicon thin film transistors,”J. Appl. Phys., vol. 72, no. 2, pp. 766–772, Jul. 1992.

[27] C.-S. Chiang, S. Martin, J. Kanicki, Y. Ugai, T. Yukawa, and S. Takeuchi,“Top-gate staggered amorphous silicon thin-film transistors: Series resis-tance and nitride thickness effects,” Jpn. J. Appl. Phys., vol. 37, no. 11,pp. 5914–5920, Nov. 1998.

[28] S. Martin, C.-S. Chiang, J.-Y. Nahm, T. Li, J. Kanicki, and Y. Ugai,“Influence of the amorphous silicon thickness on top gate thin-film tran-sistor electrical performances,” Jpn. J. Appl. Phys., vol. 40, no. 2A,pp. 530–537, Feb. 2001.

[29] J. Zaumseil, K. W. Baldwin, and J. A. Rogers, “Contact resistance inorganic transistors that use source and drain electrodes formed by softcontact lamination,” J. Appl. Phys., vol. 93, no. 10, pp. 6117–6124,May 2003.

[30] D. J. Gundlach, L. Zhou, J. A. Nichols, T. N. Jackson, P. V. Necliudov,and M. S. Shur, “An experimental study of contact effects in organic thinfilm transistors,” J. Appl. Phys., vol. 100, no. 2, pp. 024 509-1–024 509-13,Jul. 2006.

[31] R. R. Troutman and A. Kotwal, “Device model for the amorphous-siliconstaggered-electrode thin-film transistor,” IEEE Trans. Electron Devices,vol. 36, no. 12, pp. 2915–2922, Dec. 1989.

[32] H. H. Busta, J. E. Pogemiller, R. W. Standley, and K. D. Mackenzie,“Self-aligned bottom-gate submicrometer-channel-length a-Si:H thin-filmtransistors,” IEEE Trans. Electron Devices, vol. 36, no. 12, pp. 2883–2888, Dec. 1989.

[33] S. M. Gadelrab and S. G. Chamberlain, “The effects of metal-n+ interfaceand space charge limited conduction on the performance of amorphoussilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 41, no. 3,pp. 462–464, Mar. 1994.

[34] W. Shockley, A. Goetzberger, and R. M. Scarlett, “Research and investiga-tion of inverse epitaxial UHF power transistors,” Air Force Avionics Lab.,Air Force Syst. Command, Wright-Patterson Air Force Base, Dayton, OH,Final Tech. Rep. AL-TDR-64-207, Sep. 1964.

[35] C. R. Kagan and P. Andry, Thin-Film Transistors. New York: MarcelDekker, 2003.

[36] A. Rolland, J. Richard, J. P. Kleider, and D. Mencaraglia, “Source anddrain parasitic resistances of amorphous silicon transistors: Comparisonbetween top nitride and bottom nitride configurations,” Jpn. J. Appl.Phys., vol. 35, no. 1, pp. 4257–4260, Aug. 1996.

[37] P. V. Necliudova, M. S. Shur, D. J. Gundlach, and T. N. Jackson, “Con-tact resistance extraction in pentacene thin film transistors,” Solid StateElectron., vol. 47, no. 2, pp. 259–262, Feb. 2003.

[38] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices.Cambridge, U.K.: Cambridge Univ. Press, 1998.

[39] ATLAS User’s Manual, Silvaco Int., Santa Clara, CA, 2002.[40] K.-D. Jung, B.-J. Kim, Y. C. Kim, B.-G. Park, H. Shin, and J. D. Lee, “A

novel gated transmission line method for organic thin film transistors,” inProc. Int. Semicond. Device Res. Symp., 2007, pp. 1–2.

Keum-Dong Jung (S’06) was born in Korea onNovember 1, 1978. He received the B.S. degree inelectrical engineering and the Ph.D. degree in elec-trical engineering and computer science from SeoulNational University, Seoul, Korea, in 2001 and 2009,respectively.

From 2001 to 2003, he was with Ahnlab, Inc.,where he developed the network server using theC++ programming language. He is currently withthe Inter-University Semiconductor Research Centerand School of Electrical Engineering, Seoul National

University. His previous research interest was the display devices. His currentresearch interest includes the fabrication, characterization, and modeling ofTFTs, including a-Si and organic TFTs.

Yoo Chul Kim (S’07) was born in Seoul, Korea, in1980. He received the B.S. and M.S. degrees in elec-trical engineering from Seoul National University,Seoul, in 2006 and 2008, respectively.

He is currently with the Inter-University Semi-conductor Research Center and School of ElectricalEngineering, Seoul National University. His currentresearch interests include modeling, measurement,and fabrication of organic thin-film transistors.

Byung-Gook Park (M’90) received the B.S. andM.S. degrees in electronics engineering from SeoulNational University (SNU), Seoul, Korea, in 1982and 1984, respectively, and the Ph.D. degree inelectrical engineering from Stanford University,Stanford, CA, in 1990.

From 1990 to 1993, he was with the AT&T BellLaboratories, where he contributed to the develop-ment of 0.1-μm CMOS and its characterization.From 1993 to 1994, he was with Texas Instruments,developing 0.25-μm CMOS. Since 1994, he has been

with the School of Electrical Engineering (SoEE), SNU, where he was first anAssistant Professor and is currently a Professor. In 2002, he was with StanfordUniversity as a Visiting Professor, on his sabbatical leave from SNU. Hehas been leading the Inter-university Semiconductor Research Center (ISRC),SNU, as the Director since June 2008. His current research interests include thedesign and fabrication of nanoscale CMOS, flash memories, silicon quantumdevices, and organic thin-film transistors. He has authored and coauthored over580 research papers in journals and conferences and currently holds 34 Koreanand 7 U.S. patents.

Prof. Park has served as a committee member on several international con-ferences, including Microprocesses and Nanotechnology, IEEE InternationalElectron Devices Meeting, International Conference on Solid State Devices andMaterials, and IEEE Silicon Nanoelectronics Workshop (Technical ProgramChair in 2005 and General Chair in 2007). He is currently serving as anExecutive Director of the Institute of Electronics Engineers of Korea (IEEK)and a Board Member of IEEE Seoul Section. He received “Best Teacher”Award from SoEE in 1997, Doyeon Award for Creative Research from ISRC in2003, Haedong Paper Award from IEEK in 2005, and Educational Award fromCollege of Engineering, SNU, in 2006.

Hyungcheol Shin (S’92–M’93–SM’00) received theB.S. (magna cum laude) and M.S. degrees in elec-tronics engineering from Seoul National University,Seoul, Korea, in 1985 and 1987, respectively, andthe Ph.D. degree in electrical engineering from theUniversity of California, Berkeley, in 1993.

From 1994 to 1996, he was a Senior DeviceEngineer with Motorola Advanced Custom Tech-nologies. In 1996, he was with the Departmentof Electrical Engineering and Computer Sciences,Korea Advanced Institute of Science and Technology

(KAIST), Daejeon, Korea. During his sabbatical leave from 2001 to 2002,he was a Staff Scientist with Berkana Wireless, Inc., San Jose, CA, wherehe was in charge of CMOS RF modeling. Since 2003, he has been withthe School of Electrical Engineering and Computer Science, Seoul NationalUniversity. He has published over 300 technical papers in international journalsand conference proceedings. He also wrote a chapter in a Japanese bookon plasma charging damage and semiconductor device physics. His currentresearch interests include nano-CMOS, Flash memory, DRAM cell transistors,CMOS RF, and noise.

Prof. Shin is a lifetime member of the Institute of Electronics Engineersof Korea (IEEK). He was a committee member of the International ElectronDevices Meeting. He has also served as a committee member of severalinternational conferences, including the International Workshop on CompactModeling, and as a committee member of the IEEE EDS Graduate StudentFellowship. He received the Second Best Paper Award from the AmericanVacuum Society in 1991, the Excellent Teaching Award from the Department ofElectrical Engineering and Computer Sciences, KAIST, in 1998, The HaedongPaper Award from IEEK in 1999, and the Excellent Teaching Award from SeoulNational University in 2005 and 2007. He is listed in Who’s Who in the World.


Jong Duk Lee (M’79) was born in Youngchun,Kyungpook, Korea. He received the B.S. degreein physics from Seoul National University (SNU),Seoul, Korea, in 1966, and the Ph.D. degree fromthe Department of Physics, University of NorthCarolina, Chapel Hill, in 1975.

He was with the Department of Applied Physics,College of Engineering, SNU, as a Teaching As-sistant until 1970. From 1975 to 1978, he was anAssistant Professor with the Department of Electron-ics Engineering, Kyungpook National University,

Gyeongbuk, Korea. In 1978, he studied microelectric technology in HP-ICL,Palo Alto, CA. Afterward, he was with the Korea Institute of Electronic Tech-nology (KIET) as the Director of the semiconductor division. He establishedthe KIET Kumi Facility and introduced the first polysilicon gate technologyin Korea by developing 4K SRAM, 32K and 64K Mask ROM’s, and one-chip8-b microcomputer. In July 1983, he moved to the Department of ElectronicsEngineering, SNU, which has been merged to School of Electrical Engineering,in 1992, where he is currently a Professor. He started to establish the Inter-University Semiconductor Research Center, SNU, in 1985, where he served asthe Director from 1987 to 1989. He served as the Chairman of the ElectronicsEngineering Department, SNU, from 1994 to 1996. He worked for SamsungSDI Company, Ltd., as the Head of Display R&D Center for a year on theleave of SNU in 1996. Since 1985, he has been concentrating his study on theimage sensors such as Vidicon type, MOS type, and also CCD to help SamsungSDI Co. and Samsung Electronics Co. His current research interests includesub-0.1-μm CMOS structure and technology, CMOS image sensors and fieldemission display, and organic TFTs.

Dr. Lee is a member of KPS, KVS, IEEK, and KIDS. He is also a lifetimemember of CAST (Korean Academy of Science and Technology). He wasa member of IEEE (M’78), SID, AVS, and ECS. He was also a member ofthe steering committee for International Vacuum Microelectronics Conference(IVMC) from 1997 to 2001 and Korean Conference on Semiconductors (KCS)from 1998 to 2008. He was the Conference Chairman of IVMC’97 and KCS’98who led the IVMC’97 and the KCS’98 successfully. He was also a member ofInternational Electron Devices Meeting Subcommittee on Detectors, Sensorsand Displays operated by IEEE Electron Devices Society from 1998 to 1999.He was the first President of the Korean Information Display Society fromJune 1999 to December 31, 2001. He initiated the International Meeting onInformation Display for KIDS activity and served as the first OrganizationChairman in 2001.

modeling and parameter extraction for the series resistance in thin film transistors

Documents