mitac 8575a service manual

SERVICE MANUAL FOR

8575A8575A8575A8575A

SERVICE MANUAL FORSERVICE MANUAL FOR

8575A8575A8575A8575A8575A8575A8575A8575A

TESTING TECHNOLOGY DEPARTMENT / TSSCTESTING TECHNOLOGY DEPARTMENT / TSSC

Aug . 2002

BY: Sissel DiaoSissel Diao8 5 7 5 A

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85758575A N/B MaintenanceA N/B Maintenance

Contents

1. Hardware Engineering Specification …………………………………………………………………

Introduction ………………………………………………………………………………………………………….1.2 System Hardware Parts ……………………………………………………………………………………………. 1.3 Other Functions …………………………………………………………………………………………………….. 1.4 Peripheral Components ……………………………………………………………………………………………..1.5 Power Management …………………………………………………………………………………………………1.6 Appendix 1: SiS961 GPIO Definitions ……………………………………………………………………………..1.7 Appendix 2: H8 Pins Definitions ……………………………………………………………………………………

2. System View and Disassembly ………………………………………………………………………...2.1 System View ………………………………………………………………………………………………………….2.2 System Disassembly …………………………………………………………………………………………………

3. Definition & Location of Connectors / Switches ……………………………………………………..Mother Board ………………………………………………………………………………………………………..

3.2 DC Power Board …………………………………………………………………………………………………….3.3 ESB Board …………………………………………………………………………………………………………...3.4 Touch-pad ……………………………………………………………………………………………………………3.5 Daughter Board ……………………………………………………………………………………………………..

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Contents

4. Definition & Location of Major Component …………………………………………………………Mother Board ………………………………………………………………………………………………………..

5. Pin Description of Major Component ………………………………………………………………...

Intel Pentium 4 Processor mPGA478 Socket ……………………………………………………………………...5.2 SiS650 IGUI Host / Memory Controller …………………………………………………………………………... 5.3 SiS691 MuTIOL Media I/O Controller ……………………………………………………………………………5.4 SiS301LV / Chrontel CH7019 TV/LVDS Encoder ………………………………………………………………..5.5 PCI1410GGU PCMCIA Controller ………………………………………………………………………………..5.6 uPD72872 IEEE1394 Controller ……………………………………………………………………………………

6. System Block Diagram …………………………………………………………………………………

7. Maintenance Diagnostics ………………………………………………………………………………7.1 Introduction ………………………………………………………………………………………………………….7.2 Error Codes ………………………………………………………………………………………………………….7.3 Maintenance Diagnostics ……………………………………………………………………………………………

8. Trouble Shooting ……………………………………………………………………………………….No Power ……………………………………………………………………………………………………………..

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Contents

8.2 No Display ……………………………………………………………………………………………………………8.3 VGA Controller Failure LCD No Display …………………………………………………………………………8.4 External Monitor No Display ………………………………………………………………………………………8.5 Memory Test Error …………………………………………………………………………………………………8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error …………………………………………………………………….8.7 Hard Disk Drive Test Error ………………………………………………………………………………………..8.8 CD-ROM Driver Test Error ………………………………………………………………………………………..8.9 USB Test Error ………………………………………………………………………………………………………8.10 PIO Port Test Error ……………………………………………………………………………………………….8.11 Audio Failure ………………………………………………………………………………………………………8.12 LAN Test Error ……………………………………………………………………………………………………8.13 PC Card Socket Failure ……………………………………………………………………………………………8.14 IEEE 1394 Failure …………………………………………………………………………………………………

9. Spare Parts List ………………………………………………………………………………………..

10. System Exploded Views ………………………………………………………………………………

11. Circuit Diagram ………………………………………………………………………………………

12. Reference Material ……………………………………………………………………………………

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1. Hardware Engineering Specification

1.1 IntroductionThe 8575A motherboard would support the Intel® Pentium® 4 processor with FC-PGA2 packaged, using 478-Pin micro PGA (mPGA478) socket, which will supports different speeds up to Willamette P4 1.7GHz (Throttling)/Northwood above 2.0GHz (Throttling).

The memory subsystem supports 0MB on board memory, two JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM), support PC2100 & PC2700.

This system is based on PCI architecture, which have standard hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface (ACPI) 1.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing F2 at system start up or warm reset. System also provides icon LEDs to display system status, such as power indicator, HDD/CDROM, NUM LOCK, CAP LOCK, SCROLL LOCK, SUSPEND MODE and Battery charging status. It also equipped 2 USB ports.

SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media I/O.

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85758575A N/B MaintenanceA N/B MaintenanceThe SiS961 MuTIOL® Media I/O integrates the Audio Controller with AC 97 Interface, the Ethernet MAC, the Dual Universal Serial Bus Host Controllers, the IDE Master/Slave controllers, and the MuTIOL® Connect to PCI bridge. The PCI to LPC bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O, I/O Advanced Programmable Interrupt Controller and legacy power management functionalities are also integrated. The SiS961 also incorporates an universal interface supporting the asynchronous inputs/outputs of the X86 compatible microprocessors like P4.

The SiS301LV is a Display device which has two data operation paths. Channel B path is selected when SiS301LV performs TV or LCD only display function. There’s scaling hardware in this path. In LCD display mode, this hardware can make lower VGA resolution display to fit up to 1280x1024 LCD panel. In TV display mode, this scaler can provide overscan and underscan option for TV. At TV and LCD simultaneous display mode, TV data stream run through Channel B and LCD data stream run through Channel A.

To provide for the increasing number of multimedia applications, the AC97 CODEC ALC201 is integrated onto the motherboard.

A full set of software drivers and utilities are available to allow advanced operating systems such as Windows Me and Windows 2000 to take full advantage of the hardware capabilities such as bus mastering IDE, Windows 95-ready Plug & Play, Advanced Power Management (APM) and Advance configuration and power interface (ACPI).

Following chapters will have more detail description for each individual sub-systems and functions.

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1.2 System Hardware Parts

CPU Mobile Intel® Pentium® 4 Processor – M Built on 0.13-micron process Available speeds 1.80GHz, 1.70GHz, 1.60GHz, 1.50GHz, 1.40GHz Intel® Pentium® 4 processor; Willamette/Northwood with mFCPGA2 Package, mPGA 478 Socket Support up to Willamette P4 1.7GHz (Throttling) / Northwood above 2.0 GHz(Throttling) FSB 400MHz /PC 2100/1600

Core logic SiS 650+SiS961: Host & Memory & AGP Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance memory controller, a AGP interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media IO.

VGA Control SiS301LV System BIOS 256KB Flash EPROM

Inside -Includes System BIOS, VGA BIOS, and plug & Play capability, ACPI Memory 0MB on board memory

-Two JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM) -Support PC2100 & PC2700

Video Memory 8/16/32/64 UMA Clock Generator DDR Clock Buffer

ICS 952001 ICS 93722

Embedded controller Hitachi H8 3437S PCMCIA Card Bus Controller: TI PCI1410

One type II slot/ Card Bus support/ No ZV port support Power Switch : TI TPS2211

Audio System AC97 CODEC: Advance Logic, Inc, ALC201 Power Amplifier: TI TPA0202

Super I/O NS PC87393 Modem 56Kbps (V.90, worldwide) MDC Modem PHY of LAN ICS1893Y-10 10/100 base T PHY IEEE1394 IEEE1394 OHCI Controller : NEC uPD72872

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Built on 0.13-micron process technology and Intel® NetBurst™ micro-architecture, the Mobile Intel®Pentium® 4 Processor - M represents a new generation of mobile computing. It provides superior capabilities for graphics-intensive multimedia applications, and processor-intensive background computing tasks such as compression, encryption, and virus scanning. Enhanced Intel® SpeedStep® technology helps to optimize application performance and power consumption, and Deeper Sleep Alert State, a dynamic power management mode, adjusts voltage during brief periods of inactivity - even between keystrokes - for longer battery life. Innovative Micro FCPGA packaging technology enables the processor to fit into small form factors, such as thin-and-light notebooks.

The Intel® Pentium® 4 processor, Intel’s most advanced, most powerful processor, is based on the new Intel®NetBurst™ micro-architecture. The Pentium 4 processor is designed to deliver performance across applications and usages where end users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multi-media, and multi-tasking user environments. The Intel Pentium 4 processor delivers this world-class performance for consumer enthusiast and business professional desktop users as well as for entry-level workstation users.

1.2.1 CPU_Intel Pentium 4 Processor

Highlights of the Pentium 4 Processor :

Available at speeds ranging from 1.50 to 2 GHz

Featuring the new Intel NetBurst micro-architecture

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85758575A N/B MaintenanceA N/B MaintenanceSupported by the SiS650 chipset

Fully compatible with existing Intel Architecture-based software

Internet Streaming SIMD Extensions 2

Intel® MMX™ media enhancement technology

Memory cache ability up to 4 GB of addressable memory space and system memory scalability up to 64GB of physical memory

Support for uni-processor designs

Based upon Intel’s 0.18 micron manufacturing process

The Intel NetBurst micro-architecture delivers a number of new and innovative features including Hyper Pipelined Technology, 400 MHz System Bus, Execution Trace Cache, and Rapid Execution Engine as well as a number of enhanced features Advanced Transfer Cache, Advanced Dynamic Execution, Enhanced Floating-point and Multi-media Unit, and Streaming SIMD Extensions 2. Many of these new innovations and advances were made possible with improvements in processor technology, process technology, and circuit design that could not previously be implemented in high-volume, manufacturable solutions. The features and resulting benefits of the new micro-architecture are defined below.

Intel Pentium 4 Processor Product Feature Highlights

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85758575A N/B MaintenanceA N/B MaintenanceHyper Pipelined Technology:

The hyper-pipelined technology of the NetBurst micro-architecture doubles the pipeline depth compared tothe P6 micro-architecture used on today’s Pentium III processors. One of the key pipelines, the branch prediction/ recovery pipeline, is implemented in 20 stages in the NetBurst micro-architecture, compared to10 stages in the P6 micro-architecture. This technology significantly increases the performance, frequency, and scalability of the processor.

400 MHZ System Bus:

The Pentium4 processor supports Intel’s highest performance desktop system bus by delivering 3.2 GBof data per second into and out of the processor. This is accomplished through a physical signaling scheme of quad pumping the data transfers over a 100-MHz clocked system bus and a buffering scheme allowingfor sustained 400-MHz data transfers. This compares to 1.06 GB/s delivered on the Pentium III processor’s133-MHz system bus.

Level 1 Execution Trace Cache:

In addition to the 8KB data cache, the Pentium 4 processor includes an Execution Trace Cache that stores up to 12K decoded micro-ops in the order of program execution. This increases performance by removing the decoder from the main execution loop and makes more efficient usage of the cache storage space sinceinstructions that are branched around are not stored. The result is a means to deliver a high volume of instructions to the processor’s execution units and a reduction in the overall time required to recover from branches that have been mis-predicted.

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85758575A N/B MaintenanceA N/B MaintenanceRapid Execution Engine:

Two Arithmetic Logic Units (ALUs) on the Pentium 4 processor are clocked at twice the core processorfrequency. This allows basic integer instructions such as Add, Subtract, Logical AND, Logical OR, etc. to execute in half a clock cycle. For example, the Rapid Execution Engine on a 1.50 GHz Pentium 4 processorruns at 3 GHz.

256KB, Level 2 Advanced Transfer Cache:

The Level 2 Advanced Transfer Cache (ATC) is 256KB in size and delivers a much higher data throughputchannel between the Level 2 cache and the processor core. The Advanced Transfer Cache consists of a 256-bit (32-byte) interface that transfers data on each core clock. As a result, the Pentium 4 processor 1.50 GHz can deliver a data transfer rate of 48 GB/s. This compares to a transfer rate of 16 GB/s on the Pentium III processor at 1 GHz. Features of the ATC include:

Non-Blocking, full speed, on-die Level 2 cache 8-way set associativity 256-bit data bus to the level 2 cache Data clocked into and out of the cache every clock cycle

Advanced Dynamic Execution:

The Advanced Dynamic Execution engine is a very deep, out-of-order speculative execution engine that keeps the execution units executing instructions. The Pentium 4 processor can also view 126 instructions in flight and handle up to 48 loads and 24 stores in the pipeline. It also includes an enhanced branch prediction algorithm that has the net effect of reducing the number of branch mis-predictions by about 33% over the P6 generation processor’s branch prediction capability. It does this by implementing a 4KB branch target buffer that stores more detail on the history of past branches, as well as by implementing a more advanced branch prediction algorithm.

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85758575A N/B MaintenanceA N/B MaintenanceEnhanced Floating-Point and Multimedia Unit:

The Pentium 4 processor expands the floating-point registers to a full 128-bit and adds an additional registerfor data movement which improves performance on both floating-point and multimedia applications.

Internet Streaming SIMD Extensions 2 (SSE2):

With the introduction of SSE2, the NetBurst micro-architecture now extends the SIMD capabilities thatMMX technology and SSE technology delivered by adding 144 new instructions. These instructions include128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. These new instructions reduce the overall number of instructions required to execute a particular program task and as a result can contribute to an overall performance increase. They accelerate a broad range of applications, including video, speech, and image, photo processing, encryption, financial, engineering and scientific applications.

Features Used for Test and Performance / Thermal Monitoring:

Built-in Self Test (BIST) provides single stuck-at fault coverage of the micro-code and large logic arrays, as well as testing of the instruction cache, data cache, Translation Lookaside Buffers (TLBs), and ROMs.

IEEE 1149.1 Standard Test Access Port and Boundary Scan mechanism enables testing of the Pentium 4 processor and system connections through a standard interface.

Internal performance counters can be used for performance monitoring and event counting.

Includes a new Thermal Monitor feature that allows motherboards to be cost effectively designed to expected application power usages rather than theoretical maximums.

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1.2.2 System Frequency

1.2.2.1 System frequency synthesizer_ICS952001

Programmable Timing Control Hub™ for P4™ processor

General Description :

The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks signals for such a system.

The ICS952001 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.

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85758575A N/B MaintenanceA N/B MaintenanceRecommended Application:

2 - Pairs of differential CPUCLKs @ 3.3V

1 - SDRAM @ 3.3V

8 - PCI @3.3V

2 - AGP @ 3.3V

2 - ZCLKs @ 3.3V

1 - 48MHz, @3.3V fixed

1 - 24/48MHz, @3.3V selectable by I2 C

3 - REF @3.3V, 14.318MHz

SiS645/650 style chipsets

Output features:

Key Specifications:

PCI - PCI output skew: < 500ps

CPU - SDRAM output skew: < 1ns

AGP - AGP output skew: <150ps

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85758575A N/B MaintenanceA N/B MaintenanceFeatures/Benefits:

Programmable output frequency, divider ratios, output rise/fall time, output skew.

Programmable spread percentage for EMI control.

Watchdog timer technology to reset system if system malfunctions

Programmable watch dog safe frequency.

Support I2 C Index read/write and block read/write operations

For PC133 SDRAM system use the ICS9179-06 as the memory buffer.

For DDR SDRAM system use the ICS93705 as the memory buffer.

Uses external 14.318MHz crystal.

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85758575A N/B MaintenanceA N/B Maintenance1.2.2.2 DDR buffer frequency synthesizer_ICS93722

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Recommended Application:

Low skew, low jitter PLL clock driver

I2 C for functional and output control

Feedback pins for input to output synchronization

Spread Spectrum tolerant inputs

3.3V tolerant CLK_INT input

SiS645/650 style chipsets

Product description/features:

PEAK - PEAK jitter (66MHz): <120ps

PEAK - PEAK jitter (>100MHz): <75ps

CYCLE - CYCLE jitter (66MHz): <120ps

CYCLE - CYCLE jitter (>100MHz): <65ps

OUTPUT - OUTPUT skew: <100ps

Output Rise and Fall Time: 650ps - 950ps

DUTY CYCLE: 49.5% - 50.5%

Switching Characteristics

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1.2.3 Core Logic_SiS650 + SiS961

1.2.3.1 SiS650 IGUI Host/Memory Controller

SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media IO.

SiS650 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-die termination to support Intel Pentium 4 processors. SiS650 provides a 12-level In-Order-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4 series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition to integrated GUI, SiS650 also can support external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature SiS MuTIOL® technology is incorporated to connect SiS650 and SiS961 MuTIOL® Media I/O together. SiS MuTIOL® technology is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533 MB/s bandwidth from/to Multi-threaded I/O Link layer to/from SiS650, and the Multi-threaded I/O Link Encoder/Decoder in SiS650 to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from SiS961.

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85758575A N/B MaintenanceA N/B MaintenanceAn Unified Memory Controller supporting PC133 or DDR266 DRAM is incorporated, delivering a high performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The SiS650 adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.

The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture, and a 128 bit 2D accelerator with 1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware acceleration logic to deliver high quality DVD playback. A Dual 12 bit DDR digital video link interfaced toSiS 301B Video Bridge packaged in 100-pin PQFP is incorporated to expand the SiS650 functionality to support the secondary display, in addition to the default primary CRT display. The SiS301B Video Bridge integrates an NTSL/PAL video encoder with Macro Vision Ver. 7.1.L1 option for TV display, a TMDS transmitter with Bi-linear scaling capability for TFT LCD panel support, and an analog RGB port to support a secondary CRT. The primary CRT display and the extended secondary display (TV, TFT LCD Panel, 2'ndCRT) features the Dual View Capability in the sense that both can generate the display in independent resolutions, color depths, and frame rates.

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85758575A N/B MaintenanceA N/B MaintenanceTwo separate buses, Host-t-GUI in the width of 64 bit, and GUI-t-Memory Controller in the width of 128 bit are devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In PC133, or DDR266 memory subsystem, the 128 bit GUI-t-MC bus will attain the AGP4X or AGP 8X equivalent texture transfer rate, respectively. The Memory Controller mainly comprises the Memory Arbiter, the M-data/M-Command Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP controller, Host Controller, and I/O bus masters based on a default optimized priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data queue, any command compliant to the paging mechanism is generated and pushed into the M-CMD queue. The M-data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by scheduling the command requests in the background when the data requests streamlines in the foreground.

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85758575A N/B MaintenanceA N/B Maintenance1.2.3.2 SiS961 MuTIOL® Media I/O overview

The SiS961 MuTIOL® Media I/O integrates the Audio Controller with AC 97 Interface, the Ethernet MAC, the Dual Universal Serial Bus Host Controllers, the IDE Master/Slave controllers, and the MuTIOL®Connect to PCI bridge. The PCI to LPC bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O, I/O Advanced Programmable Interrupt Controller and legacy power management functionalities are also integrated. The SiS961 also incorporates an universal interface supporting the asynchronous inputs/outputs of the X86 compatible microprocessors like PIII, K7 and P4.

The Integrated Audio Controller features a 6 channels of AC 97 v2.2 compliance audio to present 5.1-channel Dolby digital material or to generate stereo audio with simultaneous V.90 HSP modem operation. Besides, 4 separate SDATAIN pins are provided to support multiple audio Codecs + one modem Codecmaximally, effectuating the realization of 5.1 channel Dolby digital material in theater quality sound. Both traditional consumer digital audio channel as well as the AC 97 v2.2 compliant consumer digital audio slot are supported. VRA mode is also associated with both the AC 97 audio link and the traditional consumer digital audio channel.

The integrated Fast Ethernet MAC features an IEEE 802.3 and IEEE 802.3x compliant MAC supportingfull duplex 10 Base-T, 100 Base-T Ethernet, or 1Mb/s & 10Mb/s Home networking. 5 wake-up Frames, Magic Packet and link status change wake-up functions in G1/G2 states are supported. Besides, the integrated MAC provides a scheme to store the MAC address without the need of an external EEPROM. The 25 MHz oscillating circuit is integrated so as only an external low cost 25 MHz crystal is needed for the clocking system.

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85758575A N/B MaintenanceA N/B MaintenanceThe integrated Universal Serial Bus Host Controllers features Dual Independent OHCI Compliant Host controllers with six USB ports delivering 2 x 12 Mb/s bandwidth and rich connectivity. Besides, each port can be optionally configured as the wake-up source. Legacy USB devices as well as over current detection are also implemented. The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode 0,1,2,3,4, and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that sustain the high data transfer rate in the multitasking environment. The MuTIOL® Connect to PCI bridge supporting 6 PCI master is compliant to PCI 2.2 specification. The SiS961 also incorporates the legacy system I/O like: two 8237A compatible DMA controllers, three 8254 compatible programmable 16-bit counters, hardwired keyboard controller and PS2 mouse interface, Real Time clock with 256B CMOS SRAM and two 8259A compatible Interrupt controllers. Besides, the I/O APIC managing up to 24 interrupts with both Serial and FSB interrupt delivery modes is supported.

The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2 compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for specific application. In addition, the SiS961 supports Intel Speed Step technology and Deeper Sleep power state for Intel Mobile processor. For AMD processor, the SiS961 use the CPUSTP# signal to reduce processor voltage during C3 and S1 state.

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SiS301LV, which is an accompany chip of SiS VGA chip, integrates :A NTSC/PAL video encoder with Macrovision Ver.7.1.L1 option for TV display.A LVDS transmitter with bi-linear scaling capability for TFT LCD panel display.

All the above functions can support dual-display features. It means that the second display device driven by SiS301LV can display independent resolutions, color depths and frame rates different from the traditional CRT monitor driven by primary VGA chip. SiS301LV receives digital video signals and control signals from the primary VGA chip then transforms them into composite, S-Video or component video output for TV display, LVDS signals for LCD display. The output display combination can be one of the three :(1) Primary CRT+SiS301LV TV(2) Primary CRT+SiS301LV LCD(3) SiS301LV TV + SiS301LV LCD.

The package type of SiS301LV is 128-pin LQFP.

1.2.4 SiS301LV TV Encoder / LVDS Transmitter

General Description

Prim aryVG A

(SiS650/SiS330)

V ideoDecoder

SiS301LV

C R TMonitor

LC DMonitor

NTSC/PALTV

Fram eBuffer Feature

C onnector

1st channel

2nd channel

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Supports PAL and NTSC Systems.

Supports Composite, S-Video, and Component RGB( SCART) Output Signals

Supports Macrovision Copy Protection Process Rev. 7.1.L1

Support Progressive TV 525P YPbPr Output Signals.

Support Macrovision Conpy Protection Waveforms for 525p Progressive Scan Output

Supports TV/Primary VGA Independent Display Resolution and Frame Rate at Enhanced Mode

Provides Adaptive 6-Line Anti-Flicker Filtering.

Provides Hardware Interpolation for Programmable Under-Scan/Over-Scan Adjustment.

Provides Programmable Display Position Adjustment.

Provides Programmable Notch Filter for Cross Color Elimination.

Provides Chrominance Filter for Cross Luminance Elimination.

Provides Color Saturation Adjustment for Vivid TV Output.

Provides Gamma Correction Independent of That of Primary VGA.

Auto-Sense of TV Connection

1.2.4.1 TV-Out :

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85758575A N/B MaintenanceA N/B Maintenance1.2.4.2 LVDS

Supports LVDS Transmitter Function.

Single LVDS supports pixel rate up to 110M pixel/sec.

Compatible with TIA/EIA-644 LVDS standard.

Provides Bi-linear Scaling to Scale VGA Low Resolution Mode up for LCD Display – up to 1280x1024

Supports LCD/Primary VGA Independent Display Resolution and Frame Rate at Enhanced Mode.

Support 2D dither for 18-bit panels.

Provides Programmable Display Centering.

Compliant with VESA DDC2B

Compliant with VESA Plug & Display, Hot Plugging Function.

Provides Correction Independent of That of Primary VGA

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The TI PCI1410 is a high-performance PCI-to-PC Card controller that supports a single PC Card socket compliant with the 1997 PC Card Standard. The PCI1410 provides features that make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1410 supports both 16-bit andCardBus PC Cards, powered at 5 V or 3.3 V, as required. .

The PCI1410 is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bridging transactions. The PCI1410 is also compliant with the latest PCI Bus Power Management Interface Specification and PCI Bus Power Management Interface Specification for PCI toCardBus Bridges.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1410 is register compatible with the IntelE 82365SL-DF and 82365SL ExCA controllers. The PCI1410 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1410 can also be programmed to accept fast posted writes to improve system-bus utilization.

1.2.5 PC Card Interface Controller: TI PCI1410

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85758575A N/B MaintenanceA N/B MaintenanceMultiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PCI1410, such as socket activity light-emitting diode (LED) outputs, are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.

Features

Ability to wake from D3hot and D3cold

Fully compatible with the Intel 430TX (Mobile Triton II) chipset

A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGAE ball grid array (GGU) package, or209-terminal MicroStar BGAE (GHK) package3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards

Single PC Card or CardBus slot with hot insertion and removal

Burst transfers to maximize data throughput on the PCI bus and the CardBus bus

Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI interrupts, and serial ISA IRQ and PCI interrupts

26

85758575A N/B MaintenanceA N/B Maintenance1.2.5.1 Single-Slot PC Card Power Interface Switch: TPS2211A

The TPS2211A PC Card power-interface switch provides an integrated power-management solution for a single PC Card. All of the discrete power MOSFETs, a logic section, current limiting, and thermal protection for PC Card control are combined on a single integrated circuit, using the Texas Instruments LinBiCMOSTM

process. The circuit allows the distribution of 3.3-V, 5-V, and/or 12-V card power, and is compatible with many PCMCIA controllers. The current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card.

The TPS2211A features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V. Bias power can be derived from either the 3.3-V or 5-V inputs. This facilitates low-power system designs such as sleep mode and pager mode where only 3.3 V is available.

End equipment for the TPS2211A includes notebook computers, desktop computers, personal digital assistants (PDAs), digital cameras, and bar-code scanners.

27

85758575A N/B MaintenanceA N/B MaintenanceFeatures

Fully Integrated VCC and Vpp Switching for Single-Slot PC CardTM Interface

Low rDS(on) (70-m 5-V VCC Switch and 3.3-V VCC Switch)

Compatible With Industry-Standard Controllers

3.3-V Low-Voltage Mode

Meets PC Card Standards

12-V Supply Can Be Disabled Except During 12-V Flash Programming

Short-Circuit and Thermal Protection

Space-Saving 16-Pin SSOP (DB)

Compatible With 3.3-V, 5-V, and 12-V PC Cards

Break-Before-Make Switching

PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association)

LinBiCMO is a trademark of Texas Instruments

28


The µPD72872 is NEC’s 1-chip solution of an OHCI-LINK layer controller and a two port, physical layer implementation compliant to P1394a specification draft 2.0. It supports the connection with transmission speeds up to 400Mbps. The two-port shrink version of the µPD72870 chip with PCI/CardBus Interface offers a compact and low-cost solution for implementing applications in PC, PC-Cards as µPD72872 supports the 1394 Open Host Controller Interface 1.0

1.2.6 IEEE1394 : NEC µPD72872 OHCI-Link Layer Controller

Features

Link Layer compliant with 1394 Open Host Controller Interface specification release 1.0 Physical layercompliant with definition in P1394a draft 2.0 (Data Rate 100/200/400 Mbps)

Selectable active port number (1, 2 ports)

Modular 32-bit host interface compliant with PCI specification release 2.1

Supports PCI Bus Power Management Interface specification release 1.1

Modular 32-bit host interface compliant with CardBus specification

Cycle Master and Isochronous Resource Manager support

32-bit CRC generation and checking for receive/transmit packets

Supports 4 isochronous transmit DMAs and 4 isochronous receive DMAs

2-wire Serial EEPROM™ interface supported

29

85758575A N/B MaintenanceA N/B MaintenanceSeparate power supply Link and PHY

Programmable latency timer from serial EEPROM™ in CardBus mode (CARD_ON = 1)

Temperature range: 0 to 70°C

Operating voltage: 3.3 V ± 10%, single power supply

SiS961 is an AC’97 2.1 compliant controller that communicates with companion Codecs SiS a digital serial link called the AC-link.

The ALC201 is an AC97 2.2 compatible stereo audio codec designed for PC multimedia systems.The ALC201 provides the way for PC98 and PC99-compliant desktop, portable and entertainment PCs, where high-quality audio is required. The ALC201 AC’97 CODEC provides a complete high quality audio solution.

1.2.7 AC’97 Audio System: Advance Logic, Inc, ALC201

Single chip audio CODEC with high S/N ratio (>90 dB)

18-bit ADC and DAC resolution

Compliant with AC’97 2.2 specification

Meet performance requirements for audio on PC2001 systems

Features

30

85758575A N/B MaintenanceA N/B Maintenance18-bit stereo full-duplex CODEC with independent and variable sampling rate

4 analog line-level stereo input with 5-bit volume control: LINE_IN, CD, VIDEO, AUX

2 analog line-level mono input: PC_BEEP, PHONE_IN

Mono output with 5-bit volume control

Stereo output with 5-bit volume control

2 MIC inputs: Software selectable

Power management

3D Stereo Enhancement

Headphone output with 50mW/20ohm driving capability (ALC201)

Line output with 50mW/20ohm driving capability (ALC201A)

Headphone jack-detect function to mute LINE output

Multiple CODEC extension

MC’97 chained in allowed for multi-channel application

External Amplifier power down capability

Support S/PDIF out is fully compliant with AC’97 specification rev2.2

DC offset cancellation

Power support: Digital: 3.3V Analog: 5V

Standard 48-Pin LQFP Package

31


The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. The combination of PC-TEL’s well proven PCT2303W chipset and the HSP56TM MR software modem driver allows systems manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while maintaining higher system performance.

1.2.8 MDC: PCTel Modem Daughter Card PCT2303W

PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating with the Pentium class processors, HSP becomes part of the host computer’s system software. It requires less power to operate and less physical space than standard modem solutions. PC-TEL’s HSP modem is an easily integrated, cost-effective communications solution that is flexible enough to carry you into the future.

The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a programmable line interface to meet international telephone line requirements. The PCT2303W chip set is available in two 16-pin small outline packages (AC’97 interface on PCT303A and phone-line interface on PCT303W). The chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to 4-wire hybrid. The PCT2303W chip set dramatically reduces the number of discrete components and cost required to achieve compliance with international regulatory requirements. The PCT2303W complies with AC’97 Interface specification Rev. 2.1.

32

85758575A N/B MaintenanceA N/B MaintenanceThe chip set is fully programmable to meet worldwide telephone line interface requirements including those described by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable parameters of the PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer threshold. The PCT2303W chip set has been designed to meet stringent worldwide requirements for out-of-band energy, billing-tone immunity, lightning surges, and safety requirements.

Operating System Compatibility

Windows 98 /NT4.0 /Win 2K /Win XP

CompatibilityITU-T V.90 56000, 54667, 53333,52000, 50667, 49333, 48000,

46667, 45333, 42667, 41333, 40000, 38667, 37333,36000, 34667, 33333, 32000, 30667, 29333, 28000bps

K56Flex 56000, 54000, 52000, 50000, 48000, 46000, 44000,42000, 40000, 38000, 36000, 32000bps

ITU-T V.34Annex 33600,31200 bps

ITU-T V.34 28800 bpsITU-T V.32bis 14400 bpsITU-T V.32 9600,4800 bpsITU-T V.22bis 2400 bpsITU-T V.22 1200 bpsITU-T V.21 300 bpsITU-T V.23 1200/75 bps

33

85758575A N/B MaintenanceA N/B MaintenanceITU-T V.17 14400,12000,9600,7200 bpsITU-T V.29 9600,7200 bpsITU-T V.27ter 4800,2400 bpsBell 212A 1200 bpsBell 103 300 bps

Modulation

56000bps(V90&K56Flex) PCM 33600 bps (V.34Annex) TCM28800 bps (V.34) TCM14400 bps (V.32bis) TCM12000 bps (V.32bis) TCM9600 bps (V.32bis) TCM 7200 bps (V.32bis) QAM 9600 bps (V.32) TCM, QAM 4800 bps (V.32) QAM 14400 bps (V.17) TCM12000 bps (V.17) TCM9600 bps (V.29) QAM7200 bps (V.29) QAM4800 bps (V.27ter) DPSK

34

85758575A N/B MaintenanceA N/B Maintenance2400 bps (V.27ter) DPS2400 bps (V.22bis) QAM1200/75bps (V.23) FSK1200bps(V.22/Bell 212A) DPSK 300bps(V.21/Bell 103) FSK

Data Compression

V.42bis, MNP5

Error Correction

V.42 LAPM, MNP 2-4

DTE interface

Low Group Frequency (Hz) 697 770 852 941 High Group 1209 1 4 7 * Frequency 1336 2 5 8 0 (Hz) 1477 3 6 9 # 1633 A B C D

DTMF Tone Frequency

DTMF signal level

35

85758575A N/B MaintenanceA N/B Maintenance1.2.8.1 High Group -10+/-2dBm

1.2.8.2 Low Group -12+/-2dBm

Dialing Type Tone or pulse dialingTelephone Line interface RJ-11 Return Loss 300HZ - 3400HZ >= 10db Flow Control XOFF/XON or RTS/CTS Receive Level -35 +/- 2dBmTransmit Level >-15 dBm

Specification and features subject to change without notice!

36


1.2.9 Keyboard System: H8 (3437S) Universal Keyboard Controller

CPU Two-way general register configuration Eight 16-bit registers or sixteen 8-bit registers High-speed operationMaximum clock rate: 16Mhz at 5VAvailable in temperature range: 0°C~70°C

Memory Include 60KB ROM and 2KB RAM16-bit free-running timerOne 16-bit free-running counterTwo output-compare linesFour input capture lines

8-bit timer (2 channels) Each channel has one 8-bit up counter, two time constant registers

PWM timer (2 channels) Resolution: 1/250Duty cycle can be set from 0 to 100%

I2C bus interface (one channel) Include single master mode and slave mode

Host interface (HIF) 8-bit host interface port Three hosts interrupt requests (HIRQ1, 11,12)Regular and fast A20 gate output

Keyboard controller Controls a matrix-scan keyboard by providing a keyboardscan function with wake-up Interrupts and sense ports

A/D converter 10-bit resolution8 channels: single or scan mode (selectable)

37

85758575A N/B MaintenanceA N/B MaintenanceD/A converter 8-bit resolution

2 channels

Interrupts Nine external interrupt lines: NMI#, IRQ0 to 7#26 on-chip interrupt sources

Power-down modes Sleep modeSoftware standby mode

Hardware standby mode

A single chip microcomputerOn-chip flash memoryMaximum 64kbyte-address space

Support three PS/2 port for external keyboard, mouse and internal track pad.

Support SMI, SCI trigger input:Cover switchBattery charging controlSmart Battery monitoring Control D/D system on/offFan control and LED indicator serial interface100pin TQFP

38


1.2.10 System Flash Memory (BIOS)

2 M bit Flash memory Flashed by 5V onlyUser can upgrade the system BIOS in the future just running flash program

1.2.11 Memory System

JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB (64 Meg x 64 [HD])VDD= VDDQ= +2.5V ±0.2VVDDSPD = +2.2V to +5.5V2.5V I/O (SSTL_2 compatible)Commands entered on each positive CK edgeDQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bi-directional data strobe (DQS) transmitted/received with data—i.e.,source-synchronous data captureDifferential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.) Four internal device banks for concurrent operation

64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMMs

39

85758575A N/B MaintenanceA N/B MaintenanceSelectable burst lengths: 2, 4 or 8Auto precharge optionKBC and PS2 mouse can be individually disabledAuto Refresh and Self Refresh Modes15.6µs (MT4VDDT864H, MT8VDDT1664HD), 7.8125µs (MT4VDDT1664H, MT8VDDT3264HD, MT8VDDT6464HD) maximum average periodic refresh intervalSerial Presence Detect (SPD) with EEPROMSerial Presence Detect (SPD) with EEPROMFast data transfer rates PC2100 or PC1600Selectable READ CAS latency for maximum compatibilityGold-plated edge contacts

1.2.12 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHYceiver The ICS1893

The ICS1893 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TXCarrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893 architecture is based on the ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch applications.

General Description

40

85758575A N/B MaintenanceA N/B MaintenanceThe ICS1893 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893 can virtually eliminate errors from killer packets.

The ICS1893 provides a Serial Management Interface for exchanging command and status information with a Station Management (STA) entity.

The ICS1893 Media Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually (with input pins or control register settings) or automatically (using the Auto-Negotiation features). When the ICS1893 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common.

Features

Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz across a temperature range from -5 to +85 C

DSP-based baseline wander correction to virtually eliminate killer packets across temperature range from -5 to +85 C

Low-power, 0.35-micron CMOS (typically 400 mW)

Single 3.3-V power supply

41

85758575A N/B MaintenanceA N/B MaintenanceSingle-chip, fully integrated PHY provides PCS, PMA, PMD and AUTONEG sublayers of IEEE standard

10Base-T and 100Base-TX IEEE 802.3 compliant

Fully integrated, DSP-based PMD includes:

Adaptive equalization and baseline wander correction Transmit wave shaping and stream cipher scrambler MLT-3 encoder and NRZ/NRZI encoder

Highly configurable design supports:Node, repeater, and switch applications Managed and unmanaged applications 10M or 100M half- and full-duplex modes Parallel detection Auto-negotiation, with Next Page capabilities

MAC/Repeater Interface can be configured as: 10M or 100M Media Independent Interface 100M Symbol Interface (bypasses the PCS) 10M 7-wire Serial Interface

Small Footprint 64-pin Thin Quad Flat Pack (TQFP)

42


1.3 Other Functions

1.3.1 Hot Key Functions

Keys Combination

Feature Meaning

Fn + F1 Reserve Fn + F2 Reserve Fn + F3 Volume Down Fn + F4 Volume Up Fn + F5 LCD/external CRT

switching Rotate display mode in LCD only, CRT only, and simultaneously display.

Fn + F6 Brightness down Decreases the LCD brightness Fn + F7 Brightness up Increases the LCD brightness Fn + F8 Brightness MAX Toggle Max Brightness Fn + F9 Pause Fn + F10 Break Fn + F11 Panel Off/On Toggle Panel on/off Fn + F12 Suspend to DRAM / HDD Force the computer into either Suspend to HDD or Suspend to DRAM mode

depending on BIOS Setup.

1.3.2 Power on/off/suspend/resume button APM mode

At APM mode, Power button is on/off system power.

43

85758575A N/B MaintenanceA N/B MaintenanceAPM mode

At ACPI mode. Windows power management control panel set power button behavior.You could set “standby”, “power off” or “hibernate”(must enable hibernate function in power Management) to power button function.Continue pushing power button over 4 seconds will force system off at ACPI mode.

1. None2. Standby3. Off4. Hibernate (must enable hibernate function in power management)

System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong the usage time when user closes the notebook cover.At ACPI mode there are four functions to be chosen at windows power management control panel.

1.3.3 Cover Switch

1.3.4 Reset Switch

There is a reset switch at bottom side of notebook. It will reset embedded controller H8 and turn off system totally. When system hands up and Power button has no function, this switch is the only way to turn off system without remove power source.

44


System has eight status LED indicators to display system activity, which include three at front side and five above keyboard.

1.3.5 LED Indicators

1) Three LED indicators at front side:From left to right that indicates: AC Power, Battery Power and Battery Status

AC Power: This LED lights green when AC is powering the notebook, and flash (on 1 second, off 1second) when Suspend to DRAM is active using AC power. The LED is off when the notebook is off or powered by batteries.

Battery Power: This LED lights green when the notebook is being powered by Battery, and flash (on 1 second, off 1 second) when Suspend to DRAM is active using Battery power. The LED is off when the notebook is off or powered by batteries, or when Suspend to Disk.

Battery Status: During normal operation, this LED stays off as long as the battery is charged. When the battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is being charged.

2) Five LED indicators above keyboard:From left to right that indicates LAN, CD-ROM/HARD DISK DRIVE, NUM LOCK, CAPS LOCK andSCROLL LOCK.

45


1.3.6 Battery Status

Battery Warning

System also provides Battery capacity monitoring and gives user a warning so that users have chance to save his data before battery dead. Also, this function protects system from mal-function while battery capacity is low.

Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds. System will suspend to HDD after 2 Minutes to protect users data.

Battery Low State

After Battery Warning State, and battery capacity is below 4%, system will generate beep for twice per second.

Battery Dead State

When the battery voltage level reaches 7.4 volts, system will shut down automatically in order to extend the battery packs' life.

1.3.7 Fan power on/off management

FAN is controlled by H8 embedded controller-using AD2201 to sense CPU temperature and PWM control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster Fan Speed.

46


1.3.8 CMOS Battery

CR2032 3V 220mAh lithium batteryWhen AC in or system main battery inside, CMOS battery will consume no power.AC or main battery not exists, CMOS battery life at less (220mAh/5.8uA) 4 years.Battery was put in battery holder, can be replaced.

1.3.9 I/O Port

One Power Supply Jack.One External CRT Connector For CRT DisplaySupports two USB port for all USB devices.One MODEM RJ-11 phone jack for PSTN line One RJ-45 for LAN.Headphone Out Jack. Microphone Input Jack.Line in JackOne Card Bus Sockets for one type II PC card extension

1.3.10 Battery current limit and learning

Implanted H/W current limit and battery learning circuit to enhance protection of battery.

47


1.4 Peripheral Components

1.4.1 LCD Panel

1.4.2 Ext.Floppy Disk DriveMitsumi D353GUExternal USB 3.5” 1.44MB /1.2 MB/720KB FDD (Option)

1.4.3 HDDHitachi 30GBHeight: 9.5 mm, 2.5”

1.4.4 24X CD-ROM DriveTEAC

LCD 14.1 Hyundai HT14X12-100A

48


1.4.5 8W/4R CD-RW

1.4.6 KeyboardWindows 98 Keyboard, 1 color, multi languages support JP, US and Europe Keyboard with “ Volume UP ”and “ Volume Down ” word.

1.4.7 Track Pad SynapticsAccurate positioningLow fatigue pointing actionLow profileNo moving part, high reliabilityLow power consumptionEnvironmentally sealedCompact size.Software configurableLow weightOperating temperature: 0 to 60 degree C

KEMHeight: 12.7 mm IDE I/F

49

85758575A N/B MaintenanceA N/B MaintenanceOperating humidity: 5%-95% relative humidity, non condensingStorage temperature: -40 to +65 degree CESD: 15KV applied to front surface SEE ESD Testing specification PN 520-000270-01Power supply voltage: 5.0Voltage ± 10%Power supply current: 4.0mA max operating

1.4.8 FanHY45J05-001

1.4.9 MemoryDDR-RAM/ATP//128M/256MDDR-RAM/Apacer//128M/256MDDR-RAM/Unidorsa//128M/256M

1.4.10 Modem MDCAskey

50


The 8575A system has built in several power saving modes to prolong the battery usage for mobile purpose. User can enable and configure different degrees of power management modes via ROM CMOS setup (booting by pressing F2 key). Following are the descriptions of the power management modes supported.

1.5 System Management

In this mode, each device is running with the maximal speed. CPU clock is up to its maximum.

1.5.1 System Management Mode

Full on mode

In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This can save battery power without loosing much computing capability. The CPU power consumption and temperature is lower in this mode.

Doze Mode

For more power saving, it turns of the peripheral components. In this mode, the following is the status of each device:

Standby mode

CPU: Stop grantLCD: backlight offHDD: spin down

51


The most chipset of the system is entering power down mode for more power saving. In this mode, the following is the status of each device:

Suspend to DRAM

Suspend to DRAM:CPU: off Twister K: Partial off VGA: Suspend PCMCIA: Suspend Audio: off SDRAM: self refresh

Suspend to HDD: All devices are stopped clock and power-downSystem status is saved in HDD All system status will be restored when powered on again

System has the ability to monitor video and hard disk activity. User can enable monitoring function for video and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU state depending on the application. When the VGA activity monitoring is enabled, the performance of the system will have some impact.

1.5.2 Other Power Management Functions

HDD & Video access

52


1.6 Appendix 1: SiS961 GPIO Definitions

Signal Name

MUX Function Mitac Definition

Buffer Type

Power Plane Tolerant

During PCISRT#

After PCISRT# S1 S3

S4/S5

GPIO0 MB_ID0 I/O Main Driven Defined Driven Defined Driven Defined Off Off

GPIO1 LDRQ1# CD_IN# I/O Main Driven Defined Driven Defined Driven Defined Off Off

GPIO2 THERM# SB_THRM# I/O Main Driven Defined Driven Defined Driven Defined Off Off

GPIO3 EXTSMI# EXTSMI# I/O Main Driven Defined Driven Defined Driven Defined Off Off

GPIO4 CLKRUN# CLKRUN# I/O Main Driven Defined Driven Defined Driven Defined Off Off

GPIO5 PREQ5# LCD_ID0 I/O Main Driven Defined Driven Defined Driven Defined Off Off

GPIO6 PGNT5# LCD_ID1 I/O Main Driven Defined Driven Defined Driven Defined Off Off

GPIO7 LCD_ID2 I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined

GPIO8 RING# WAKEUP# I/O AUX High-Z High-Z High-Z High-Z High-Z

GPIO9 AC_SDIN2 SCI# I/O AUX High-Z High-Z High-Z High-Z High-Z

GPIO10 AC_SDIN3 CRT_IN# I/O AUX High-Z High-Z High-Z High-Z High-Z

GPIO11 SPK_OFF I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined

GPIO12 CPUSTP# CPU_STP# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined

GPIO13 DPRSLPVR MPCIACT# /DPRSLPVR I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined

GPIO14 CD_PWRON# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined

GPIO15 VR_HILO# VR_HILO# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined

GPIO16 LO_HI# LO_HI# OD AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined

GPIO17 VGATEM# VGATEM# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined

GPIO18 PMCLK CD_RST O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined

GPIO19 SMBCLK SMBCLK O AUX High-Z High-Z High-Z High-Z High-Z

GPIO20 SMBDATA SMBDATA O AUX High-Z High-Z High-Z High-Z High-Z

SB_SiS961 GPIO

53


1.7 Appendix 2: H8 Pins Definitions

Invert from SUSA# to wake up H8 when system resumed by MDC modem and internal LAN.Inform system power management status

System to S4 soft off

System resume from S4 soft off through RTC Alarm

Battery low detect

Ring detect

AC adaptor in detect

Crystal input

H8 chip reset

Power button

H8 Hardware Standby input pull high

HH mode3 single chip mode

Function

H

H

L

H

H

H/L

H

H

H

H

H

H

H

STANDBY

I

I

I

I

I

I

I

I

O

I

I

I

I

I

I

I

L

H

HLH

H

H

H

I

I

I

I

I

I

I

I

O

I

I

I

I

I

I

I

ON

H

L

L

H

H

H

H/L

H

LH

H

H

H

H

I

I

I

I

I

I

I

I

O

I

I

I

I

I

I

I

AfterRESET/OFF

I↑

I↑

I↑

I↑

I↑

I↑

I↑

I↑

O

I

I

I

I↑

I↑

I↑

I↑

DuringRESET

H8_SUSB

BAT_CLK

H8 SUSC#

H8 SUSC

BATT DEAD#

RI#

H8 ADEN#

LID#

RESET OUT

Crystal

Crystal

RESET#

POWER BTN#

STBY#

H8_MODE1

H8_MODE0

H8 Pin Definitions

10

11

20

21

30

31

47

48

100

3

2

1

7

8

5

6

Pin

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Port A COMOS input level (input high min=3.5V, input low max=1.0V)

RESET OUT#

EXTAL

XTAL

RESET#

NMI#

STBY#

MD1

MD0

Name

The shadowed block is the selected function

54


LH

LH

LH

LH

LH

LH

LH

Battery charge control

Wake up SB at ACPI mode 5→3V

Keep OOOTVADJ257PB7

Lithium ion battery charging CV mode voltage level adjust

Keep OOOTVADJ158PB6

Power button trigger VIA8231 on/off Duplicate Power BTN# 5→3V

Keep HOIHLLOT H8 SB PWRBTN#91PB0

Key matrix scan output 7








Reset CPU

H8 VDD5 power source switch

Battery charge control

Power button trigger VIA8231 on 5→3V

Function

Keep L

Keep L

Keep L

Keep L

Keep L

Keep L

Keep L

Keep L

Keep

Keep

Keep H

Keep H

Keep

Keep H

Keep H

STANDBY

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

LH

LH

H

O

O

O

O

O

O

O

O

O

O

O

O

O

O

ON

L

L

L

L

L

L

L

L

L

LLH

H

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

AfterRESET/OFF

L

L

L

L

L

L

L

L

T

T

T

T↓

T

T

T

DuringRESET

KB OUT7

KB OUT6

KB OUT5

KB OUT4

KB OUT3

KB OUT2

KB OUT1

KB OUT0

SMbus SW

CHARGING2

H8 RCIN#

VDD5 SW

CHARGING1

Force Discharge

H8 WAKE#

H8 Pin Definitions

72

73

74

75

76

77

78

79

57

58

68

69

80

81

10

Pin

P17/A7

P16/A6

P15/A5

P14/A4

P13/A3

P12/A2

P11/A1

P10/A0

Port 1 TTL input voltage (input high min=2V, input low max=0.8V)

PB7

PB6

PB5

PB4

PB3

PB2

PB1

Port B TTL input voltage (input high min=2V, input low max=0.8V)

Name

PCI reset gate

55


LH Key matrix scan output 15

LH

LH

LH

LH

LH

ISA DATA bit 0



KeepI/OI/OI/OTISA SD082P30/HDB0/D0


Key matrix scan output 8Keep LOOLOLKB OUT867P20/A8

ISA DATA bit 7

ISA DATA bit 6

ISA DATA bit 5

ISA DATA bit 4

ISA DATA bit 3

ISA DATA bit 2

ISA DATA bit 1





Function

Keep

Keep

Keep

Keep

Keep

Keep

Keep

Keep L

Keep L

Keep L

Keep L

Keep L

Keep L

Keep L

STANDBY

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

O

O

O

O

LH

LH

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

O

O

O

O

ON

0

0

0

0

0

L

L

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

O

O

O

O

AfterRESET/OFF

T

T

T

T

T

T

T

L

L

L

L

L

L

L

DuringRESET

ISA SD7

ISA SD6

ISA SD5

ISA SD4

ISA SD3

ISA SD2

ISA SD1

KB OUT15

KB OUT14

KB OUT13

KB OUT12

KB OUT11

KB OUT10

KB OUT9

H8 Pin Definitions

89

88

87

86

85

84

83

60

61

62

63

64

65

66

Pin

P37/HDB7/D7

P36/HDB6/D6

P35/HDB5/D5

P34/HDB4/D4

P33/HDB3/D3

P32/HDB2/D2

P31/HDB1/D1

P27/A15

P26/A14

P25/A13

P24/A12

P23/A11

P22/A10

P21/A9


Name

Continue to previous

56


Fan power PWM controlKeepOO1OTFAN ON#156P47/PWM1

Fan power PWM control

H

LH

LED indicator shift data

Hot key and battery dead beep sound

Thermal throttling control to Southbridge

KeepOOOTLED DATA14P50/TXD0


System power on, need pull down to define initial state during reset

KeepOOLOT↓H8 PWR ON49P40/TMCI0

LED indicator shift clock

External SMI# 5→3V

PS2 mouse IRQ12

Keyboard IRQ1

Need invert to SCI# sending to SB5→3V/ Fan speed tachometer

SCI output and Fan Speed Tachometer Switch

Function

Keep

Keep

Keep

Keep

Keep

Keep

Keep

Keep

Keep H

STANDBY

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

ON

1

0

0

H

L

O

O

O

O

O

O

O

O

O

AfterRESET/OFF

T

T

T

T

T

T

T

T

T

DuringRESET

LED CLK

H8 SMI#

FAN ON#0

Beep sound

ISA IRQ12

ISA IRQ1

H8 SCI/FAN SPEED

SCI#/FAN SPD SW

H8 THRM#

H8 Pin Definitions

12

13

55

55

54

53

52

51

50

Pin

P52/SCK0

P51/RXD0

P46/PWM0

P46/PWM0

P45/TMRI1/HIRQ1

P44/TMCO1/HIRQ1

P43/TMCI1/HIRQ1

P42/TMRI0

P41/TMO0


Name


57


Charging current adjustTOOOTCharge-I_CTR44P76/AN6/DA0

Backlight inverter brightness adjustTOOOTBL ADJ45P77/AN7/DA1

TIIITVCC CORE43P75/AN5

Battery thermister temperatureTIIITBAT TEMP243P75/AN5

Battery thermister temperatureTIIITBAT TEMP142P74/AN4

To differential 3S3P lithium ion battery and 9S NiMH battery

KeepIIITLI/NIMH#41P73/AN3

TIIIT2.5V41P73/AN3

Monitor system on/off stateTIIIT3V/PWR ok40P72/AN2

Key matrix input 7 need pull high

Battery voltage measure



TIIITBAT VOLT138P70/AN0


Key matrix input 0 need pull highKeepIIIT↑KEY IN026P60/KEYIN0/FTCI

Battery voltage measure





Function

T

T

Keep

Keep

Keep

Keep

Keep

Keep

Keep H

STANDBY

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

ON

I

I

I

I

I

I

I

I

I

AfterRESET/OFF

T

T

T↑

T↑

T↑

T↑

T↑

T↑

T↑

DuringRESET

I_LIMIT

BAT VOLT2

KEY IN7

KEY IN6

KEY IN5

KEY IN4

KEY IN3

KEY IN2

KEY IN1

H8 Pin Definitions

39

39

35

34

33

32

29

28

27

Pin

P71/AN1

P71/AN1

P67/KEYIN7/IRQ7

P66/KEYIN6/IRQ6

P65/KEYIN5/FTID

P64/KEYIN4/FTIC

P63/KEYIN3/FTIB

P62/KEYIN2/FTIA

P61/KEYIN1/FTOA

Port 6 Schmitt trigger input voltage (min=1.0V max=3.5V)

Name


58


SM BUS clock need pull high 5→3VKeepI/OI/OI/OT↑BAT DATA16P97/WAIT/SDA

Read H8 send A20gate statusTIIIT↑ENABKL17P96/0

need pull highKeepI/OI/OI/OT↑H8/T DATA18P95/AS

need pull highKeepI/OI/OI/OT↑M DATA19P94/WR

need pull highKeepI/OI/OI/OT↑K/M DATA22P93/RD

need pull high

SM BUS clock need pull high 5→3V

CPU A20gate

KeepI/OI/OI/OT↑K/M CLK25P90/IRQ2/ESC2


KeepIIITISA SA293P80/HA0

need pull high

need pull high

IO port 62/66 chip select

ISA I/O write

ISA I/O read#

IO port 60/64 chip select

Function

Keep

Keep

Keep

Keep

Keep

Keep

Keep

Keep H

STANDBY

I/O

I/O

I/O

I

I

I

I

O

I/O

I/O

I/O

I

I

I

I

O

ON

I/O

I/O

I/O

I

I

I

I

O

AfterRESET/OFF

T↑

T↑

T↑

T

T

T

T

T

DuringRESET

H8/T CLK

M CLK

BAT CLK

H8 MCCS#

ISA IOW#

ISA IOR#

H8 KBCS#

X(H8 A20GATE)

H8 Pin Definitions

23

24

99

98

97

96

95

94

Pin

P92/IRQ0

P91/IRQ1/EIOW

P86/IRQ5/SCK1

P85/IRQ4/RXD1

P84/IRQ2/TXD1

P83/IOR

P82/CS1

P81/GA20


Name

↑ Pull High↓ Pull Low5→3V Level shift


59


� Stereo Speaker SetDevice Indicators�

2. System View and Disassembly

2.1 System View

2.1.1 Front View

Mini IEEE1394 Connector�

2.1.2 Left-side View

� Kensington LockVentilation Openings�

RJ-45 ConnectorPC Card Slot

�

�

� Hard Disk Drive

External Microphone JackLine Out Phone JackVolume ControlTop Cover Latch

�

�

�

�

� �

�

��

� � � � �

60


2.1.3 Right-side View

� Battery PackCD-ROM/DVD-ROM Drive�

2.1.4 Rear View

� Power ConnectorS-Video Output Connector�

USB PortsParallel Port

�

�

� D/D FanRJ-11 ConnectorVGA PortVentilation Openings

�

�

�

��

��

61


2.1.5 Top-open View

� LCD ScreenMicrophone�

KeyboardTouch Pad

�

�

Power ButtonEasy Start ButtonsBattery Charge IndicatorBattery Power IndicatorAC Power Indicator

�

�

�

�

�

�

�

�

�

�

�

�

62


2.2 System Disassembly The section discusses at length each major component for disassembly/reassembly and show correspondingillustrations. Use the chart below to determine the disassembly sequence for removing components from the notebook.

NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure thenotebook is not turned on or connected to AC power.

Modular Components

LCD Assembly Components

Base Unit Components

NOTEBOOK

2.2.1 Battery Pack

2.2.2 Keyboard

2.2.3 CPU

2.2.4 HDD Module

2.2.5 CD-ROM Drive

2.2.6 SO-DIMM

2.2.7 LCD Assembly

2.2.8 LCD Panel

2.2.9 Inverter Board

2.2.10 System Board

2.2.11 Touch-pad

2.2.12 Modem Card

63


1. Push the battery pack into the compartment. The battery pack should be correctly connected when youhear a clicking sound.

2. Slide the release lever to the “lock” ( ) position.

2.2.1 Battery Pack

Disassembly

1. Carefully put the notebook upside down.2. Slide the release lever to the “unlock” ( ) position (�), then sliding and holding the release lever

outwards while pull the battery pack out of the compartment (�). (Figure 2-1)

Figure 2-1 Remove the battery pack

Reassembly

��

�

64


2.2.2 Keyboard

Disassembly

1. Open the top cover.2. Insert a small rod, such as a straightened paper clip, into the eject hole near the power connector of the

notebook. (Figure 2-2) 3. Push the rod firmly and slide the easy start buttons cover to the left (�). Then lift the easy start buttons cover up

from the left side (�). (Figure 2-3)

Figure 2-2 Insert a rod easy to remove Figure 2-3 Remove easy start buttons cover

�

�

65


Reassembly

1. Reconnect the keyboard cable and fit the keyboard back into place with three screws. 2. Replace the easy start buttons cover.

3. Remove three screws fastening keyboard on the base unit cover. (Figure 2-4) 4. Slightly lift up the keyboard and disconnect the cable from the system board to detach the keyboard.

(Figure 2-5)

Figure 2-4 Remove three screws Figure 2-5 Remove keyboard

66


2.2.3 CPU

Disassembly

Figure 2-6 Remove the cover and rail Figure 2-7 Remove the heatsink

1. Remove the easy start buttons cover and keyboard to access the CPU compartment. (See section 2.2.2 Disassembly)2. Remove seven screws fastening the heatsink cover and the rail. (Figure 2-6)3. Remove three screws fastening the heatsink. (Figure 2-7)

67


Figure 2-8 Remove the fan’s power cord

Reassembly

1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPUpins into the holes. Tighten the screw by a flat screwdriver to locking the CPU.

2. Connect the fan’s power cord to the system board, fit the heatsink onto the top of the CPU and secure with four screws.

3. Replace the keyboard .Then replace easy start buttons cover.

4. Disconnect the fan’s power cord from the system board, then lift up the heatsink. (Figure 2-8) 5. Loosen the screw by a flat screwdriver,upraise the CPU socket to unlock the CPU. (Figure 2-9)

Figure 2-9 Remove the CPU

68


2.2.4 HDD Module

Disassembly

Figure 2-10 Remove HDD module

1. Carefully put the notebook upside down.2. Remove one screw and slide the HDD module out of the compartment. (Figure 2-10)3. Remove six screws to separate the hard disk drive from the metal shield. (Figure 2-11)

Figure 2-11 Disassemble the hard disk

Reassembly

1. To install the hard disk drive, place it in the bracket and secure with six screws.2. Slide the HDD module into the compartment and secure with one screw.

69


2.2.5 CD-ROM Drive

Disassembly

Figure 2-12 Remove one screw to loose the CD/DVD-ROM drive

Disassembly1. Carefully put the notebook upside down. 2. Remove one screw fastening the CD/DVD-ROM drive. Then hold the CD/DVD-ROM drive and slide it

outwards carefully. (Figure 2-12)

Reassembly

1. Push the CD/DVD-ROM drive into the compartment.2. Secure the CD/DVD-ROM drive with one screw.

70


2.2.6 SO-DIMM

Disassembly

Figure 2-14 Remove the SO-DIMMFigure 2-13 Remove the SO-DIMM cover

1. Carefully put the notebook upside down.2. Remove seven screws to access the SO-DIMM socket. (Figure 2-13)3. Full the retaining clips outwards (�) and remove the SO-DIMM (�). (Figure 2-14)

Reassembly

1. To install the SO-DIMM, match the SO-DIMM’s notched part with the socket’s projected part and firmlyinsert the OS-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the SO-DIMM into cover.

2. Replace the SO-DIMM cover. 3. Replace seven screws to fasten the SO-DIMM socket cover.

71


2.2.7 LCD

Disassembly

Figure 2-16 Remove the LCD hinge coverand button board

1.Carefully put the notebook upside down and remove seven screws to access the SO-DIMM socket. 2.Remove the tape from the antenna on the Mini-PCI socket.(Figure 2-15)

3. Open the top cover. Remove easy start buttons cover, keyboard, and heatsink . (See section 2.2.2 and 2.2.3 Disassembly)4. Pull out the antenna from the CPU compartment.5. Remove the two hinge covers and remove two screws fastening the easy start button board.(Figure 2-16)

Figure 2-15 Remove the tape fromthe antenna

72

85758575A N/B MaintenanceA N/B Maintenance6. Disconnect the LCD cables from the system board, and remove four screws of the hinges. Now you can

separate the LCD assembly from the base unit. (Figure 2-17)

Figure 2-17 Remove cables and screwsto separate LCD

1. Attach the LCD assembly to the base unit and secure with four screws on the hinges. 2. Replace the antenna to the SO-DIMM socket.3. Reconnect the LCD cable connectors to the system board. 4. Fit the easy start button board and secure with tow screws. 5. Replace two hinge cover, the heatsink, keyboard and easy start buttons cover.

Reassembly

73


2.2.8 LCD Panel

Disassembly

1. Remove the LCD assembly. (See section 2.2.7 Disassembly) 2. Remove the four rubber pads and two screws on the lower part of the panel. (figure 2-18)3. Insert a flat screwdriver to the lower part of the frame and gently pry the frame out. Repeat the process

until the frame is completely separated from the housing. 4. Remove the two screws on two sides and two screws on the lower part of the LCD panel, and disconnect

the cable from the inverter board. (figure 2-19)

Figure 2-18 Remove LCD frame Figure 2-19 Remove LCD panel

74

85758575A N/B MaintenanceA N/B MaintenanceReassembly1. Fit the LCD panel back into place and secure with four screws, and reconnect the cable to the inverter board. 2. Fit the LCD frame back into the housing and replace the four screws and four rubber pads. 3. Replace the LCD assembly. (See section 2.2.7 Reassembly)

75


2.2.9 Inverter Board

Disassembly

1. Remove the LCD assembly and detach the LCD panel. (see instructions in previous two sections)2. To remove the inverter board on the bottom side of the LCD assembly, disconnect the cable and remove

one screw. (figure 2-20)

Reassembly1. Fit the inverter board back into place and secure with one screw. 2. Reconnect the cable. 3. Replace the LCD frame. (See section 2.2.8 Reassembly) 4. Replace the LCD assembly. (See section 2.2.7 Reassembly)

Figure 2-20 Remove the inverter board

76


2.2.10 System Board

Disassembly

1. Remove the battery pack, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly. (See section 2.2.1 to 2.2.5 and 2.2.7 Disassembly)

2. Remove sixteen screws on the bottom of the notebook. (Figure 2-21)3. Remove nine screws fastening the base unit cover. (figure 2-22)

Figure 2-21 Remove the bottom Figure 2-22 Remove nine screws

77


Figure 2-23 Remove the base unit cover Figure 2-24 Remove the metal shield

4. Lift up the base unit cover and disconnect the touch pad cord. (Figure 2-23)5. Remove the four screws fastening the base unit. (Figure 2-24)

78


Figure 2-25 Remove the screws anddisconnect the cable

6. Remove three screws fastening the connectors shield and disconnect the cables. (Figure 2-25)7. Carefully put the notebook upside down.8. Remove seven screws and four hex nuts fastening the system board and disconnect one cable . Now

you can remove the system board. (Figure 2-26)

Reassembly

1. Replace seven screws and four hex nuts fasten the system board. 2. Reconnect one cable of system board fan and one cable of little battery to system board. 3. Replace three screws fasten the the connectors shield .4. Reconnect two cables of speakers and one cable to system board. 5. Reconnect the touch pad cord. 6. Replace the base unit cover and secure with nine screws7. Carefully put the notebook upside down. Then replace the bottom frame and secure with sixteen screws.8. Replace the battery pack, LED panel, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly.

Figure 2-26 Remove the system board

79


2.2.11 Touch-pad

Disassembly

1. Remove the base unit cover. (See steps 1-6 in section 2.2.10 Disassembly.) 2. Remove the eight screws to lift up the touch pad holder and touch pad panel. (Figure 2-27)

Reassembly1. Replace the touch-pad holder and touch-pad panel, and secure with eight screws. 2. Assemble the base unit cover. (See section 2.2.10 Reassembly)

Figure 2-27 Remove the touch-pad

80


2.2.12 Modem Card

Disassembly

Figure 2-28 Remove the Modem card

1. Remove the battery pack, keyboard, CPU, HDD module, CD/DVD-ROM drive, and LCD assembly. (See section 2.2.1 to 2.2.5 and 2.2.7 Disassembly)

2. Disassemble the notebook to access the system board. (See section 2.2.10 Disassembly)3. Remove the two screws fastening the modem card,and then disconnect the cable from system board. (Figure 2-28)

Reassembly1. Reconnect the cable to the modem card and secure the modem card with two screws. 2. Assemble the notebook. (See section 2.2.10 Reassembly)

81


3. Definition & Location of Connectors / Switches

3.1 Mother Board – A-1

� J1 : Modem Connector (RJ11)

� J2 : External VGA Connector

� J3 : LCD Connector

� J4 : D/D Connector

� J5 : MDC Jump Wire Connector

� J6 : Easy Start Buttons Connector

� J7 : MISC Connector

� J8 : Fan Connector

� J9 : LAN Connector (RJ45)

� J11 : PC Card Socket

� J12 : Secondary IDE Connector

� J13 : Internal Keyboard Connector

� J14 : Battery Connector

To next page

J509J9

J19

J21

J14

J12

J4J7

J6J5

J13

J3

J2

J8

VR1

J24

J28

J27

J20

J25

J23

J1

J18

J11SW6

82



3.1 Mother Board – A-2

� J18 : MDC Connector

� J19 : Primary IDE Connector

� J20 : Touch-pad Connector

� J21 : Internal Micro Phone Jack

� J23 : L Speaker Connector

� J24 : Line Out Phone Jack

� J25 : R Speaker Connector

� J27 : IEEE1394 Port

� J28 : External Microphone Jack

� SW6 : CPU Model Select Switch

� VR1 : Volume ControlJ9

J19

J21

J14

J12

J4J7

J6J5

J13

J3

J2

J8

VR1

J24

J28

J27

J20

J25

J23

J1

J18

J11SW6

Continue to previous page

83



3.1 Mother Board – B

U3U5U6

?

J506 J505

J509ON 2

1

SW503

J503

J508

� J503 : Fan Connector

� J505 : 200-pin expansion DDR SDRAM Socket

� J506 : 200-pin expansion DDR SDRAM Socket

� J508 : CMOS Battery Connector

� J509 : Mini PCI Socket

� SW503 : Country Selection for Keyboard

84



3.2 DC Power Board - A

� J1 : TV Out Jack

� J2 : Power Jack (AC adapter)

� J3 : Parallel Port Connector

� J4 : USB Port Connector


� J6 : Inverter Board Connector



� PJ1 : D/D Connector

� PJ2 : MISC Connector

� SW1 : Cover Switch

J3 J1PJ2

PJ1

J6J5 J7 J4 J8 J2

SW1

85



3.3 ESB Board – A,B

� J501 : Easy Start Button Connector

� SW1 : Programmable Easy Start Button Switch





� SW6 : Programmable Easy Start Button Power Switch

SW6SW5SW4SW3SW2SW1

J501

A

B

86



3.4 Touch-pad – A,B

� J501 : Touch-pad Board to Touch-pad Connector

� J502 : Touch-pad Board to Main Board Connector

� SW1 : Scroll Up Button Switch

� SW2 : Left Button Switch

� SW3 : Right Button Switch

� SW4 : Scroll Down Button Switch

J501

J502SW2

SW4

SW1 SW3

JP1 JP3

3.5 Daughter Board -A

� JP1 : MDC Jump Wire Connector

� JP3 : MDC/LAN Transfer Board to M/B Connector

A B

87


4. Definition & Location of Major Components

4.1 Mother Board - A

� U1 : Intel Pentium 4 Processor mPGA478 Socket

� U3 : LF-H80P Isolation Transformers

� U4 : SiS650 IGUI Host/Memory Controller

� U5 : ISC1893Y LAN Controller

� U6 : PCI1410GGU PCMCIA Controller

� U9 : ICS93722 Clock Buffer

� U10 : Flash ROM (BIOS)

� U11 : SN74CBTD3384 Level Shift

� U14 : SiS961 MuTIOL Media I/O Controller

� U15 : ALC201 Audio CODEC

� U16 : TPA0202 Audio Amplifier

� U18 : uPD72872 IEEE1394 Controller

� PU10 : CM8500 1.25V Generator

J509

U1U4

U15

U14

U18

U9U3 U5

U11U16

PU10U10

U6

88


4. Definition & Location of Major Components

4.1 Mother Board - B

� U504 : SiS301LV/Chrontel CH7019

� U505 : TPS2211 PC Card Slot Power Switch

� U508 : ICS952001 Clock Generator

� U509 : H8/F3437 Micro Controller

� U511 : PC87393 Super I/O

� PU508 : LTC3716 CPU Power Generator

� PU510 : LTC3707 1.8V/2.5V Generator

� PU511 : TL594C PWM

U3U5U6

?

U504

U511

U509

U508

U505

PU511PU510

PU508

89


5. Pin Descriptions of Major Components

5.1 Intel Pentium 4 Processor mPGA478 SocketName Type Description

A[35:3]# Input/ Output

A[35:3]# (Address) define a 2 36 -byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Pentium 4 processor in the 478-pin package system bus. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# pins to determine power-on configuration.

A20M# Input If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.

ADS# Input/ Output

ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.

ADSTB[1:0]# Input/ Output

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.

Signals Associated Strobe REQ[4:0]#, A[16:3]# ADSTB0#

A[35:17]# ADSTB1#

Name Type Description AP[1:0]# Input/

OutputAP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins of all Pentium 4 processor in the 478-pin package system bus agents. The following table defines

Request Signals subphase 1 subphase 2 A[35:24]# AP0# AP1# A[23:3]# AP1# AP0#

REQ[4:0]# AP1# AP0#

BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the system bus frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V CROSS .

BINIT# Input/ Output

BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT# activation. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the system bus and attempt completion of their bus queue and IOQ entries. If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system.

BNR# Input/ Output

BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.

90



BPM[5:0]# Input/ Output

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins of all Pentium 4 processor in the 478-pin package system bus agents. BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. Please refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for more detailed information. These signals do not have on-die termination. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for termination requirements.

BPRI# Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of all processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#.

BR0# Input/ Output

BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this pin is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated.

BSEL[1:0]

Output The BCLK[1:0] frequency select signals BSEL[1:0] are used to select the processor input clock frequency. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The Pentium 4 processor in the 478-pin package operates currently at a 400 MHz system bus frequency (100 MHz BCLK[1:0] frequency).

COMP[1:0] Analog COMP[1:0] must be terminated on the system board using precision resistors. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for details on implementation.

Name Type Description D[63:0]# Input/

OutputD[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#. Quad-Pumped Signal Groups

Data Group DSTBN#/ DSTBP# DBI#

D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3

Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high.

DBI[3:0]# Input/ Output

DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DBI[3:0] Assignment To Data Bus

Bus Signal Data Bus Signals DBI3# D[63:48]# DBI2# D[47:32]# DBI1# D[31:16]# DBI0# D[15:0]#

DBR# Output DBR# is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.

91



DBSY#

Input/ Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. The data bus isreleased after DBSY# is deasserted. This signal must connect the appropriate pins on all processor system bus agents.

DEFER#

Input

DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of all processor system bus agents.

DP[3:0]#

Input/ Output

DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all Pentium 4 processor in the 478-pin package system bus gents.

DSTBN[3:0]#

Input/ Output

Data strobe used to latch in D[63:0]#.

Signals Associated Strobe D[15:0]#, DBI0# DSTBN0#

D[31:16]#, DBI1# DSTBN1# D[47:32]#, DBI2# DSTBN2# D[63:48]#, DBI3# DSTBN3#

DSTBP[3:0]# Input/ Output

Data strobe used to latch in D[63:0]#.

Signals Associated Strobe D[15:0]#, DBI0# DSTBP0#

D[31:16]#, DBI1# DSTBP1# D[47:32]#, DBI2# DSTBP2# D[63:48]#, DBI3# DSTBP3#

FERR#

Output

FERR# (Floating-point Error) is asserted when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MSDOS*-type floating-point error reporting.

GTLREF

Input GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCC. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for more information.

Name Type Description HIT# HITM#

Input/ Output Input/ Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.

IERR#

Output IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. This signals does not have on-die termination.

IGNNE#

Input IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error.IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.

INIT#

Input INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST).

ITPCLKOUT[1:0]

Output

The ITPCLKOUT[1:0] pins do not provide any output for the Pentium® 4 processor in the 478-pin package.

ITP_CLK[1:0]

Input ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals.

92



LINT[1:0]

Input

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration.

LOCK#

Input/ Output

LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock.

MCERR#

Input/ Output

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options:

Enabled or disabled. Asserted, if configured, for internal errors along with IERR#.Asserted, if configured, by the request initiator of a bus

transaction after it observes an error. Asserted by any bus agent when it observes an error in a bus

transaction. For more details regarding machine check architecture, please refer to the IA-32 Software Developer’s Manual, Volume 3: System Programming Guide.

PROCHOT#

Output

PROCHOT# will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. .

Name Type Description PWRGOOD

Input

PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.

RESET#

Input

Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. This signal does not have on-die termination and must be terminated on the system board.

RS[2:0]#

Input

RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents.

RSP#

Input

RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor system bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity.

93



REQ[4:0]#

Input/ Output

REQ[4:0]# (Request Command) must connect the appropriate pins of all processor system bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity checking of these signals.

SKTOCC#

Output

SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this pin to determine if the processor is present.

SLP#

Input

SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internalclock signals to the bus and processor core units. If the BCLK input is stopped while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state.

SMI#

Input

SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs.

STPCLK#

Input

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

TCK

Input

TCK (Test Clock) provides the clock input for the processor Test Bus (also knownas the Test Access Port).

Name Type Description TDI

Input

TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.

TDO

Output

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support.

TESTHI[12:8] TESTHI[5:0]

Input

TESTHI[12:8] and TESTHI[5:0] must be connected to a VCC power source through a resistor for proper processor operation.

THERMDA Other Thermal Diode Anode. THERMDC Other Thermal Diode Cathode. THERMTRIP#

Output

Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135°C.Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (VCC) must be removed following the assertion of THERMTRIP#. Once activated, THERMTRIP# remains latched until RESET# is asserted. While the assertion of the RESET# signal will de-assert THERMTRIP# , if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted after RESET# is de-asserted.

TMS

Input

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY#

Input

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents.

TRST#

Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. This can be done with a 680 . pull-down resistor.

VCCA

Input

VCCA provides isolated power for the internal processor core PLLs. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for complete implementation details.

94



VCCIOPLL

Input

VCCIOPLL provides isolated power for internal processor system bus PLLs. Follow he guidelines for VCCA, and refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for complete implementation details.

VCCSENSE

Output

VCCSENSE is an isolated low impedance connection to processor core power(VCC). It can be used to sense or measure power near the silicon with little noise.

VCCVID Input

There is no imput voltage requirement for VCCVID for designs intended tosupport only the Pentium 4 processor in the 478-pin package. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for more information.

VID[4:0]

Output

VID[4:0] (Voltage ID) pins can be used to support automatic selection of power supply voltages (Vcc). These pins are not signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts defines the voltage required by the processor. The VID pins are needed to cleanly support processor voltage specification variations. The power supply must supply the voltage that is requested by these pins, or disable itself.

VSSA Input VSSA is the isolated ground for internal PLLs. VSSSENSE

Output

VSSSENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise

TMS Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY#

Input

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents.

TRST#

Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. This can be done with a 680 . pull-down resistor.

VCCA

Input

VCCA provides isolated power for the internal processor core PLLs. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for complete implementation details.

95


Name Pin Attr Signal Description RS[2:0]#

O 1.2~1.85V – M

Response Status: RS[2:0]# are driven by the response agent to indicate the transaction response type. The following shows the response type.

RS[2:0] Response 000 Idle State 001 Retry 010 Defer 011 Reserved 100 Reserved 101 No data 110 Implicit Write-back 111 Normal Data

HTRDY#

O 1.2~1.85V – M

Target Ready: During write cycles, response agent will drive TRDY# to indicate it is ready to accept data.

DRDY#

I/O 1.2~1.85V – M

Data Ready: DRDY# is driven by the bus owner whenever the data is valid on the bus.

DBSY#

I/O 1.2~1.85V – M

Data Bus Busy: Whenever the data is not valid on the bus with DRDY# is deserted, DBSY# deasserted to hold the bus.

HD[63:0]#

I/O 1.2~1.85V – M

Data Bus Busy: Whenever the data is not valid on the bus with DRDY# is deserted, DBSY# deasserted to hold the bus.

DBI[3:0]#

I/O 1.2~1.85V – M

Dynamic Bus Inversion: An active DBI# will invert it’s corresponding data group signals. DBI0# is referenced by HD[15:0], DBI1# is referenced by HD[31:16] DBI2# is referenced by HD[47:32] DBI3# is referenced by HD[63:48]

HDSTBP[3:0]#

I/O 1.2~1.85V – M

Source synchronous data strobe used to latch data at falling edge HD[15:0], DBI0# are latched by HDSTBP0# HD[31:16], DBI1# are latched by HDSTBP1# HD[47:32], DBI2# are latched by HDSTBP2# HD[63:48], DBI3# are latched by HDSTBP3#

HDSTBN[3:0]#

I/O 1.2~1.85V– M

Source synchronous data strobe used to latch data at falling edge HD[15:0], DBI0# are latched by HDSTBN0# HD[31:16], DBI1# are latched by HDSTBN1# HD[47:32], DBI2# are latched by HDSTBN2# HD[63:48], DBI3# are latched by HDSTBN3#

HNCOMP

I M

GTL N-MOS Compensation Input

Host BUS Interface Name Pin Attr Signal Description

CPUCLK CPUCLK#

I 0.71V – M

Host differential clock input.

CPURST#

O 1.2~1.85V – M

Host Bus Reset: CPURST# is used to keep all the bus agents in the same initial state before valid cycles issued.

CPUPWRGD#

CPUPWRGD# is used to inform CPU that main power is stable

ADS#

I/O 1.2~1.85V – M

Address Strobe : Address Strobe is driven by CPU or SiS650 to indicate the start of a CPU bus cycle.

HADSTB[1:0]# 1.2~1.85V – M

Source synchronous address strobe used to latch HREQ[4:0]# & HA[31:3]# at both falling and rising edge. HREQ[4:0]# & HA[16:3]# are latched by HASTB0# HA[31:17] are latched by HASTB1#

HREQ[4:0]#

I/O 1.2~1.85V – M

Request Command: HREQ[4:0]# are used to define each transaction type during the clock when ADS# is asserted and the clock after ADS# is asserted.

HA[31:3]#

I/O 1.2~1.85V – M

Host Address Bus

BREQ0#

O 1.2~1.85V – M

Symmetric Agent Bus Request: BREQ0# is driven by the symmetric agent to request for the bus.

BPRI#

O 1.2~1.85V – M

Priority Agent Bus Request: BPRI# is driven by the priority agent that wants to request the bus. BPRI# has higher priority than BREQ0# to access a bus.

BNR#

I/O 1.2~1.85V – M

Block Next Request: This signal can be driven asserted by any bus agent to block further requests being pipelined.

HLOCK#

I 1.2~1.85V – M

Host Lock : CPU asserts HLOCK# to indicate the current bus cycle is locked.

HIT#

I/O 1.2~1.85V – M

Keeping a Non-Modified Cache Line

HITM#

I/O 1.2~1.85V – M

Hits a Modified Cache Line: Hit Modified indicates the snoop cycle hits a modified line in the L1/L2 cache of CPU.

DEFER#

O 1.2~1.85V – M

Defer Transaction Completion: r defer response to host bus.

O1.2~1.85V – M

5.2 SiS650 IGUI Host/Memory Controller

96


Host BUS Interface Continue Name Pin Attr Signal Description

HPCOMP

I M

GTL P-MOS Compensation Input

HVREF[4:0] HNCOMPVREF

I M

AGTL+ I/O reference voltage

DRAM Controller Name Pin Attr Signal Description

SDCLK

I 3.3V - M

SDRAM Clock Input

SDRCLKI

I 2.5V/3.3V - M

SDRAM Read Clock Input

FWDSDCLKO

O 2.5V/3.3V – M

SDRAM Forward Clock Output

MA[14:0]

O 2.5V/3.3V - M

System Memory Address Bus

SRAS#

O 2.5V/3.3V - M

SDRAM Row Address Strobe

SCAS#

O 2.5V/3.3V - M

SDRAM Column Address Strobe

SWE#

O 2.5V/3.3V - M

SDRAM Write Enable

CS[5:0]# CSB[5:0]#

O 2.5V/3.3V - M

SDRAM Chip Select CSB[5:0] multiplexed with DQS[5:0]

DQM[7:0]#

O 2.5V/3.3V - M

SDRAM Input/Output Data Mask

DQS[7:0]

I/O 2.5V/3.3V - M

DDR Data Strobe

MD[63:0]

I/O 2.5V/3.3V - M

System Memory Data Bus

CKE[5:0]

O (open-drain) 2.5V/3.3V – AUX

SDRAM Clock Enable

S3AUXSW# (CKE6)

O (open-drain) 2.5V/3.3V - AUX

Aux power switch for ACPI-S3 state, low active.

DDRVREF[A:B] I M

DDR I/O Reference Voltage

SiS MuTIOL Interface

AIRDY#

I/O 1.5V/3.3V - M

AGP Initiator Ready

ATRDY#

I/O 1.5V/3.3V - M

AGP Target Ready

ASTOP#

I/O 1.5V/3.3V - M

AGP Stop#

ADEVSEL#

I/O 1.5V/3.3V - M

AGP Device Select

ASERR#

I 1.5V/3.3V - M

AGP System Error

AREQ#

I 1.5V/3.3V - M

AGP Bus Request

AGNT#

O 1.5V/3.3V - M

AGP Bus Grant

AAD[31:0]

I/O 1.5V/3.3V - M

AGP Address/Data Bus

Name Pin Attr Signal Description ZCLK

I 3.3V - M

SiS MuTIOL Connect

ZUREQ/ZD REQ

I/O 1.8V - M

SiS MuTIOL Connect Control pins

ZSTB[1:0]

I/O 1.8V - M

SiS MuTIOL Connect Strobe

ZSTB[1:0]#

I/O 1.8V - M

Strobe Compliment

ZAD[15:0]

I/O 1.8V - M

I/O 1.8V - M

ZVREF

I M

SiS MuTIOL Connect Reference Voltage

ZCMP_N

I M

N-MOS Compensation Input

ZCMP_P

I M

P-MOS Compensation Input

AGPCLK

I 3.3V – M

AGP Clock

AFRAME#

I/O 1.5V/3.3V - M

AGP Frame#


97


SiS MuTIOL Interface Continue

Name Pin Attr Signal Description AC/BE[3:0]

I/O 1.5V/3.3V - M

AGP Command/Byte Enable

APAR

I/O 1.5V/3.3V - M

AGP Parity

ST[2:0]

O 1.5V/3.3V - M

AGP Status Bus

PIPE#

I 1.5V/3.3V - M

AGP Pipeline Request

SBA[7:0]

I/O 1.5V/3.3V - M

Side Band Address

RBF#

I 1.5V/3.3V - M

Read Buffer Full

WBF#

I 1.5V/3.3V - M

Write Buffer Full

AD_STB[1:0] I/O 1.5V/3.3V - M

AD Bus Strobe

AD_STB[1:0]#

I/O 1.5V/3.3V - M

AD Bus Strobe Compliment

SB_STB

I 1.5V/3.3V - M

Side Band Strobe

SB_STB#

I 1.5V/3.3V - M

Side Band Strobe Compliment

VB Interface

Name Pin Attr Signal Description VBCLK

I 1.8V/3.3V - M

Channel B/A Clock Input VBCLK multiplexed with SBA0

VBHCLK

O 1.8V/3.3V – M

VB Programming Interface Clock VBHCLK multiplexed with RBF#

VBCAD

I/O 1.8V/3.3V – M

VB Programming Interface Data VBCAD multiplexed with AREQ#

VBCTL[1:0]

O 1.8V/3.3V - M

VB Data Control VBCTL[1:0] multiplexed with AAD[29:28]

VGPIO[3:2]

I/O 3.3V - M

VB GPIO pins VGPIO[3:2] multiplexed with PIPE#/WBF#

VBHSYNC

I/O 1.8V/3.3V - M

Channel B H-Sync VBHSYNC multiplexed with AAD30

VBVSYNC

I/O 1.8V/3.3V - M

Channel B V-Sync VBVSYNC multiplexed with AAD31

VBDE

I/O 1.8V/3.3V - M

Channel B Data Valid VBDE multiplexed with AAD27

VBGCLK

I/O 1.8V/3.3V - M

Channel B Clock Output. This clock is used to trigger dual edge data transfer. Perfect duty cycle is required. VBGCLK multiplexed with AD_STB1

VBD[11:0]

I/O 1.8V/3.3V - M

Channel B Data VBD[11:0] multiplexed with AAD

VAHSYNC

I/O 1.8V/3.3V - M

Channel A H-Sync VAHSYNC multiplexed with AAD18

VAVSYNC

I/O 1.8V/3.3V - M

Channel A V-Sync VAVSYNC multiplexed with AAD17

VADE

I/O 1.8V/3.3V - M

Channel A Data Valid VADE multiplexed with AAD16

VAGCLK

I/O 1.8V/3.3V - M

Channel A Clock Output. This clock is used to trigger dual edge data transfer. Perfect duty cycle is required. VAGCLK multiplexed with AD_STB0

VAGCLK#

I/O 1.8V/3.3V - M

Channel A Differential Clock Output. (To support Chrontel). VAGCLK# multiplexed with AD_STB0#

VAD[11:0]

I/O 1.8V/3.3V - M

Channel A Data VAD[11:0] multiplexed with AAD

Stereo Glasses Interface Name Pin Attr Signal Description

CSYNC

O 3.3V - M

Stereo Clock

RSYNC

O 3.3V - M

Stereo Right

LSYNC

O 3.3V - M

Stereo Left


98


VGA Interface

Name Pin Attr Signal Description VOSCI

I 3.3V - M

14.318 Reference Clock Input

HSYNC

O 3.3V - M

Horizontal Sync

VSYNC

O 3.3V - M

Vertical Sync

INTA#

O 3.3V - M

Internal VGA Interrupt Pin

VGPIO[1:0]

I/O 3.3V - M

Internal VGA GPIO pins

VCOMP

AI Analog - M

Compensation Pin

VRSET

AI Analog - M

Reference Resistor

VVBWN

AI Analog - M

Voltage Reference

ROUT

AO Analog - M

Red Signal Output

GOUT

AO Analog - M

Green Signal Output

BOUT

AO Analog - M

Blue Signal Output

Power and Ground Signals

Name Tolerance Power Plane Type Attribute A1XAVDD 3.3V MAIN Analog

A1XAVSS 0V GROUND Analog

A4XAVDD 3.3V MAIN Analog

A4XAVSS 0V GROUND Analog

AGPVSSREF 0V GROUND Analog

AUX1.8 1.8V AUX Digital

AUX3.3 3.3V AUX Digital

C1XAVDD 3.3V MAIN Analog

C1XAVSS 0V GROUND Analog

Name Tolerance Power Plane Type Attribute C4XAVDD 3.3V MAIN Analog

C4XAVSS 0V GROUND Analog

DACAVDD1 1.8V MAIN Analog

DACAVDD2 1.8V MAIN Analog

DACAVSS1 0V GROUND Analog

DACAVSS2 0V GROUND Digital

DCLKAVDD 3.3V MAIN Digital

DCLKAVSS 0V GROUND Analog

DDRAVDD 3.3V MAIN Analog

DDRAVSS 0V GROUND Analog

ECLKAVDD 3.3 MAIN Analog

ECLKAVSS 0V GROUND Analog

IVDD 1.8V MAIN Digital

OVDD 3.3V MAIN Digital

PVDD 3.3V MAIN Digital

PVDDM 3.3V AUX Digital

PVDDP 1.8V MAIN Digital

PVDDZ 1.8V MAIN Digital

SDAVDD 3.3V MAIN Analog

SDAVSS 0V GROUND Analog

VDDM 2.5/3.3V MAIN(AUX) Digital

VDDQ 1.5/1.8/3.3V MAIN Digitalv

VDDZ 1.8V MAIN Digital

VDDMCMP 1.8V MAIN Analog

VTT 1.2~1.85V MAIN Digital

Z1XAVDD 3.3V MAIN Analog

Z1XAVSS 0V GROUND Analog

Z4XAVDD 3.3V MAIN Analog Z4XAVSS 0V GROUND Analog


99


Test Mode/Hardware Trap/Power Management Name Pin Attr Signal Description

DLLEN#

I/O 3.3V/5V - M

Hardware Trap pin (refer to section 5)

DRAM_SEL

I 3.3V/5V - AUX

Hardware Trap pin (refer to section 5)

TRAP[1:0]

I 3.3V/5V - M

Hardware Trap pins (refer to section 5)

ENTEST

I 3.3V/5V - M

Test Mode enable pin

TESTMOD E[2:0]

I 3.3V/5V - M

Test Mode select pin Nand Tree Test: 100

AUXOK

I 3.3V - AUXI

Auxiliary Power OK : This signal is supplied from the power source of resume well. It is also used to reset the logic in resume power well. If there is no auxiliary power source on the system, this pin should be tied together with PWROK.

PCIRST#

I 3.3V - AUXI

PCI Bus Reset : PCIRST# is supplied from SiS MuTIOL Media IO SiS961.

PWROK

I 3.3V - AUXI

Main Power OK : A high-level input to this signal indicates the power being supplied to the system is in stable operating state. During the period of PWROK being low, CPURST and PCIRST# will all be asserted until after PWROK goes high for 24 ms.


100


Host Bus Interface Name Pin Attr Signal Description

FERR#

I 1.1V/2.65V -M

Floating Point Error: CPU will assert this signal upon a floating point error occurring.

IGNNE#

OD 1.1V/2.65V -M

Ignore Numeric Error: IGNNE# is asserted to inform CPU to ignore a numeric error.

NMI

OD 1.1V/2.65V -M

Non-Maskable Interrupt: A rising edge on NMI will trigger a non-maskable interrupt to CPU.

INTR

OD 1.1V/2.65V -M

Interrupt Request: High-level voltage of this signal conveys to CPU that there is outstanding interrupt(s) needed to be serviced.

APICD[1:0]

I/OD 1.1V/2.65V -M

APIC Data: These two signals are used to send and receive APIC data.

CPUSLP#/ CPUSTP#

OD 1.1V/2.65V -M

CPU Sleep: The CPUSLP# can be used to force CPU enter the Sleep state. CPU Clock STOP: For Intel Mobile processor, this signal can be used to stop the clock to the processor. If the processor is in Quick Start state and the processor clock is stopped, the processor will enter the Deep Sleep state. For AMD processor, this signal can be to reduce processor voltage during C3/S1 state.

STPCLK#

OD 1.1V/2.65V -M

Stop Clock: STPCLK# will be asserted to inhibit or throttle CPU activities upon a pre-defined power management event occurs

INIT#

OD 1.1V/2.65V -M

Initialization: INIT is used to re-start the CPU without flushing its internal caches and registers. In Pentium III platform it is active high. This signal requires an external pull-up resistor tied to 3.3V.

APICCK

I 2.5V - M

APIC Clock: This signal is used to determine when valid data is being sent over the APCI bus.

A20M#

OD 1.1V/2.65V- M

Address 20 Mask: When A20M# is asserted, the CPU A20 signal will be forced to “0”

MuTIOL Connect Interface Name Pin Attr Signal Description

ZCLK I 3.3V - M

Megaband I/O Connect Clock

ZUREQ

I/O 1.8V - M

Megaband I/O Conect Controll pins

ZDREQ

I/O 1.8V - M

Megaband I/O Conect Controll pins

ZSTB[1:0]

I/O 1.8V - M

Megaband I/O Connect Strobe

ZSTB[1:0]#

I/O 1.8V - M

Strobe Compliment

ZAD[15:0]

I/O 1.8V - M

Address/Data pins

ZVRE I -M Megaband I/O Connect I/O reference voltage ZCMP_N I -M N-MOS Compensation Input ZCMP_P I -M P-MOS Compensation input

PCI Interface Name Pin Attr Signal Description

PCICLK

I 3.3V/5V -M

PCI Clock: The PCICLK input provides the fundamental timing and the internal operating frequency for the SiS961. It runs at the same frequency and skew of the PCI local bus.

C/BE[3:0]#

I/O 3.3V/5V -M

PCI Bus Command and Byte Enables: PCI Bus Command and Byte Enables define the PCI command during the address phase of a PCI cycle, and the PCI byte enables during the data phases. C/BE[3:0]# are outputs when the SiS961 is a PCI bus master and inputs when it is a PCI slave.

PLOCK#

I/O 3.3V/5V -M

PCI Lock: When PLOCK# is sampled asserted at the beginning of a PCI cycle, SiS961 considers itself being locked and remains in the locked state until PLOCK# is sampled and negated at the following PCI cycle.

5.3 SiS961 MuTIOL Media I/O Controller

101


PCI Interface Continue Name Pin Attr Signal Description

AD[31:0]

I/O 3.3V/5V -M

PCI Address /Data Bus: In address phase: 1.When the SiS961 is a PCI bus master, AD[31:0] are output signals. 2.When the SiS961 is a PCI target, AD[31:0] are input signals.In data phase: 1.When the SiS961 is a target of a memory read/write cycle, AD[31:0] are floating. 2.When the SiS961 is a target of a configuration or an I/O cycle, AD[31:0] are output signals in a read cycle, and input signals in a write cycle.

PAR

I/O 3.3V/5V -M

Parity: SiS961 drives out Even Parity covering AD[31:0] and C/BE[3:0]#. It does not check the input parity signal.

FRAME#

I/O 3.3V/5V -M

Frame#: FRAME# is an output when the SiS961 is a PCI bus master. The SiS961 drives FRAME# to indicate the beginning and duration of an access. When the SiS961 is a PCI slave device, FRAME# is an input signal.

IRDY#

I/O 3.3V/5V -M

Initiator Ready: IRDY# is an output when the SiS961 is a PCI bus master. The assertion of IRDY# indicates the current PCI bus master's ability to complete the current data phase of the transaction. For a read cycle, IRDY# indicates that the PCI bus master is prepared to accept the read data on the following rising edge of the PCI clock. For a write cycle, IRDY# indicates that the bus master has driven valid data on the PCI bus. When the SiS961 is a PCI slave, IRDY# is an input pin.

TRDY#

I/O 3.3V/5V -M

Target Ready: TRDY# is an output when the SiS961 is a PCI slave. The assertion of TRDY# indicates the target agent's ability to complete the current data phase of the transaction. For a read cycle, TRDY# indicates that the target has driven valid data onto the PCI bus. For a write cycle, TRDY# indicates that the target is prepared to accept data from the PCI bus. When the SiS961 is a PCI master, it is an input pin.

STOP#

I/O 3.3V/5V -M

Stop#: STOP# indicates that the bus master must start terminating its current PCI bus cycle at the next clock edge and release control of the PCI bus. STOP# is used for disconnection, retry, and target-abortion sequences on the PCI bus.

Name Pin Attr Signal Description DEVSEL#

I/O 3.3V/5V -M

Device Select: As a PCI target, SiS961 asserts DEVSEL# by doing positive or subtractive decoding. SiS961 positively asserts DEVSEL# when the DRAM address is being accessed by a PCI master, PCI configuration registers or embedded controllers’ registers are being addressed, or the BIOS memory space is being accessed. The low 16K I/O space and low 16M memory space are responded subtractively. The DEVESEL# is an input pin when SiS961 is acting as a PCI master. It is asserted by the addressed agent to claim the current transaction.

PREQ[4:0]#

I 3.3V/5V -M

PCI Bus Request: PCI Bus Master Request Signals

PGNT[4:0]#

O 3.3V –M

PCI Bus Grant: PCI Bus Master Grant Signals

PREQ5# / GPIO5

I I/O 3.3V/5V- M

PCI Bus Request: PCI Bus Master Request Signal

PGNT5# / GPIO6

O I/O 3.3V- M

PCI Bus Grant: PCI Bus Master Grant Signal

INT[A:D]#

I 3.3V/5V –M

PCI interrupt A,B,C,D: The PCI interrupts will be connected to the inputs of the internal Interrupt controller through the rerouting logic associated with each PCI interrupt.

PCIRST#

O 3.3V –M

PCI Bus Reset: PCIRST# will be asserted during the period when PWROK is low, and will be kept on asserting until about 24ms after PWROK goes high.

SERR#

I 3.3V/5V –M

System Error: When sampled active low, a non-maskable interrupt (NMI) can be generated to CPU if enabled.


102


IED Interface Name Pin Attr Signal Description

IDA[15:0]

I/O 3.3V/5V -M

Primary Channel Data Bus

IDB[15:0]

I/O 3.3V/5V -M

Secondary Channel Data Bus

IDECSA[1:0]#

O 3.3V -M

Primary Channel CS[1:0]

IDECSB[1:0]#

O 3.3V -M

Secondary Channel CS[1:0]

IIOR[A:B]#

O 3.3V -M

Primary/Secondary Channel IOR# Signals

IIOW[A:B]#

O 3.3V -M

Primary/Secondary Channel IOW# Signals

ICHRDY[A:B]

I 3.3V/5V -M

Primary/Secondary Channel ICHRDY# Signals

IDREQ[A:B]

I 3.3V/5V -M

Primary/Secondary Channel DMA Request Signals

IDACK[A:B]#

O 3.3V -M

Primary/Secondary Channel DMACK# Signals

IIRQ[A:B]

I 3.3V/5V -M

Primary/Secondary Channel Interrupt Signals

IDSAA[2:0]

O 3.3V -M

Primary Channel Address [2:0]

IDSAB[2:0]

O 3.3V -M

Secondary Channel Address [2:0]

CBLID[A:B]

I 3.3V/5V -M

Primary/Secondary Ultra-66 Cable ID

Power Management Interface Name Pin Attr Signal Description

ACPILED

OD <=5V -AUX

ACPILED : ACPILED can be used to control the blinking of an LED at the frequency of 1Hz to indicate the system is at power saving mode.

EXTSMI# / GPIO3

I I/O 3.3V/5V -M

External SMI#: EXTSMI# can be used to generate wakeup event, sleep event, or SCI/SMI# event to the ACPI compatible power management unit.

PME#

I 3.3V/5V -AUX

PME# : When the system is in power-down mode, an active low event on PME# will cause the PSON# to go low and hence turn on the power supply. When the system is in suspend mode, an active PME# event will cause the system wakeup and generate an SCI/SMI#.

PSON#

OD <=5V -AUX

ATX Power ON/OFF control: PSON# is used to control the on/off state of the ATX power supply. When the ATX power supply is in the OFF state, an activated power-on event will force the power supply to ON state.

AUXOK

I 3.3V -AUX

Auxiliary Power OK: This signal is supplied from the AUX power source. It is also used to reset the logic in AUX power well. If there is no auxiliary power source on the system, this pin should be tied together with PWROK.

PWRBTN#

I 3.3V/5V -AUX

Power Button: This signal is from the power button switch and will be monitored by the ACPI-compatible power management unit to switch the system between working and sleeping states.

RING / GPIO8

I I/O 3.3V/5V -AUX

Ring Indication: An active RING pulse and lasting for more than 4ms will cause a wakeup event for system to wake from S1~S5.

BCLK_STP# GPIO12

O I/O 3.3V/5V -AUX

Stop CPU clock: Output to the external clock generator for it to turn off the CPU clock during C3/Sx.

DPRSLPVR GPIO13

O O 3.3V/5V -AUX

Deeper Sleep: DPRSLP# can be used to lower the Intel processor voltage during C3/S1 state.

Legacy I/O and Miscellaneous Signals Signal Name Pin Attr Signal Description

SPK O 3.3V -M

Speaker output: The SPK is connected to the system speaker.

ENTEST I 3.3V/5V -M

SiS961 Test Mode Enable Pin

OSCI I 3.3V -M

SiS961 Test Mode Enable Pin


103


Keyboard Control Interface Name Pin Attr Signal Description

KBDAT / GPIO15

I/OD O/OD 3.3V/5V -AUX

Keyboard Dada: When the internal keyboard controller is enabled, this pin is used as the keyboard data signal.

KBCLK / GPIO16


Keyboard Clock: When the internal keyboard controller is enabled, this pin is used as the keyboard clock signal.

PMDAT / GPIO17


PS2 Mouse Data: When the internal keyboard and PS2 mouse controllers are enabled, this pin is used as PS2 mouse data signal.

PMCLK / GPIO18


PS2 Mouse Clock: When the internal keyboard and PS2 mouse controllers are enabled, this pin is used as the PS2 mouse clock signal.

MAC Interface Name Pin Attr Signal Description

RXER

I 3.3V/5V -AUX

RX Packet Error This event is signaled after the last received descriptor in a failed packet reception that has been updated with valid status.

MIICLK25M

I 3.3V/5V -AUX

PHY 25MHz Clock Input: This pin provides the 25MHz clock signal input to the built-in oscillator.

MDC O 3.3V -AUX

Management Data Clock: Clock signal with a maximum rate of 2.5MHz used to transfer management data for the external physical unit on the MIIMDIO pin.

TXD[0:3]

I 3.3V/5V -AUX

Receive Data: This is a group of 4 data signals aligned on nibble boundaries which are driven synchronous to the RXCLK by the external physical unit.

TXEN

O 3.3V -AUX

Transmit Data: This is a group of 4 data signals which are driven synchronous to the TXCLK for transmission to the external physical unit.

RXD[0:3]

I 3.3V/5V -AUX

Receive Data: This is a group of 4 data signals aligned on nibble boundaries which are driven synchronous to the RXCLK by the external physical unit.

Name Pin Attr Signal Description TXEN

O 3.3V -AUX

Transmit Enable: When set to a 1, and the transmit state machine is idle, then the transmit state machine becomes active. This bit will read back as a 1 whenever the transmit state machine is active. After initial power-up, software must insure that the transmitter has completely reset before setting this bit

MDIO

I/O 3.3V/5V -AUX

Management Data I/O: Bi-direction signal used to transfer management information for the external physical unit. Requires external pull-up resistor.

RXDV

I 3.3V/5V -AUX

Receive Data Valid. This indicates that the external physical unit is presenting recovered and decoded nibbles on the RXD[3:0] and that RXCLK is synchronous to the recovered data. This signal will encompass the frame, starting with the Start-Of-Frame delimiter and excluding the End-Of-Frame delimiter.

COL

I 3.3V/5V -AUX

Collision Detect: This signal is asserted high asynchronous by the external physical unit upon detection of a collision on the medium. It’ll remain asserted as long as the collision condition persists.

CRS

I 3.3V/5V -AUX

Carrier Sense: This signal is asserted high asynchronously by the physical unit upon detection of a non-idle medium.

RXCLK

I 3.3V/5V -AUX

Receive Clock A continuous clock that is recovered from the incoming data. During 100Mb/s operation RXCLK is 25MHz and during 10Mb/s this is 2.5MHz.

TXCLK

I 3.3V/5V -AUX

Transmit Clock A continuous clock that is sourced by the physical unit. During 100Mb/s operation RXCLK is 25MHz and during 10Mb/s this is 2.5MHz.


104


LPC Interface Name Pin Attr Signal Description

LAD[3:0]

I/O 3.3V/5V-M

LPC Address/Data Bus: LPC controller drives these four pins to transmit LPC command, address, and data to LPC device.

LDRQ#

I 3.3V/5V-M

LPC DMA Request 0: This pin is used by LPC device to request DMA cycle.

LDRQ1# / GPIO1

I I/O 3.3V/5V-M

LPC DMA Request 1: This pin is used by LPC device to request DMA cycle.

LFRAME#

O 3.3V -M

LPC Frame: This pin is used to notify LPC device that a start or a abort LPC cycle will occur.

SIRQ

I/O 3.3V/5V -M

I/O 3.3V/5V -M

TRC Interface Name Pin Attr Signal Description

BATOK

I 3.3V -RTC

Battery Power OK: When the internal RTC is enabled, this signal is used to indicate that the power of RTC well is stable. It is also used to reset the logic in RTC well. If the internal RTC is disabled, this pin should be tied low.

OSC32KHI

I 3.3V-RTC

RTC 32.768 KHz Input: When internal RTC is enabled, this pin provides the 32.768 KHz clock signal from external crystal or oscillator.

OSC32KHO

O <3.3V -RTC

RTC 32.768 KHz Output: When internal RTC is enabled, this pin should be connected with the other end of the 32.768 KHz crystal or left unconnected if an external oscillator is used.

PWROK

I 3.3V-RTC

Main Power OK: A high-level input to this signal indicates the power being supplied to the system is in stable operating state. During the period of PWROK being low, PCIRST# will all be asserted until after PWROK goes high for 12 ms.

AC’97 Interface Name Pin Attr Signal Description

AC_BIT_CLK

I 3.3V/5V -M

AC’97 Bit Clock: This signal is a 12.288MHz serial data clock, which is generated by primary Codec.

AC_RESET#

O 3.3V -AUX

AC’97 Reset: Hardware reset signal for external Codecs.

AC_SDIN0

I 3.3V/5V -AUX

AC’97 Serial Data Input : Serial data input from primary Codec.

AC_SDIN1

I 3.3V/5V -AUX

AC’97 Serial Data Input: Serial data input from secondary Codec. When Modem Codec is used, this pin dedicate to Modem Serial data input.

AC_SDIN[3:2]/GPIO[10:9]

I I/O 3.3V/5V -AUX

AC’97 Serial Data Input: Serial data input from third and forth Audio Codec.

AC_SDOUT

O 3.3V -M

AC’97 Serial Data Output: Serial data output to Codecs.

AC_SYNC

O 3.3V -M

AC’97 Synchronization: This is a 48KHz signal, which is used to synchronize the Codecs

USB Interface Name Pin Attr Signal Description

USBCLK48M

I 3.3V/5V -M

USB 48 MHz clock input: This signal provides the fundamental clock for the USB Controller.

OC[0:5]#

I/O 3.3V/5V - AUX

USB Port 0-5 Overcurrent Detection: OC[0:5]# are used to detect the overcurrent condition of USB Ports 0-5.

UV[2:0]+, UV[2:0]-

I/O 3.3V - AUX

USB Port [2:0] Differential: These differential pairs are used to transmit Data/Address /Command signals for ports 0-2. (USB controller 1)

UV[5:3]+, UV[5:3]-

I/O 3.3V - AUX

USB Port [5:3] Differential: These differential pairs are used to transmit Data/Address/ Command signals for ports 3-5. (USB controller 2)


105


General Purpose I/O Signal Name Pin Attr Signal Description

GPIO[6:0]

I/O 3.3V/5V -M

GPIO: Can be a general purpose input or output.

GPIO14,[12:7]

I/O 3.3V/5V -AUX

GPIO : Can be a general purpose input or output.

GPIO13

O 3.3V/5V - AUX

GPO: Can be a general purpose output.

GPIO[18:15]

O 3.3V/5V - AUX

GPO: Can be a general purpose output.

GPIO[20:19]

I/O 3.3V/5V - AUX

GPIO: Can be a general purpose input or output.

Power and Ground Signals Name Tolerance Power Plane Type Attribute

VSS 0V GROUND Digital VSSZ 0V GROUND Digital

IVDD 1.8V MAIN Digital

PVDDZ 1.8V MAIN Digital

VDDZ 1.8V MAIN Digital

VDDZCMP 1.8V MAIN Analog

VSSZCMP 0V GROUND Analog

ZVSSREF 0V GROUND Analog

PVDD 3.3V MAIN Digital

OVDD 3.3V MAIN Digital

VTT 1.1V-2.65V MAIN Digital

IVDD_AUX 1.8V AUX Digital

PVDD_AUX 3.3V AUX Digital

OVDD_AUX 3.3V AUX Digital

MIIAVDD 3.3V AUX Analog

MIIAVSS 0V GROUND Analog

USBVDD 3.3V AUX Analog

USBVSS 0V GROUND Analog

RTCVDD 3.3V RTC Analog

RTCVSS 0V GROUND Analog





IDEAVDD 1.8V MAIN Analog

IDEAVSS 0V GROUND Analog


106


5.4 SiS301LV / Chrontel CH7019 TV/LVDS EncoderPin # Type Symbol Description

66,101 In/Out H1,H2 Horizontal Sync Input / Output When the SYO control bit is low, these pins accept a horizontal sync inputs for use with the input data. The amplitude will be 0 to VDDV. VREF1 is the threshold level for these inputs. These pins must be used as inputs in RGB Bypass mode. When the SYO control bit is high, the TV encoder will output a horizontal sync pulse 64 pixels wide to one of these pins. The output is driven from the DVDD supply. This output is valid only when TV-Out is in operation.

65,102 In/Out V1,V2 Vertical Sync Input / Output When the SYO control bit is low, these pins accept a vertical sync inputs for use with the input data. The amplitude will be 0 to VDDV. VREF1 signal is the threshold level. These pins must be used as inputs in RGB Bypass mode. When the SYO control bit is high, the TV encoder will output a vertical sync pulse one line wide to one of these pins. The output is driven from the DVDD supply. This output is valid only when TV-Out is in operation.

63,104 In DE1,DE2 Data Enable These pins accept a data enable signal which is high when active video data is input to the device, and remains low during all other times. The levels are 0 to VDDV. VREF1 is the threshold level. One of these inputs is used by the LVDS links. The TV-Out function uses H and V sync signals and values in the SAV register as reference to active video.

62,105

Out FLD/STL1 FLD/STL2

TV Field / Flat Panel Stall Signal These outputs can be programmed to be either a TV Field output from the TV encoder or a Stall output from the flat panel Up-scaler. These outputs are tri-stated upon power up.

107 In/Out SPD Serial Port Data Input / Output This pin functions as the bi-directional data pin of the serial port, and uses VREF2 / 2 as the threshold voltage. VREF2 divide by 2 function is generated on-chip.

108 In SPC Serial Port Clock Input This pin functions as the clock input of the serial port and uses VREF2 / 2 as the threshold voltage. VREF2 divide by 2 function is generated on-chip.

106 In AS Address Select (Internal Pull-up) This pin determines the device address of the serial port.

Pin # Type Symbol Description 112 In/Out SDD Low-Voltage DDC Serial Data

Low-voltage serial data for DDC. It uses VREF2 / 2 as the threshold voltage. VREF2 divide by 2 function is generated on-chip.

113 In/Out SDC Low-Voltage DDC Serial Clock Low-voltage serial clock for DDC. It uses VREF2 / 2 as the threshold voltage. VREF2 divide by 2 function is generated on-chip.

114,116 In/Out DD1, DD2 DDC Serial Data Serial data for DDC. (0V to 5V) .

111

In VREF2 Reference Voltage 2 Used to generate the threshold level for SDD, SDC, SPD and SPC port. This pin should be tied externally to the maximum voltage seen by the ports. (1.5V to 3.3V).

115,117 In/Out DC1,DC2 DDC Serial Clock Clock for DDC. (0V to 5V)

123-126 56,57

In/Out GPIO[5:0] General Purpose Input / Output [5:0] These pins provide general purpose I/O and are controlled via the serial port. (3.3V).

127 Out ENAVDD Panel Power Enable Enable panel VDD. (3.3V)

128 Out ENABLK Back Light Enable Enable Back-Light of LCD Panel. (3.3V)

121 In HPD Hot Plug Detect (Internal Pull-down) This input pin determines whether a CRT monitor is connected to the VGA connector. When terminated, the monitor is required to apply a voltage greater than 2.4 volts. Changes on the status of this pin will be relayed to the graphics controller via the HPINT* pin pulling low.

122 Out HPINT* Hot Plug Interrupt Output This pin provides an open drain output, which pulls low when a termination change has been detected on the HPD input.

36 In VSWING LVDS Voltage Swing Control This pin sets the swing level of the LVDS outputs. A 2.4K Ohm resistor should be connected between this pin and LGND ( pin 35) using short and wide traces.

58 In RESET* Reset * Input (Internal Pull-up) When this pin is low, the device is held in the power on reset condition. When this pin is high, reset is controlled through the serial port.

107



2 Analog LPLLCAP LVDS PLL Capacitor This pins allows coupling of any signal to the on-chip loop filter capacitor.

5,24 Out LL2C,LL1C Positive LVDS differential Clock2 & Clock1 6,25 Out LL2C*,LL1C* Negative LVDS differential Clock2 & Clock1 8,11,14,17 Out LDC[7:4] Positive LVDS differential data[7:4] 9,12,15,18 Out LDC[7:4]* Negative LVDS differential data[7:4] 21,27,30,33 Out LDC[3:0] Positive LVDS differential data[3:0] 22,28,31,34 Out LDC[3:0]* Negative LVDS differential data [3:0] 38 Analog ISET Current Set Resistor Input

This pin sets the DAC current. A 140-ohm resistor should be connected between this pin and DAC_GND (pin 39) using short and wide traces.

40,42,44,46 Out DACB[3:0] DAC Output B Video Digital-to-Analog outputs.

41,43,45,47 Out DACA[3:0] DAC Output A Video Digital-to-Analog outputs.

120 Out VOUT V-Sync Output This pin is the output of a voltage translating digital buffer and is driven from V5V.

110 In VIN V-Sync Input This pin is the input of a voltage translating digital buffer. Input threshold can be programmed by serial port to equal to VREF2/2 or to DVDD/2. The amplitude will be 0 to VDDV. VREF1 is the threshold level for these inputs.

119 Out HOUT H-Sync Output This pin is the output of a voltage translating digital buffer and is driven from V5V.

109 In HIN H-Sync Input This pin is the input of a voltage translating digital buffer. Input threshold can be programmed by serial port to equal to VREF2/2 or to DVDD/2.

49 Out C/HSYNC Composite / Horizontal Sync Provides composite sync in TV modes and horizontal sync in bypass RGB mode. This pin is driven by the DVDD supply.

50 Out BCO/VSYNC Buffered Clock Outputs / Vertical Sync This output pin provides buffered crystal oscillator clock output or VSYNC output in bypass RGB mode. This pin is driven by the DVDD supply.

Pin # Type Symbol Description 52 In XI/FIN Crystal Input / External Reference Input

A parallel resonant 14.31818MHz crystal (+ 20 ppm) should be attached between this pin and XO. However, an external CMOS compatible clock can drive the XI/FIN input.

53 Out XO Crystal Output A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached between this pin and XI / FIN. However, if an external CMOS clock is attached to XI/FIN, XO should be left open.

59 Out P-OUT Pixel Clock Output This pin provides a pixel clock signal to the VGA controller which can be used as a reference frequency. The output is selectable between 1X and 2X of the pixel clock frequency. The output driver is driven from the VDDV supply (pin 60). This output has a programmable tri-state. The capacitive loading on this pin should be kept to a minimum.

61 In VREF1 Reference Voltage Input 1 The VREF1 pin inputs a reference voltage of VDDV / 2. The signal is derived externally through a resistor divider and decoupling capacitor, and will be used as a reference level for data, sync and clock inputs.

68-73,77-82 In D1[11:0] Data1[11] through Data1[0] Inputs These pins accept the 12 data inputs from a digital video port of a graphics controller. The levels are 0 to VDDV. VREF1 is the threshold level.

76,74 In XCLK1 XCLK1*

External Clock Inputs These inputs form a differential clock signal input to the device for use with the H1, V1 and D1[11:0] data. If differential clocks are not available, the XCLK1* input should be connected to VREF1. The clock polarity can be selected by the MCP1 control bit.

85-90,94-99 In D2[11:0] Data2[11] through Data2[0] Inputs These pins accept the 12 data inputs from a digital video port of a graphics controller. The levels are 0 to DVDDV. VREF1 is the threshold level.

93,91 In XCLK XCLK2*

External Clock Inputs These inputs form a differential clock signal input to the device for use with the H2, V2 and D2[11:0] data. If differential clocks are not available, the XCLK2* input should be connected to VREF1. The clock polarity can be selected by the MCP2 control bit.

108



118 Power V5V 5V supply for H/VOUT (5V) 64,83,84,103 Power DVDD Digital Supply Voltage (3.3V) 67,75,92,100 Power DGND Digital Ground 60 Power VDDV I/O Supply Voltage (1.1V to 3.3V) 55 Power TVPLL_VDD TV PLL Supply Voltage (3.3V) 54 Power TVPLL_VCC TV PLL Supply Voltage (3.3V) 51 Power TVPLL_GND TV PLL Ground 37 Power DAC_VDD DAC Supply Voltage (3.3V) 39,48 Power DAC_GND DAC Ground 7,13,19,20,26,32 Power LVDD LVDS Supply Voltage (3.3V) 4,10,16,23,29,35 Power LGND LVDS Ground 1 Power LPLL_VDD LVDS PLL Supply Voltage (3.3V) 3 Power LPLL_GND LVDS PLL Ground

109


5.5 PCI1410GGU PCMCIA ControllerPower Supply

Name I/O Description GND Device ground terminals VCC Power supply terminal for core logic (3.3V) VCCCB Clamp voltage for PC Card interface. Matches card signaling environment,

5 V or 3.3 V. VCCI Clamp voltage for interrupt subsystem interface and miscellaneous I/O, 5 V

or 3.3 V VCCP Clamp voltage for PCI signaling, 5 V or 3.3 V PC Card Power Switch

Name I/O Description VCCD0 VCCD1

O Logic controls to the TPS2211 PC Card power interface switch to control AVCC.

VPPD0 VPPD1

O Logic controls to the TPS2211 PC Card power interface switch to control AVPP.

PCI System

Name I/O Description GRST# I Global reset. When the global reset is asserted, the GRST# signal causes the

PCI1410 to place all output buffers in a high-impedance state and reset all internal registers. When GRST# is asserted, the device is completely in its default state. For systems that require wake-up from D3, GRST# will normally be asserted only during initial boot. PRST# should be used following initial boot so that PME context is retained when transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST# should be tied to PRST#. When the SUSPEND# mode is enabled, the device is protected from the GRST#, and the internal registers are preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

PCLK I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PRST# I PCI reset. When the PCI bus reset is asserted, PRST# causes the PCI1410 to place all output buffers in a high-impedance state and reset internal registers. When PRST# is asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI1410 is in a default state. When the SUSPEND# mode is enabled, the device is protected from the PRST#, and the internal registers are preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

PCI Interface Control Name I/O Description

DEVSEL# I/O PCI device select. The PCI1410 asserts DEVSEL# to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1410 monitors DEVSEL# until a target responds. If no target responds before timeout occurs, then the PCI1410 terminates the cycle with an initiator abort.

FRAME# I/O PCI cycle frame. FRAME# is driven by the initiator of a bus cycle. FRAME# is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME# is deasserted, the PCI bus transaction is in the final data phase.

GNT# I PCI bus grant. GNT# is driven by the PCI bus arbiter to grant the PCI1410 access to the PCI bus after the current data transaction has completed. GNT# may or may not follow a PCI bus request, depending on the PCI bus parking algorithm.

IDSEL I Initialization device select. IDSEL selects the PCI1410 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

IRDY# I/O PCI initiator ready. IRDY# indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY# and TRDY# are asserted. Until IRDY# and TRDY# are both sampled asserted, wait states are inserted.

PERR# I/O PCI parity error indicator. PERR# is driven by a PCI device to indicate that calculated parity does not match PAR when PERR# is enabled through bit 6 of the command register.

REQ# O PCI bus request. REQ# is asserted by the PCI1410 to request access to the PCI bus as an initiator.

SERR# O PCI system error. SERR# is an output that is pulsed from the PCI1410 when enabled through bit 8 of the command register indicating a system error has occurred. The PCI1410 need not be the target of the PCI cycle to assert this signal. When SERR# is enabled in the command register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface.

STOP# I/O PCI cycle stop signal. STOP# is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP# is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers.

TRDY# I/O PCI target ready. TRDY# indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY# and TRDY# are asserted. Until both IRDY# and TRDY# are asserted, wait states are inserted.

110


5.5 PCI1410GGU PCMCIA ControllerPCI Address and Data

Name I/O Description AD[31:0] I/O PCI address/data bus. These signals make up the multiplexed PCI address

and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data.

C/BE#[3:0] I/O PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE#3–C/BE#0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE#0 applies to byte 0 (AD7–AD0), C/BE#1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE#3 applies to byte 3 (AD31–AD24).

PAR I/O PCI bus parity. In all PCI bus read and write cycles, the PCI1410 calculates even parity across the AD31–AD0 and C/BE#3–C/BE#0 buses. As an initiator during PCI cycles, the PCI1410 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR#).

16-Bit PC Card Address and Data (Slots A and B)

Name I/O Description ADDR[25:0] O PC Card address. 16-bit PC Card address lines. ADDR25 is the most

significant bit. DATA[15:0] I/O PC Card data. 16-bit PC Card data lines. DATA15 is the most significant

bit.

Multifunction and Miscellaneous Pins Name I/O Description

MFUNC0 I/O Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA#, GPI0, GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ.

MFUNC1 I/O Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ. Serial data (SDA). When VPPD0 and VPPD1 are high after a PCI reset, the MFUNC1 terminal provides the SDA signaling for the serial bus interface. The two-pin serial interface loads the subsystem identification and other register defaults from an EEPROM after a PCI reset.

MFUNC2 I/O Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, RI_OUT#, or a parallel IRQ.

MFUNC3 I/O Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER.

MFUNC4 I/O Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK#, GPI3, GPO3, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, RI_OUT#, or a parallel IRQ. Serial clock (SCL). When VPPD0 and VPPD1 are high after a PCI reset, the MFUNC4 terminal provides the SCL signaling for the serial bus interface. The two-pin serial interface loads the subsystem identification and other register defaults from an EEPROM after a PCI reset.

MFUNC5 I/O Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant, GPI4, GPO4, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ.

MFUNC6 I/O Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN# or a parallel IRQ.

RI_OUT#/PME# O Ring indicate out and power management event output. Terminal provides an output for ring-indicate or PME# signals.

SPKROUT O Speaker output. SPKROUT is the output to the host system that can carry SPKR# or CAUDIO through the PCI1410 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR#//CAUDIO inputs.

SUSPEND# I Suspend. SUSPEND# protects the internal registers from clearing when the GRST# or PRST# signal is asserted.

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5.5 PCI1410GGU PCMCIA Controller16-Bit PC Card Interface Control (Slots A and B)

Name I/O Description BVD1 (STSCHG#/RI#)

I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. Status change. STSCHG# is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.

BVD2 (SPKR#)

I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. Speaker. SPKR# is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1410 and are output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.

CD1# CD2#

I Card detect 1 and Card detect 2. CD1# and CD2# are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1# and CD2# are pulled low.

CE1# CE2#

O Card enable 1 and card enable 2. CE1# and CE2# enable even- and odd-numbered address bytes. CE1# enables even-numbered address bytes, and CE2# enables odd-numbered address bytes.

INPACK# I Input acknowledge. INPACK# is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK# can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If it is used as a strobe, then the PC Card asserts this signal to indicate a request for a DMA operation.

IORD# O I/O read. IORD# is asserted by the PCI1410 to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD# is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1410 asserts IORD# during DMA transfers from the PC Card to host memory.

IOWR# O I/O write. IOWR# is driven low by the PCI1410 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. DMA read. IOWR# is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1410 asserts IOWR# during transfers from host memory to the PC Card.

Name I/O Description OE# O Output enable. OE# is driven low by the PCI1410 to enable 16-bit memory PC

Card data output during host memory read cycles. DMA terminal count. OE# is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1410 asserts OE# to indicate TC for a DMA write operation.

READY (IREQ#)

I Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ# is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I /O PC Card requires service by the host software. IREQ# is high (deasserted) when no interrupt is requested.

REG# O Attribute memory select. REG# remains high for all common memory accesses. When REG# is asserted, access is limited to attribute memory (OE# or WE# active) and to the I/O space (IORD# or IOWR# active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG# is used as a DMA acknowledge (DACK#) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1410 asserts REG to indicate a DMA operation. REG# is used in conjunction with the DMA read (IOWR#) or DMA write (IORD#) strobes to transfer data.

RESET O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. WAIT# I Bus cycle wait. WAIT# is driven by a 16-bit PC Card to extend the completion of

the memory or I/O cycle in progress. WE# O Write enable. WE# is used to strobe memory write data into 16-bit memory PC

Cards. WE# is also used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE# is used as TC# during DMA operations to a 16-bit PC Card that supports DMA. The PCI1410 asserts WE# to indicate TC# for a DMA read operation.

WP (IOIS16#)

I Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16#) function. I/O is 16 bits. IOIS16# applies to 16-bit I/O PC Cards. IOIS16# is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, then the PC Card asserts WP to indicate a request for a DMA operation.

VS1# VS2#

I/O Voltage sense 1 and voltage sense 2. VS1# and VS2#, when used in conjunction with each other, determine the operating voltage of the PC Card.

112


5.5 PCI1410GGU PCMCIA ControllerCardBus PC Card Interface System (Slots A and B)

Name I/O Description CCLK O CardBus clock. CCLK provides synchronous timing for all transactions on

the CardBus interface. All signals except CRST#, CCLKRUN#, CINT#, CSTSCHG, CAUDIO, CCD2#, CCD1#, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings.

CCLKRUN# I/O CardBus clock run. CCLKRUN# is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1410 to indicate that the CCLK frequency is going to be decreased.

CRST# O CardBus reset. CRST# brings CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST# is asserted, all CardBus PC Card signals are placed in a high-impedance state, and the PCI1410 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

CardBus PC Card Address and Data (Slots A and B)

Name I/O Description CAD[31:0] I/O CardBus address and data. These signals make up the multiplexed CardBus

address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most significant bit.

CC/BE#[3:0] I/O CardBus bus commands and byte enables. CC/BE#3–CC/BE#0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE#3–CC/BE#0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE#0 applies to byte 0 (CAD7–CAD0), CC/BE#1 applies to byte 1 (CAD15–CAD8), CC/BE#2 applies to byte 2 (CAD23–CAD8), and CC/BE#3 applies to byte 3 (CAD31–CAD24).

CPAR I/O CardBus parity. In all CardBus read and write cycles, the PCI1410 calculates even parity across the CAD and CC/BE# buses. As an initiator during CardBus cycles, the PCI1410 outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion.

CardBua PC Card Interface Control (Slots A and B) Name I/O Description

CAUDIO I CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1410 supports the binary audio mode and outputs a binary signal from the card to SPKROUT.

CBLOCK# I/O CardBus lock. CBLOCK# is used to gain exclusive access to a target. CCD1# CCD2#

I CardBus detect 1 and CardBus detect 2. CCD1# and CCD2# are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type.

CE1# CE2#

O Card enable 1 and card enable 2. CE1# and CE2# enable even- and odd-numbered address bytes. CE1# enables even-numbered address bytes, and CE2# enables odd-numbered address bytes.

CDEVSEL# I/O CardBus device select. The PCI1410 asserts CDEVSEL# to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1410 monitors CDEVSEL# until a target responds. If no target responds before timeout occurs, then the PCI1410 terminates the cycle with an initiator abort.

CFRAME# I/O CardBus cycle frame. CFRAME# is driven by the initiator of a CardBus bus cycle. CFRAME# is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME# is deasserted, the CardBus bus transaction is in the final data phase.

CGNT# O CardBus bus grant. CGNT# is driven by the PCI1410 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed.

CINT# I CardBus interrupt. CINT# is asserted low by a CardBus PC Card to request interrupt servicing from the host.

CIRDY# I/O CardBus initiator ready. CIRDY# indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY# and CTRDY# are asserted. Until CIRDY# and CTRDY# are both sampled asserted, wait states are inserted.

113


5.5 PCI1410GGU PCMCIA ControllerCardBua PC Card Interface Control (Slots A and B) Continue

Name I/O Description CPERR# I/O CardBus parity error. CPERR# reports parity errors during CardBus

transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected.

CREQ# I CardBus request. CREQ# indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator.

CSERR# I CardBus system error. CSERR# reports address parity errors and other system errors that could lead to catastrophic results. CSERR# is driven by the card synchronous to CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1410 can report CSERR# to the system by assertion of SERR# on the PCI interface.

CSTOP# I/O CardBus stop. CSTOP# is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP# is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers.

CSTSCHG I CardBus status change. CSTSCHG alerts the system to a change in the card’s status, and is used as a wake-up mechanism.

CTRDY# I/O CardBus target ready. CTRDY# indicates the CardBus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY# and CTRDY# are asserted; until this time, wait states are inserted.

CVS1 CVS2

I/O CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1# and CCD2# to identify card insertion and interrogate cards to determine the operating voltage and card type.

114


5.6 uPD72872 IEEE1394 ControllerPCI/Cardbus Interface Signals: (52 pins)

Name I/O PIN NO. IOL Volts(V) Function Block*PAR I/O 44 PCI/Cardbus 5/3.3 Parity is even parity across

AD0-AD31 and CBE0-CBE3. It is an input when AD0-AD31 is an input; it is an output when AD0-AD31 is an output.

Link

AD0-AD31 I/O 9, 10, 12, 13, 15-18, 23, 24, 26-29, 32, 33, 47-50, 52, 53, 55, 56, 58,59, 62, 63, 65-68

PCI/Cardbus 5/3.3 PCI Multiplexed Address and Data

Link

CBE0-CBE3 I 21, 34, 45, 57 - 5/3.3 Command/Byte Enables are multiplexed Bus Commands & Byte enables.

Link

FRAME I/O 35 PCI/Cardbus 5/3.3 Frame is asserted by the initiator to indicate the cycle beginning and is kept asserted during the burst cycle. If Cardbus mode (CARD_ON = 1), this pin should be pulled up to VDD.

Link

TRDY I/O 37 PCI/Cardbus 5/3.3 Target Ready indicates that the current data phase of the transaction is ready to be completed.

Link

IRDY I/O 36 PCI/Cardbus 5/3.3 Initiator Ready indicates that the current bus master is ready to complete the current data phase. During a write, its assertion indicates that the initiator is driving valid data onto the data bus.During a read, its assertion indicates that the initiator is ready to accept data from the currently-addressed target.

Link

Name I/O PIN NO. IOL Volts(V) Function Block* REQ O 8 PCI/Cardbus 5/3.3 Bus_master Request

indicates to the bus arbiter that this device wants to become a bus master.

Link

GNT I 7 - 5/3.3 Bus_master Grant indicates to this device thataccess to the bus has been granted.

Link

IDSEL I 22 - 5/3.3 Initialization Device Select is used as chip select for configuration read/write transaction during the phase of device initialization. If Cardbus mode (CARD_ON = 1), this pin should be pulled up to VDD.

Link

DEVSEL I/O 39 PCI/Cardbus 5/3.3 Device Select when actively driven, indicates that the driving device has decoded its address as the target of the current access.

Link

STOP I/O 40 PCI/Cardbus 5/3.3 PCI Stop when actively driven, indicates that the target is requesting the current bus master to stop the transaction.

Link

PME O 3 PCI/Cardbus 5/3.3 PME Output for power management enable.

Link

CLKRUN I/O 2 PCI/Cardbus 5/3.3 PCICLK Running as input, to determine the status of PCLK; as output, to request starting or speeding up clock.

Link

INTA O 4 PCI/Cardbus 5/3.3 Interrupt the PCI interrupt request A.

Link

115


5.6 uPD72872 IEEE1394 ControllerPCI/Cardbus Interface Signals: (52 pins) Continue

Name I/O PIN NO. IOL Volts(V) Function Block*PERR I/O 41 PCI/Cardbus 5/3.3 Parity Error is used for

reporting data parity errorsduring all PCI transactions, except a Special Cycle. It is an output when AD0-AD31 and PAR are both inputs. It is an input when AD0-AD31 and PAR are both outputs.

Link

SERR O 42 PCI/Cardbus 5/3.3 System Error is used for reporting address parity errors, data parity errors during the Special Cycle, orany other system error where the effect can be catastrophic. When reporting address parity errors, it is an output.

Link

PRST I 5 - 5/3.3 Reset PCI reset Link PCLK I 6 - 5/3.3 PCI Clock 33 MHz system

bus clock. Link

Remark *: If the Link pin is pulled up, it should be connected to L_VDD.

116


6. System Block DiagramU1

Pentium 4 Processor-MWillamette/NorthwoodMicro-FCPGA2 478 pin

U504TV-EncoderSiS301LV/

CH7019

LCD PANEL

CRT

TV S-VIDEO

200 pin DDR SO-DIMM Socket * 2

U4 IGUI Host/Memory

Controller SiS650

U6

PCMCIA

ControllerPCI 1410

U505Power Switch

U10

Flash ROM

AC Link U16Amplifier

J18M.D.C RJ-11 Jack

U15

Audio Codec

External Microphone

Internal Microphone

Internal Speaker

SPDIF JACK

USB

Cover Switch

CDROM

HDDU14

MuTIOL Media I/O

Controller

SiS961

FAN

Power Button

Keyboard

Touch Pad

U5LAN PHYRJ-45 Jack

U2 Thermal Sensor

ADM1032

Hyperzip Data Bus

U509

Micro

Controller

H8/F3437

U511

Super I/O

PC87393Print Port

IR ModuleISA BUS

PCMCIA/CARDBUSSocket

J509MINI PCI

Socket

U18IEEE 1394ControlleruPD72872

PCI BUS

LPC

117


7. Maintenance Diagnostics

7.1 Introduction

Each time the computer is turned on, the system bios runs a series of internal checks on the hardware. This power-on self test (post) allows the computer to detect problems as early as the power-on stage. Errormessages of post can alert you to the problems of your computer.

If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs before the display is initialized,then the screen cannot display the error message. Error codes or system beeps are used to identify a post error that occurs when the screen is not available.

The value for the diagnostic port (378H) is written at the beginning of the test. Therefore, if the testfailed, the user can determine where the problem occurred by reading the last value written to port 378H by the 378H port debug board plug at PIO PORT.

118


7.2 Error CodesFollowing is a list of error codes in sequent display on the PIO debug board.

Test 8237A page registers1Fh

Initialize monochrome adapter1Eh

Initialize color adapter1Dh

Initialize video (6845Regs)1Ch

Initialize video adapter(s)1Bh

Reset PIC’s1Ah

Check sum the ROM19h

Dispatch to RAM test18h

Sizememory17h

User register config through CMOS16h

Reset counter / Timer 115h

Search for ISA Bus VGA adapter14h

Initialize the chipset13h

Signal power on reset12h

Turn off FAST A20 for POST11h

Some type of lone reset10h

POST Routine DescriptionCode

Signon messages displayed2Fh

Search for color adapter2Eh

Search for monochrome adapter2Dh

Going to initialize video2Ch

Setup shadow2Bh

Protected mode exit successful2Ah

RAM test completed29h

Protected mode entered safely28h

RAM quick sizing27h

Initialize int vectors26h

Initialize 8237A controller25h

Test the DMA controller24h

Test battery fail & CMOS X-SUM23h

Check if CMOS RAM valid22h

Test keyboard controller21h

Test keyboard20h


119


7.2 Error CodesFollowing is a list of error codes in sequent display on the PIO debug board.

Special init of COMM and LPT ports3Fh

Update NUMLOCK status3Eh

Search and init the mouse3Dh

Initialize the hardware vectors3Ch

Test for RTC ticking3Bh

Test if 18.2Hz periodic working3Ah

Setup cache controller39h

Update output port38h

Protected mode exit successful37h

RAM test complete36h

Protected mode entered safely(2)35h

Test, blank and count all RAM34h

Test keyboard command byte33h

Test keyboard Interrupt32h

Test if keyboard Present31h

Special init of keyboard ctlr30h


USB HC init52h

PM init & Geyserville 51h

ACPI init50h

Jump into bootstrap code49h

Dispatch to operate system boot48h

OEM functions before boot47h

Test for coprocessor installed46h

Update NUMLOCK status45h

OEM’s init of power management44h

Initialize option ROMs43h

Initialize the hard disk42h

Initialize the floppies41h

Configure the COMM and LPT ports40h


120


7.3 Maintenance Diagnostics7.3.1 Diagnostic Tools :

� LED * 8

� PIO CONNECTOR * 1

PIN1 : STROBE PIN 13 : SLCT

PIN10: ACK# PIN 16 : INT#

PIN11: BUSY PIN 17 : SELIN#

PIN12: PTERR PIN 14 : AUTOFD#

PIN{9:2}: PD{7:0}

7.3.2 Circuit:

PIO Connector

LED

111313

14142525

P/N:411904800001Description: PWA; PWA-378Port Debug BDNote: Order it from MIC/TSSC

OR

121


8. Trouble Shooting

� 8.1 No Power

� 8.2 No Display

� 8.3 VGA Controller Failure LCD No Display

� 8.4 External Monitor No Display

� 8.5 Memory Test Error

� 8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error

� 8.7 Hard Driver Test Error

� 8.8 CD-ROM Driver Test Error

� 8.9 PIO Port Test Error

� 8.10 USB Port Test Error

� 8.11 Audio Failure

� 8.12 LAN Test Error

� 8.13 PC Card Socket Failure

� 8.14 IEEE 1394 Failure

122


No power

Connect AC adaptoror battery.

Replace the faultyAC adaptor orBattery.

PowerOK?

No

Yes

No

Try another known goodbattery or AC adapter.

PowerOK?

Yes

Try another known good charger BD.

Is thenotebook connected

to power (either AC adaptoror battery)?

Is theM/B and charger

BD connectedproperly?

No

Replace the faultyCharger BD.

AC

Battery

ADINPALWAYS+DVMAIN+VDD5S

BATTVMAIN-ADENBAT_VBAT_T

J2PF501PL508PL501JS501PU502PD502PD514PD505

PD506PD504

J14PF502PL504PL505PR564PU513

Where frompower source problem

(first use AC to power it)?

Board-levelTroubleshooting

ReplaceMotherboard

Check following parts and signals:

Parts: Signals:

Check following parts and signals:

Parts: Signals:

8.1 No PowerWhen the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

PU512PR551PQ509PQ508RP553PR552

No

Connect AC adaptoror battery.

Yes

123



Main Voltage Map

+DVMAINADINPPOWER IN

ALWAYS

J2

PF501PL501PL508JS501

JO502PU502

P2 P2

PD504

DischargeP2

P2

PD503

PD514PD505PD506

PL504PL505

+DVMAIN1 +3V_P

PU2PU3PU4

JO506JO507

+3VPU503

+3VS

+5V_P

PU4PU5PU6PL3

JO1JO2

+5VPU501

+5VS

USB0VCC5U3

USB5VCC5U1

+12V_P

PU4PU5PU6PL3PU507 JO505

+12VPQ1

+12VS

P2

P2

P2

P3

P2P1P1

P1P1

P1 P1

JO503JO504

+D/VMAINP1 PL7

PU510PU7PU507

+1.8V_PJO501JO502

+1.8VS

+2.5V_PPU8PU509

JO503JO504

+2.5V_DDR

5V_AMPJS2JS3

P20

U512+1.8V

1.25VPU10

+PHYVDDL543

P15

L544P29

MIIAVDDL32

P16

U523USBVDD

P16

P23

P29

+PHYAVDD

+5VS_HDDP17JS4

JS5

+5VS_CDP17JS6

JS7

VCCAP18

U505

VCCPP18

U505

AVDDADJS505L554 P20

+VCC_COREPL501PL502

PU501PU502

PU505PU506

PU508PU1~PU6

P26

P24

P24 P24

P24

P27

VMAINPJ1/J4

To next page

To next page

To next page

PJ2

J7P27

P2

H8_AVREF1

F504U506

Q509P27 +5VA

P27

+5VAS

+3VA

Q8

U17 Q14VCC_RTC

P15P15

P27

+5VQ511

BATT

PD3,PL5,PQ1,PL6,PU9

PU513

P25

Charge

DischargeJ7

PJ2

P27

P2

: Page 6 - 29 of M/B boardcircuit diagram.

: Through by part PF501.

NOTE:

PF501

: Page 1- 3 of D/D boardcircuit diagram.

P29P6

P1 P3

P1

124


VDDA48

VDDZ

L23

L19

P11

P11

L8+3V_LAN

L20VDDPCI

VDDSDL16

SZ1XAVDDL517

L26

VDDAGPL21

L17VDDREF

SZ4XAVDD

+3VS_SPDQ529

VDDCPUP11

L18

P11

P11

P11

P11

P14

P14

P19

20

+VDDV

+TVPLL_VCC

+TVPLL_VDD

P9

P9

P9

L10

L7

L9


+3VSP2

L516DDRAVDD

L15PHYAVDD

AGPAVDD2L511

AGPVREFR62

L13

CPUAVDDL14

L507AGPAVDD1

SDAVDD

P6

P6

P6

P6

P6

DCLKAVDD

ECLKAVDD

Z1XAVDD

Z4XAVDD

P7

P7

P7

P7

P7

P7

L505

L506

L515

L12

L512+DAV_VDD

+LVDD0/1L510

+LVDD2L509

L508+LVDD3

P9

P9

+LPLL_VDD

LCDVCC

VDDA

P7

P9

P9

P10

L513

Q503F503L504

L520 P11

+DVDDP9

L519

+2.5V_DDR

L518VDDZCMP

L22CBVDDA

+DDRVREFR95

R557

DDRVREFBR616

L24CBVDD

ZVREF

P7

DACAVDD1,2

SVDDZCMP

IDEAVDD

SZVREF

P7

P7

P7

P14

L514

L524

L38

R109

DDRVREFA

P14

P14

P12

P11

P11

P7R613

+1.8VSP24

P24

From last page From last page

From last page

Main Voltage Map

125



PF501PL501

120Z/100M

PD501RLZ24D

J2+DVMAIN

PD514

POWER IN

PC5010.1µ

PC5020.1µ

PL508120Z/100M

JS501

S D

23

1678

5

G PU502SI4835DY

JO502

PR507470K

ALWAYSPD503

PD504

ADINP

PR508100K

PQ5012N7002

PR5091M

LEARNING

PD505

PD506

PR5164.7K

PC5180.1µ

PC5231000P

F504

ALWAYS

8 IN

F/B

5VTAP

SHUTDNGND

7

6

34

OUT

SENSE

1

2

U506LP2951-02BM

P27

+5V

D508RLZ5.6B

D S

G

Q509SI2301DS

+5VA

SW_+5VA

C6994.7µ R621

100K

DS

G

Q511SI2301DS

Q510DTC144WK

R61810K

H8_AVREF1

C69810µ

D516UDZ5.6B

-SW_+5VA

From H8

To H8

Step1 : Connect Adaptor to ( D/D BD ) J2 & O/P “ALWAYS”.

Step2 : “ALWAYS” --> U506 Generate +5VA.

Step3 : H8 O/P “LEARNING” for Charger Circuitry.

Step4 : For MOSFET “PU502” G=0,D<-->S.

Step5 : O/P “ADINP”& “+DVMAIN”.

VCC

RS+/-

+VDD5S

PC40.1µ

3

4,5

OUT 6

PC51µ

PR310

I_LIMT

P2

MAX4173FEUT-T

PU1

45

47

R6742.2K

U509

MicroControllerH8/F3437

P2281

39

Mother Board

PJ2 J7

P27P2

SW502

+5VA

4R7181K

C7990.01µ

R724100K

1

-H8_R

ESE

T

RESET

VCC

MN

P22

3

2

R72510K

U515

D/D Board

126


ADINP

PL5120Z/100M

PC130.01µ

PD3EC31QS04

PR54447K

PQ5072N7002G

S

D

PQ506DTC144WK

PC5690.1µ

PL501

BATT

PD511RLZ20C

PU9ASI4925DY

2

187

PU9BSI4925DY

4

356

PR15100K

PR1633k

PQ42N7002 LI_OVP

PD7BAS32L

PR3100K

PD4EC31QS04

4

G

S D

23

1678

5

PR44.7K

PQ1SI4835DY

PL633UH

PR720K

PR9487K

PR1013.7k

PR8976K

1

65 From H8

VCC

OUTPUTCTRL

C1,C2

8,11

REF2IN-

DTC 4FEEDBACK

PR541100K

3

1IN-

2IN+ 16

2

2N+

PU511

PWM

TL594C

8.1 No Power – Battery ChargeWhen the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

PC1410µ

PC5670.01µ

PC15100µ

PR144.7K

PQ3MMBT2222A

+

_

PR560130K

+5VASPR562100K

1.25V 3

2

PR55814K

PC5810.1µ

LI_OVP

3

42

PQ2BNDC7002N

PQ2ANDC7002N

D/VADJ1

PR61M

PR51M

From H8

D/VADJ2

PR5451M

PC573150P

CHARGING

From H8

2IN+12

13

14

5

6

CT

RT

PR54010K

PC5681000P

PC5750.01µ PC566

1µ

PC5750.01µ

PR5436.19K

PR5462.49K

JS1

PR547249K CHARGE_I_CTR

From H8

PU514ALMV393M

1

84

+

_

PR556681K

+5VASPR559100K

1.25V 5

6

PR557100K

C8980.1µ

BATT_DEAD

PU514ALMV393M

7

84

VMAIN

PC5800.1µ

+5VAS

PR5614.7K

PQ510SCK431LCSK-5

To H8

12.30V

12.40V

12.50V

12.60V

VADJ_2_P

0

0

1

1

VADJ_1_P

0

1

0

1

BAT_TYPE

0

0

0

0

NIMH_CELL

0

0

0

0

P25

PR54210K

PC5700.1µ

Mother Board

To next page

PC381000P

PC391000P

127


8.1 No Power – Battery DischargeWhen the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

G

SD

23

1678

5

PU513SI4835DY

BATT

G

SD

23

1678

5

PU512SI4835DY

BATT1

PR553100K

R6551M

PQ5082N7002

PQ509DTC144WK

PR551226K

ADINP

-ADEN

PC5791000P

PC5780.01µ

VMAIN

PR564301K

PL505120Z/100M

PL504120Z/100M

PF502

1,2

PC5830.01µ

PC5841000P

PC5820.1µ

PR563100K

U509

Micro

Controller

H8/F3437

P22

PC190.1µ

PR1220K

+5VAS

PR114.99K

+5VA

BAT_V

BAT_T

R6722.2K

R67122

BAT_VOLT

BAT_TEMP

2 1

3

C7370.1µ

C7360.1µ

D511BAV70LT1

C70768P

C71068P

X50316MHZ

38

42

3

2

47-ADEN

+5VA H8_AVREF1

C7080.1µ

C7090.1µ

C7280.1µ

4,9,59 36,37

J14

3

Battery C

onnector

P23

C7310.1µ

PR55233K

Mother Board

128


DS

G

DS

G

DS

G

PU6FDD6676

PU4FDD6676

PU5FDD6672A

PD503EC31QS04

DS

G

DS

G

PD505EC10QS04

PC5380.1µ

PU516FDD6676

PU502FDD6676

PC5170.1µ

DS

G

DS

G

DS

G

PL11.2UH

PR502.005

PU1FDD6676

PU2FDD6676

PU3FDD6672A

PD501EC31QS04

DS

G

DS

G

PD504EC10QS04

PC5290.1µ

PU515FDD6676

PU501FDD6676

PC5160.1µ

PU508

CPU_COREGenerator

LTC3716

SW2

8.1 No Power – Select CPU ModelWhen the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

DPRSLPVR

+5VA

PR320

PR5900

PD6BAS32L

PR6021M

PQ5192N7002

PQ5202N7002

PR6021M

PR2926.7K

PQ5182N7002

PR23750K

PR2226.7K

PR27100K

VID1

MOBO/DT#

From U1 CPU

PR210

PD516EC31QS04

PD515EC31QS04

PR2120K

PQ102N7002

DT/MOBO#

VID2

VID3

PQ62N7002

PQ82N7002

W/N#PR351M

1234

PR262M

PR342M

8765

+5VA

X X

SW6

DT/MOBO#

PR5145.1

VIN23

INTVCC29

35

33TG1

BOOST1

SW1

BG1

34

31

24

26TG2

BOOST2

BG2

25

27

+VCC_CORE

PL502120Z/100M

PL501120Z/100M

Core_InVMAIN

INTVCC_3

PC541470P

4,15

16,10

PQ5132N7002

JO35

PQ5142N7002

JO36

JO34

DT/MOBO#PQ92N7002

PR20187K

11VOS-

PR58120K

JO511

PR5112.2K

PR51310K

INTVCC_3

P26

PR5720

PGOOD36

PR51843.2K INTVCC_3

PC5250.22µ

PC5361000P

PR52222K

PC5341000P

PR51918.2K

VID0_P

VID[1:4]From U1 CPU

18-21

17

H_PWRGD

From page 7 in M/B circuit

1

8

RUN/SS

VSS_SENSE

From U14 SiS961

PQ72N7002

From U1 CPU

VCC_SENSE

ON

OFF

OFF

W/N#

ON

ON

OFF

DT/MOBO#

OFF

OFF

ON

MOBO/DT#

Willamette

Mobile

Northwood

PL21.2UH

PR504.005

CPU Model Select table

129


8.2 No Display

No Display

Replace monitoror LCD. Board-level

Troubleshooting

Yes

NoMonitoror LCD module

OK?

SystemBIOS writes

error code to port378H?

Yes

No

Refer to port 378Herror code descriptionsection to find out which part is causing the problem.

Make sure that CPU module,DIMM memory are installedProperly.

DisplayOK?

Yes

No

Correct it.

To be continuedClock and reset checking

Check system clock and reset circuit.

ReplaceMotherboard

1.Try another known good CPU module, DIMM module and BIOS.

2.Remove all of I/O device (FDD,HDD, CD-ROM…….) frommotherboard except LCD or monitor.

DisplayOK?

1. Replace faulty part.2. Connect the I/O device to the

M/B one at a time to find outwhich part is causing the problem.

Yes

No

There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.

130


U508

ClockGenerator

ICS952001

P11

8.2 No Display****** System Clock Check ******

U1CPU

Pentium 4

40

39

U4

IGUI Host/Memory

ControllerSiS650

U511Super I/OPC87393

HCLK_CPUR644 33

R648 33

R641 22

R661 22

R632 22

R630 33

R635 33

R639 33

FS0

9

31

47

2

44

43

ZCLK0

AGP_CLK

SDRAMCLK

REFCLK0

HCLK_SIS650

HCLK_SIS650#

R670 22

R656 33

27

15

CLK_SIO

CLK_LPC33

20

8

P4

P6 P7

P21

7

6

X50214.318MHz

C70210P

C70110P

HCLK_CPU#

R64549.9

R64949.9

R63649.9

R64049.9

R633 33

R625 33

R646 22

R667 33

R668 33

FS1

45

3

10

26

14

CPU_STP#

REFCLK1

REFCLK3

ZCLK1

USBCLK_SB

CLK_SBPCIFS3

+3VS

+3VS

R6244.7K

R87510K

R6264.7K

D520

U14

MuTIOLMedia I/OController

SiS961

P14 P15 P16

FS4

R660 33

R756 33

R755 33

17

23

21

CLK_CARDPCI

CLK_MINIPCI

CLK_1394PCI

R8333

4 FS2 14.318MHZ_TV

R5650 MOD_XOUT To U504

SiS301LV/Chrontel CH7019

To U6PCMCIA Controller

To J509MINI PCI Socket

To U18IEEE1394 Controller

P9

P18

P28

P29

+3VS L17 120Z/100M

L19 120Z/100M

L20 120Z/100M

L23 120Z/100M

VDDZ

VDDPCI

VDDA48

1

11

VDDREF

13,19

28

L21 120Z/100M

L18 120Z/100M

L16 120Z/100M

VDDAGP

VDDCPU

VDDSD

29

42

48

+3VS

R66410K

+3VS

R67310K

+VCC_CORE

R67810K

Q517MMBT3904L

Q516MMBT3904L

33PD#/VTT_PWRGD

+3VS

C7181000P

C7190.1µ

C7150.1µ

L520300Z/100M

36

37

324

1

FWDSDCLKO

To next page

131


U9

ClockBuffer

ICS93722

P11

CLK_DDR0

CLK_DDR0#

CLK_DDR1

CLK_DDR1#

CLK_DDR2

CLK_DDR2#

CLK_DDR3

CLK8_DDR3#

CLK_DDR4

CLK_DDR4#

CLK_DDR5

CLK_DDR5#

R90

R91

R89

R88

R94

R93

0

0

0

0

0

0

R98

R97

R100

R101

R102

R102

0

0

0

0

0

0

2

1

4

5

13

14

19

17

16

24

25

26

27

J505P12

P12

L24600Z/100M

+2.5V_DDR

C1100.1µ

3,12,23

8.2 No Display****** System Clock Check ******

Bit 7FS3

0000000011111111

Bit 6FS2

0000111100001111

Bit 4FS1

0011001100110011

Bit 5FS0

0101010101010101

CPU(MHz)

66.7100.00100.00100.00100.00100.00100.00100.00100.00100.00 100.0080.0080.0095.0095.0066.67

SDRAM(MHz)

66.67100.00200.00133.33150.00125.00160.00133.33200.00166.67166.67133.33133.3395.00126.6766.67

ZCLK(MHz)

66.6766.6766.6766.6760.0062.5066.6780.0066.6762.5071.4366.6766.6763.3363.3350.00

AGP(MHz)

66.6766.6766.6766.6760.0062.5066.6766.6766.6762.5083.3366.6766.6763.3363.3350.00

Bit 2FS4

0000000000000000

C1500.1µ

C1120.1µ

C9910µ

C1011000P

C1110.1µ

L22300Z/100M

+2.5V_DDR

10VDDA

VDD[0:2]

FWDSDCLKO

CBVDDA

CBVDD

8CLK_INT

C19610P

20 BF_OUT

R9922

FBINT

FB_OUTT

J506

From previous page

132


8.2 No Display****** Power Good & Reset Circuit Check ******

P24 P26

PU510PU508

8575APower

Module

U502MIC5248

+5VS

R51710K

U1

CPU

Pentium 4

P4

CPU_CORE_EN

VCCPVID

PG

OUT

4

5

INEN

+5VS

1,3

C5140.1µ

R8940

C5131µ

P5

U4

IGUI Host/Memory

ControllerSiS650

P6 P7

+VCC_CORE

R12301

CPURST#

CPUPWRGD

R51251

-PCIRST

U14


SiS961

P14 P15

-PCIRST

U2MAX809

RESET# 2VCC

+3VS

3

C2230.1µ

R145100K

P7

U509


P22

SW502

+5VA

4R7181K

C7990.01µ

3

R72510K

VCC

MN

RESET

U515

P22

R724100K

-H8_RESET1 1

H8_PWRON 49

R6821KPWR_ON

R67920K

C73210P

+3V

R66510K

SIS_PWRBTN Q515DTC144WK

SIS_PWRBTN#

91

R7051K

D513RLS4148

+3V

C78222µ

R706100K

AUXOK

AUXOK

PWROK

PWROK

PWROK

H8_PWROK 68

H_PWRGDD14

RLS4148

D15RLS4148

CPU_CORE_EN

Q19DTC144TKA

+5VS

R21510K

R1

R1

R21410K

Q18DTC144TKA

IDE_RST# 1

5

P17

P17

J19

J12

Primary EIDEConnector

Secondary EIDE Connector

-PCIRST

AC97_RST#

To I/O devices

U504SiS301LV

Chrotel/CH7019

U6PCMCIAController

U511LPC

Super I/O

J509MINI PCI

Socket

U18IEEE 1394Controller

P9 P29P28P21P18

J18MDC

P19

U15Audio Codec

P20

133


Replace faultyLCD or monitor.

Check if U504, J3 are cold

solder?

VGA Controller FailureLCD No Display

1. Confirm LCD panel or monitor is good and check the cable are connected properly.

2. Try another known good monitor or LCD module.

DisplayOK?

Remove all the I/O device & cable from motherboard except LCD panel or extended monitor.

DisplayOK?

Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem.

Yes

No

Yes

No

Re-soldering.

One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement.

Parts: Signals:

TX2OUT[0:2]+TX2OUT[0:2]-BLADJKH8_ENABKL-LID


ReplaceMotherboard

Yes

No

U4U504U509J3J7PJ2J6Q503F503L504Q2

R828R829R830L514L512L513L515SW1R511

+3VSLCDVCCENAVDDPID[0:2]TXCLK+TXCLK-TX2CLK+TX2CLK-TXOUT[0:2]+TXOUT[0:2]-

8.3 VGA Controller Failure LCD No DisplayThere is no display or picture abnormal on LCD although power-on-self-test is passed.

134


S

D

23

1678

5

G

Q503NDS9410

F503mircoSMDC110

L504120Z/100M

C5060.1µ

R1

+12VS

LCD

C5130.1µ

C5120.1µ

L514

L512

L513

L515

+5V

Inverter Board

J6

J7 PJ2

DC Power Board

LCDVCC

+3VS

InverterQ2

DTC144TKAC5060.1µ

C5100.1µ

C5091000P

C30.1µ

C21000PR505

470K

8.3 VGA Controller Failure LCD No DisplayThere is no display or picture abnormal on LCD although power-on-self-test is passed.

U4

IGUI Host/Memory

Controller

SiS650

P7

ENAVDD 127

TXCLK+

TXCLK-

TX2CLK+

TX2CLK-

TXOUT [0:2]+

TXOUT [0:2]-

TX2OUT [0:2]+

TX2OUT [0:2]-

24

25

5

6

33,30,27

34,31,28

17,14,11

18,15,12

U504

SiS301LV/Chrontel

CH7019

R828 0

R829 0

R830 0

PID0

PID1

PID2

LCD_ID0

LCD_ID1

LCD_ID2

RP11K*4

+3VS

1,2

J3

LCD

Connector

8

10

7

9

22,28,27

20,26,25

15,16,21

13,14,19

32,34,36

P10

+5VS

2,3

11

4

1

5,6

P2

BLADJ

ENPBLT1

8

7

U509


BLADJ

H8_ENABKL

45

17 ENABKL

ENABKL 128

R74100

4 3 2 1

5 6 7 8X

X

RP4010K*4

P22

P9

P27 P2

SW1R5111K

-LID49-LID48

C5222.2µ

+5VA

C7142.2µ

R64210K

Cover SwitchSignal

-LID

HI

Normal

LOW

Suspend

DISPLAYUNIQACHYUNDAIHANNSTARCMO

LCD_ID01010

LCD_ID20001

LCD_ID10110

31

33

35

135


8.4 External Monitor No DisplayThere is no display or picture abnormal on CRT monitor, but it is OK for LCD.

DisplayOK?

External Monitor No Display

1. Confirm monitor is good and checkthe cable are connected properly.

2. Try another known good monitor.

Remove all the I/O device & cable from motherboard except monitor.

DisplayOK?

Replace faulty monitor.

Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem.

Yes

No

Yes

No

YesRe-soldering.

No

One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement.

Parts:

U4U14U508J2R1R566R546R547R548

Signals:

Check if U4, J2

are cold solder?

CRT_IN#REFCLK0CRT_DDDACRT_HSYNCCRT_VSYNCCRT_DDCKCRT_REDCRT_GREENCRT_BLUE

Q505Q502Q501Q506FA501L503L502L501


ReplaceMotherboard

136


8.4 External Monitor No DisplayThere is no display or picture abnormal on CRT monitor, but it is OK for LCD.

Q5062N7002

G

S D

U4

IGUI Host/Memory

Controller

SiS650

P7

CRT_DDDA

CRT_HSYNC

CRT_VSYNC

CRT_DDCK

R566100

R54633

R54733

R548100

Q5012N7002

G

S D

Q5022N7002

G

S D

Q5052N7002

G

S D

R5522.2K

R5582.2K

+3VS

+3VS

CRT_RED

CRT_GREEN

CRT_BLUE

L503 120Z/100M

L502 120Z/100M

L501 120Z/100M

4 3 2 1

5 6 7 8X

X

RP50275*4

4 3 2 1

5 6 7 8

CP50122P*4

4 3 2 1

5 6 7 8X

X

CP50222P*4

J2

P10

External VG

A C

onnector

JL1

JL501

VVBWN

VCOMP

C6000.1µ

C5930.1µ

DACAVDD1,2

C5830.1µ

C5841µ

+1.8VS

C56110µ

L514120Z/100M

JL509DACAVSS1,2

VRSET

R545130

FA501120OHM/100MHZ

C11000P

+3VS

R21KR1

1KCRT_IN#To U14 SiS961

P155

12

13

14

15

1

2

3

6,7,8,10

REFCLK0

From U508 Clock Gen.

P11

137


8.5 Memory Test ErrorExtend DDR SDRAM is failure or system hangs up.

Memory Test Error

One of the following components or signals on the motherboard may be defective ,Use an oscilloscope to check the signals or replace the parts one at A time and test after each replacement.

TestOK?

Yes

No

Parts:U4U508U9J505J506RP8~RP12RP13~RP15RP16~RP20R632R614R658R662R98R100R102R97R101R103

Signals:

1.If your system installed with expansionSO-DIMM module then check them forproper installation.

2.Make sure that your SO-DIMM socketsare OK.

3.Then try another known good SO-DIMMmodules.

If your system host bus clock running at 266MHZ then make sure that SO-DIMM module meet require of PC 266.

TestOk?

Replace the faulty DDR SDRAM module.

Yes

No

+2.5V_DDR+DDRVREFCKE[0:3]DDR_DQM[0:7]DDR_MD[0:63]DDR_BA [0,1]DDR_CS[0:3]#DDR_MA[0:12]DDR_DQS[0:7]DDR_RAS#DDR_CAS#DDR_WE#SDRAMCLKFWDSDCLKSMBDATASMBCLKCLK_DDR[0:5]CLK_DDR[0:5]#


ReplaceMotherboard

R90R91R98R88R94R93

Replace the faulty DDR SDRAM module.

138


+3VSL516

120Z/100M

C6230.01µ

DDRAVDD

DDRAVSS

C6240.1µ

C63210µ

JL507

U4

IGUI Host/Memory

Controller

SiS650

8.5 Memory Test ErrorExtend DDR SDRAM is failure or system hangs up.

RP7470

+2.5V_DDR

CKE [0:3]

DDR_DQM [0:7]

DDR_MD [0:63]

DDR_MA [0:12], DDR_DQS [0:7]

DDR_RAS#, DDR_CAS#, DDR_WE#

RP8~RP12 10*8 RP13~RP15 0*8RP16~RP20 10*8

RP21~RP3333*8

MD [0:63]

MA [0:12], DQS [0:7]

BA [0,1], CS [0:3]#

RAS#, CAS#, WE#

DQM [0:7]

+1.25V

U508

Clock Gen.ICS952001

U9

Clock BufferICS93722

R613150

DDRVREFA

+2.5V_DDR

C6890.01µ

R612150

C6880.01µ

R616150

DDRVREFB

+2.5V_DDR

C6920.01µ

R615150

C6930.01µ

+3VS

R5994.7K

DRAM_SEL

SDRAMCLK

FWDSDCLKO

R61422

8

47

R63222

SMBDATA

SMBCLK

R65833

R66233

35

34

7

22

2,1,4,5,13,14,17,16,24~27 CLK_DDR [3:5] , CLK_DDR [3:5]#

CLK_DDR [0:2] , CLK_DDR [0:2]#

CKE 0,1

CKE 2,3

CS [0,1]#

CS [2,3]#

R90,R89,R94R91,R88,R93

0

R98,R100,R102R97,R101,R103

0

DDR_BA [0,1], DDR_CS [0:3]#

R8364.7K

R8374.7K

+3VS

SMBDATA

SMBCLK

P11

P11

P7

J505

J506

P12

P12

+DDRREF

+2.5V_DDR

R951K

+2.5V_DDR

R5561K

+DDRVREF

From U14 SiS961

P15

DD

R SO

DIM

MD

DR

SOD

IMM

CLK_DDR [0:5] , CLK_DDR [0:5]#

139


8.6 Keyboard (K/B) Touch-Pad (T/P) Test ErrorError message of keyboard or touch-pad failure is shown or any key does not work.

Keyboard or Touch-PadTest Error

Try another known good Keyboard or Touch-pad.

TestOk?

Replace the faulty Keyboard or Touch-Pad

Yes

No

CheckU509, J13, J20for cold solder?

One of the following parts or signals on the motherboardmay be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement.

Yes

No

Re-soldering

Parts

U511U11U509J13J20L521R146R690F1L29

Signals

+5VAH8_AVREF1+3VS+5V-ROMCS-MCCSKI[0:7]KO[0:15]T_CLK_H8T_DATA

Yes

NoCorrect it.

Is K/B orT/P cable connected to

notebookproperly?


ReplaceMotherboard

KBD_US/JP#SA2IRQ1IRQ12-IOR-IOW

L33L31SW503RP48

140


8.6 Keyboard (K/B) Touch-Pad (T/P) Test ErrorError message of keyboard or touch-pad failure is shown or any key does not work.

U509

MicroController

H8/F3437

P22

L29 120Z/100M

L31 120Z/100M

L33 120Z/100M

F10.25A

+5V

T_CLK_H8

T_DATA

RP480

KO 0,1

KI 0,5

KI [0:7]

KO [0:15]

5,6

7,8

1

2

3

C22247P

C22847P

C2210.1µ

4

U511

LPCSuper I/O

PC87393

P21

23

18

T_CLK

17~24

1~16

Internal Keyboard Connector

Touch-pad

Leve

l Shi

ft-ROMCS72

R2454.7K

R1460

8

+3VS

-MCCS73

R6900

14

9

15

R13810K

+5VA

-H8_KBCS

-H8_MCCS

R12510K

95

98

VCC1,2,B

L521120Z/100M

U11

P21

P22

J20

J13

H8_AVREF1

C7090.1µ

C7310.1µ

C7080.1µ

C7280.1µ37,369,59,4

+5VA

AVCCAVREF

KBD_US/JP#19

R737100K

+3VS

SW5031

2

4

3XR74410K

SA293

87 IRQ1

86 IRQ12

83

82

-IOR

-IOW

93

53

54

96

82-IOW_H8

RP480

141


Hard Driver Test Error

One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement.

Yes

No

Re-bootOK? Replace the faulty parts.

1. Check if BIOS setup is OK?.2. Try another working drive and cable.

Check the system driver for proper installation.

No

Re - TestOK?

EndYes


ReplaceMotherboard

8.7 Hard Drive Test ErrorEither an error message is shown, or the drive motor spins non-stop, while reading data from or writingdata to hard disk.

Parts: Signals:

U14J12R215Q19Q18R214JS6JS7R202RP42RP45R781

+5VS+5VS_HDD-PCIRSTIDE_PIORDYIDE_PDD[0:15]IDE_PDA[0:2]IDE_PDCS3#IDE_PDCS1#IDE_PDIOR#IDE_PDIOW#IDE_PDDACK#IDE_PDDREQIDE_IRQ14

R212R213R211R205R210

142


-PCIRST Q19DTC144TKA

IDE_RST#

JS5

C2734.7µ

C2580.1µ

+5VS

41, 42

1

IDE_PDA[0:2], IDE_PDCS3#

U14


SiS961

P14

IDE_PDD[0:15]

IDE_PDIOR#

IDE_PDIOW#

IDE_PDDACK#

IDE_PDCS1#

IDE_PDDREQ

IDE_IRQ14

IDE_PIORDY

+5VS

R1444.7K

+5VS 39

R200470

D19PG1102W

R781 33

RP42, PR4510*8

J19

P17

27

2~18

33,35,36,38

25

23

29

37

21

31

+5VS

R21510K

R1

R1

R21410K

Q18DTC144TKA

RP528 33*4

R212 10

R213 22

R211 22

R205 82

R210 82

PDD[0:15]

PDA[0:2], PDCS3#

PDIOR#

PDIOW#

PDDACK#

PDCS1#

PDDREQ

IRQ14

PIORDY

Primary ED

IE Connector

C2610.1µ

+5VS_HDDJS4

R202 10

8.7 Hard Drive Test ErrorEither an error message is shown, or the drive motor spins non-stop, while reading data from or writingdata to hard disk.

143


8.8 CD-ROM Drive Test ErrorAn error message is shown when reading data from CD-ROM drive.

CD-ROM Driver Test Error


Yes

No

Parts: Signals:TestOK?

Replace the faulty parts.

1. Try another known good compact disk.2. Check install for correctly.

Check the CD-ROM driver for proper installation.

No

Re - TestOK?

End

U14J12R215Q19Q18R214JS6JS7R204RP41RP44RP43

Yes


ReplaceMotherboard

+5VS+5VS_CD-PCIRSTIDE_SIORDYIDE_SDD[0:15]IDE_SDA[0:2]IDE_SDCS3#IDE_SDCS1#IDE_SDIOR#IDE_SDIOW#IDE_SDDACK#IDE_SDDREQIDE_IRQ15

R208R176R203R170R207R777

144


8.8 CD-ROM Drive Test ErrorAn error message is shown when reading data from CD-ROM drive.

-PCIRST Q19DTC144TKA

IDE_RST#

JS7

C740.1µ

C6430.1µ

+5VS

38~42

5

IDE_SDA[0:2], IDE_SDCS3#

U14


SiS961

P14

IDE_SDD[0:15]

IDE_SDIOR#

IDE_SDIOW#

IDE_SDDACK#

IDE_SDCS1#

IDE_SDDREQ

IDE_IRQ15

IDE_SIORDY

+5VS

R734.7K

+5VS 37

R743470

D18PG1102W

R208 33

RP41, PR4410*8

J12

P17

27

7~21

31,33,34.36

24

25

28

35

22

29

+5VS

R21510K

R1

R1

R21410K

Q18DTC144TKA

RP43 33*4

R176 10

R203 22

R170 22

R207 82

R777 82

SDD[0:15]

SDA[0:2], SDCS3#

SDIOR#

SDIOW#

SDDACK#

SDCS1#

SDDREQ

IRQ15

SIORDY

Secondary EDIE C

onnector

C6484.7µ

+5VS_CDJS6

R204 10

145


8.9 USB Test ErrorAn error occurs when a USB I/O device is installed.

USB Test Error

Check if the USB device is installed properly. (Including charge board.)

Re-testOK?

No

Yes

No

YesCorrect it

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a timeand test after each replacement.

Signals:

Replace another known good charge board or good USB device.


ReplaceMotherboard

Correct it

TestOK?

+3V

USBCLK_SB

-USBOC0_1

USBP0+

USBP0-

USB0VCC5

USBP1+

USBP1-

-USBOC3_5

USBP5+

USBP5-

USB5VCC5

USBP3+

USBP3-

Parts:

U14J7R147R148R75R518R142R143R161R163

PJ2JU3J5J7D504L524L509L516L518

M/B D/D

U1J8J4D3L520L522L504L508

146


4 3

21

R50415K

R50515K

USBP0+

USBP0-

4 3

21

R50815K

R50915K

USBP1+

USBP1-

8.9 USB Test Error - 1An error occurs when a USB I/O device is installed.

U14


SiS961

P16

C86100P

USBP0_P

USBP0_N

C8722P

C122100P

USBP1_P

USBP1_N

C12122P

C83100P

USBP3_P

USBP3_N

C8422P

C126100P

USBP5_P

USBP5_N

C12522P

R14722

R14822

USBP0+

USBP0-

R7522

R15822

USBP1+

USBP1-

R14222

R14322

USBP3+

USBP3-

R16122

R16322

USBP5+

USBP5-

+3VL523

120Z/100M

C7440.1µ

USBVDD

USBVSS

C7451µ

C74310µ

USBCLK_SBFrom U508 clock generator

USB_OC0_1#

USB_OC3_5#OC0,1#

OC3,5#

50

48

32

34

26

28

14

16

1

3

J7 PJ2P27

+3V

R51610K

3

2

1

-USBOC0_1R50633K

R51847K

C5341000P

L524120Z/100M

C5060.1µ

R333K

R547K

C91000P

L516120Z/100M

C5170.1µ

VIN0

VIN1

3

4

+5V

C101µ

C81µ

VOUT1

VOUT0U3

P25

1

USB0VCC5

-USBOC0

-USBOC1

D504BAW56

USB0VCC5

-USBOC1

L509600Z/100M

L518600Z/100M

1

3

2

4

GND

1

3

2

GNDJO512

4

GND_USB

GND_USB

DC Power Board

P2

P2

P2

J5

J7

R8880

R8860

USBP_0+

USBP_0-

R8890

R8870

USBP_1+

USBP_1-

R8930

R8910

USBP_3+

USBP_3-

R8920

R8900

USBP_5+

USBP_5-

147


4 3

21

R51315K

R51415K

USBP5+

USBP5-

4 3

21

R50315K

R50215K

USBP3+

USBP3-

8.9 USB Test Error - 2An error occurs when a USB I/O device is installed.

50

48

32

34

26

28

14

16

1

3

J7 PJ2P27

+3V

R1010K

3

2

1

-USBOC3_5R7

33K

R847K

C111000P

L520120Z/100M

C5250.1µ

R233K

R447K

C11000P

L504120Z/100M

C5040.1µ

VIN0

VIN1

3

4

+5V

C5091µ

C31µ

VOUT1

VOUT0U1

P35

1

-USBOC5

-USBOC3

D3BAW56

USB5VCC5

-USBOC3

L522600Z/100M

L508600Z/100M

1

3

2

4

GND

1

3

2

GNDJO501

4

GND_USB

GND_USB

DC Power Board

P2

P3

P3

J8

J4

USB5VC5

U14


SiS961

P16

C86100P

USBP0_P

USBP0_N

C8722P

C122100P

USBP1_P

USBP1_N

C12122P

C83100P

USBP3_P

USBP3_N

C8422P

C126100P

USBP5_P

USBP5_N

C12522P

R14722

R14822

USBP0+

USBP0-

R7522

R15822

USBP1+

USBP1-

R14222

R14322

USBP3+

USBP3-

R16122

R16322

USBP5+

USBP5-

+3VL523

120Z/100M

C7440.1µ

USBVDD

USBVSS

C7451µ

C74310µ

USBCLK_SBFrom U508 clock generator

USB_OC0_1#

USB_OC3_5#OC0,1#

OC3,5#

R8880

R8860

USBP_0+

USBP_0-

R8890

R8870

USBP_1+

USBP_1-

R8930

R8910

USBP_3+

USBP_3-

R8920

R8900

USBP_5+

USBP_5-

148


8.10 PIO Port Test ErrorWhen a print command is issued, printer prints nothing or garbage.


Yes

No

Parts: Signals:TestOK?

Replace thefaulty parts.

1. Check if PIO device is installed properly. (J504)

2. Check CMOS LPT port setting properly.

Try another known goodPIO device.

No

Re - TestOK?

EndYes


Correct it

ReplaceMotherboard

PIO Port Test Error

Yes

No

U511J7RP501RP503RP504RP505R501CP503CP504CP505CP506C504

PJ2U501U502J3RP1RP2R1RP3RP4D1

+5VSP_LPD0P_LPD1P_LPD2P_LPD3P_LPD4P_LPD5P_LPD6P_LPD7

-P_STB-P_AFD-P_ERR-P_INIT-P_SLIN-P_ACKP_BUSYP_PEP_SLCT

M/B D/D

149


8.10 PIO Port Test Error

P_LPD [0:3]

P_LPD [4:7]

P_SLCT, -P_STB

-P_AFD, -P_ERR

-P_INIT, -P_SLIN

-P_ACK, P_BUSY

P_PE DP_PE

RP5010*4

RP5030*4

RP5040*4

RP5050*4

R5010

CP50322P*4

CP50422P*4

CP50522P*4

CP50622P*4

C50422P

Mother Board J7

DP_LPD [0:3]

DP_LPD [4:7]

DP_SLCT, -DP_STB

-DP_AFD, -DP_ERR

-DP_INIT, -DP_SLIN

-DP_ACK, DP_BUSY

STB#

AFD#

LPD0

ERR#

LPD1

INIT#

LPD2

SLIN#

LPD3

-P_STB

-P_AFD

P_LPD0

-P_ERR

P_LPD1

-P_INIT

P_LPD2

-P_SLIN

P_LPD3

-P_ACK

P_BUSY

P_PE

P_SLCT

P_LPD4

P_LPD5

P_LPD6

P_LPD7

8

7

6

5

1

2

3

4

8

7

6

5

1

2

3

4

RP10*4

RP20*4

R10

8

7

6

5

1

2

3

4

8

7

6

5

1

2

3

4

RP30*4

RP40*4

-PP_STB

-PP_AFD

P_LPD0

-PP_ERR

PP_LPD1

-PP_INIT

PP_LPD2

-PP_SLIN

PP_LPD3

-PP_ACK

PP_BUSY

PP_PE

PP_SLCT

PP_LPD4

PP_LPD5

PP_LPD6

PP_LPD7

X X

+5VS

D501BAS32L

Parallel Port Connector

J3PJ2

U501PAC128401Q

U502PAC128401Q

ACK#

BUSY

PE

SLCT

LPD4

LPD5

LPD6

LPD7

12

11

10

9

8

7

6

5

4

321

13

14

15

16

17

18

19

20

21

222324

12

11

10

9

8

7

6

5

4

321

13

14

15

16

17

18

19

20

21

222324

1

14

2

15

3

16

4

17

5

6

7

8

9

10

11

12

13

GND_IO2

18-27

GND_IO2 GND_IO2

25

23

43

21

41

19

39

17

37

35

33

31

29

36

34

32

27

U511

LPCSuper I/O

PC87393

P3

P3

P3

P2

P21

P27

+3VSVDD[0:3]

When a print command is issued, printer prints nothing or garbage.

150


8.11 Audio FailureNo sound from speaker after audio driver is installed.

Test OK?

Audio Failure

1. Check if speaker cables are connectedproperly.

2. Make sure all the drivers are installed properly.

1.Try another known good speaker,CD-ROM.

2. Exchange another known goodcharger board.

Re-test OK?


ReplaceMotherboard

YesCorrect it.

Correct it.Yes

Check the following parts for cold solder or one of the following parts on the motherboard may be defective,use an oscilloscope to check the following signal or replace parts one at a time and test after each replacement.

1.If no sound causeof line out, check the following parts & signals:

2. If no sound cause of MIC, check the following

parts & signals:

3. If no sound causeof CD-ROM, checkthe following

parts & signals:

No

NoParts:

U14U15U16VR1L529L28L530Q528Q529J24

Signals:

AOUT_RAOUT_L+3VS5V_AMP+3VS_SPDSPK_OFFSPDIFOUT

Parts:

U14U15J21J28C272L531L532

Signals:

+5VSAVDDADMIC1

Parts:

U14U15J12R187R185R186

Signals:

CDROM_LEFTCDROM_RIGHTCDROM_COMM

151



U15

Audio Codec

ALC201

AVDDADR7282.7K

C7882.2µ

R7272.2K

C2721µ

21 MIC

C798220P

L531600Z/100M

ExternalMIC

12453

L535600Z/100M

L532600Z/100M

1

2

J28

J21Internal

MIC

U14


SiS961

U6

PCI1410GU

C7770.1µ

C7710.1µ

SB_SPKR

R697470K

R69820K

U513-CARDSPK

12 PC_BEEP

SPK_OFF#To next page

AUDIO IN

AC97_SYNC

AC97_RST#

AC97_SDOUT

AC97_SDIN

AC97_BITCLK

8

5

10

11

1

2

3

4

C1200.1µ

C78410µ

AVDDADL554

120Z/100M

+5VS

DVDD1,2

AVDD1,225,38

To next page36

35

AOUT_R

AOUT_L

P20

P15

P18

R15422

6

R764 22

R699 22

5

R70310K

R70010K

AVDDAD

R1501M

2

3

C22710P

C24610P

X324.576MHZ

JS505

C1170.1µ

C8810µ

L553120Z/100M

+3VS 1,9

C1160.1µ

C8011µ

R7392.7K

MIC_VREF

C11847P

MIC_3MIC_2MIC1

C2740.1µ

C2600.1µ

23

24

LINE/IN/L

LINE/IN/R

C2711µ

R1730

R1650

22 MIC2

C2640.1µ

C2691µ

20

18

19C270

1µ

CDROM_RIGHT

CDROM_LEFT

CDROM_COMM

J12

CDROMCONN

2

1

3

P17

R1876.8K

R1856.8K

R1866.8K

R193100K

R191100K

R192100K

R1410

L34

L35

L40

L545

L546

120Z/100M

120Z/100M

120Z/100M

120Z/100M

120Z/100M

AGND

L547 120Z/100M

SPDIFOUT48

AGNDAGNDAGNDAGND

AGND AGND AGND

AGND AGND AGND

AGND AGND CAGND

AGND AGND

152



1

2

3

6

5

4 7

VR110K

C8032.2µ

C8042.2µ

R73110K

R73210K

R72010K

R71920K

AMP_MUTE

C245100µ

U16

Amplifier

TPA0202

11 MUTE IN

L27120Z/100M

+5V

AOUT_R

AOUT_L

C2840.1µ

C2470.1µ

7,18

C8052.2µ

C8062.2µ

R73310K

R73410K

R72210K

R72120K

22

15

3

10

2 1

43

R1941K

C791100P

R1741K

C789100P

C289100µ

C280100µ

R71022

R71422

L529

+3VS_SPD

SPKROUT+

SPKROUT-

SPKLOUT+

SPKLOUT-

J25

J23

1

2

1

2

LVDD/RVDD

P20

21

20

5

4

VR1_2

VR1_5

JS3

5V_AMP

AUDIO OUT

L43600Z/100M

L44600Z/100M

L39600Z/100M

L45600Z/100M

R

L

L536120Z/100M

Drive

IC

LED

2 1

43L552

120Z/100M

AGNDCAGND

L28600Z/100MSPDIFOUT

L530

789

3

2

1

5

4

5V_AMP

R1Q10DTC144TKA

R964.7K

SPK_OFF

AMP_MUTE

+3VS +3VS_SPDQ529

DTA144WK

R1Q528DTC144TKA

5V_AMP

R71310K

5V_AMP

R7624.7K -DEVICE_DECT

-DECT_HP/OPT

L534600Z/100M

C2010.1µ

J24LINE OUT

From last page

From last page

From last page

InternalSpeakerCONN

-DECT_HP/OPT

RLINE IN

RHP IN

LHP IN

LLINE IN

R1

5V_AMP

R168100K

R15947K

Q523DTC144TKA

-DEVICE_DECT

SE/BTL#

HP/LINE#

14

16

-DEVICE_DECT

0

0

1

1

-DECT_HP/OPT

0

1

0

1

HP

OPT

No this condition

No device

C2864.7µ

C2874.7µ

153


8.12 LAN Test ErrorAn error occurs when a LAN device is installed.

LAN Test Error

Yes

No

TestOK?

Correct it.

Correct it.

No

Check if BIOS setup is ok.

Re-testOK?


ReplaceMotherboard

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscopeto check the following signal or replace the parts one at a time and test after each replacement.

Parts: Signals:

1.Check if the driver is installed properly.2.Check if the notebook connect with the

LAN properly.

Yes

RXIN+RXIN-LAN_CTTXD+TXD-PJRX+PJRX-PJTX+PJTX-PJ8PJ7PJ5PJ4

MIIAVDD+3V_LANLAN_DATAIOLAN_DCLKLAN_MTXD[0:3]LAN_MTXELAN_MTXCLAN_COLLAN_CRSLAN_MRXDVLAN_MRXERLAN_MRXCLAN_MRXD[0:3]OSC25MHIOSC25MHO

U14U5U3J9L5R171R177R166R167R172R178R72R69R67

RP6RP5X4L6L8R32L4R31R538R35R537X1

154


8.12 LAN Test ErrorAn error occurs when a LAN device is installed.

U3

LF-H80P

12

3 4

RXIN+

RXIN-

R4156

R4656

C540.1µ

L6

3 4

12TXD+

TXD-

L4TD+

TD-

TDC

7

6

8

RD+

RD-

1

2P19

PJRX+

PJTX+

PJRX-

PJTX-

16

15

10

9

RX+

RX-

TX+

TX-

TXC

RXC

11

14

R3175

R3575

R53875

R53775

C5771000P

PJ7

PJ4

1,2

4,5

6

3

8

7

P19

J9

U14


SiS961

P15

14

13

5

6

3 LAN_CT

R3061.9

R2761.9

L5120Z/100M C311

0.1µ324

1

C6527P

C6827P

X125MHZ

52

53

C37100P

R320

C4110P

3RDC

C3100.1µ R

J45 LAN

Connector

U5

ISC1893Y

P19

GND_45

R171 33 LAN_DATAIO

+3V_LAN

30

R641.5K

LAN_DCLK 31R177 33

R166 33

R167 33

R172 33

R178 33

LAN_MTXD0

LAN_MTXD1

LAN_MTXD2

LAN_MTXD3

45

46

47

48

LAN_MTXE 43

LAN_MTXC 44

LAN_COL

LAN_CRS

49

50

LAN_MRXDV

LAN_MRXER

LAN_MRXC

1

2

3

4

8

7

6

5

RP622*4 36

39

38

1

2

3

4

8

7

6

5

RP522*4 35

34

33

32

LAN_MRXD0

LAN_MRXD1

LAN_MRXD2

LAN_MRXD3

324

1

C30510P

C30610P

X425MHZ

OSC25MHI

OSC25MHO

R72 22

R69 22

R67 22

+3VL5

120Z/100M

C2320.01µ

MIIAVDD

MIIAVSS

C2300.1µ

C75410µ

JL522

P16

R609 0

R66 0

R61 10K

R49 22K

R595 10K

7,8,15,16,25,54,63

37

51

55

18

VDD[0:6]

VDD_IO0

VDD_IO1

P0AC

RESETN

C571µ

+3V_LAN

L8120Z/100M

+3V+3V_LAN

C440.1µ

C450.1µ

C480.1µ

C620.1µ

C590.1µ

C640.1µ

LAN_GND

LAN_GND

R260 0

R261 0

R262 0

R263 0

GND_45

JS502

155


8.13 PC Card Socket FailureAn error occurs when a PC card device is installed.

PC Card Socket Failure

1. Check if the PC CARD device is installed properly.

2. Confirm PC card driver is installed ok.

TestOK?

Re-testOK?

Yes

No

Yes

No

Change the faulty part then end.


Parts:

U14U508U513U505J11R249R785Q20R789R793R219R220R218

Try another known good PC card device.

Correct it


ReplaceMotherboard

Signals

PCI_AD[0:31]PCI_C/BE# [0:3]PCI_REQ0#PCI_FRAME#PCI_IRDY#PCI_TRDY#PCI_DEVSEL#PCI_STOP#PCI_INTC#-PCIRST#PCI_GNT0#PCI_PARPCI_PERR#

PCI_SERR#CARD_PME#SERIRQ-CARD_RICLK_CARDPCI-VCCEN0-VCCEN1-VPPEN0-VPPEN1+3VSVCCAVPPA

156


8.13 PC Card Socket FailureAn error occurs when a PC card device is installed.

U14


SiS961

IDSEL

U505

TPS2211

J11

U513

PCMCIA

Controller

PCI1410

R22310K C217

0.1µ

+3VS

-CARD_RI

To H8

P14 P15

PCI_AD20

PCI_C/BE#[0:3]

PCI_TRDY#, PCI_STOP#, PCI_PAR, PCI_PERR#

PCI_SERR#, PCI_REQ0#, CARD_PME#, SERIRQ

-PCIRST, PCI_GNT0#

PCI_INTB#

PCI_DEVSEL, PCI_FRAME#, PCI_IRDY#

R789100

R7930

P18

-VCCEN0

-VCCEN1

VPPEN0

VPPEN1

1

2

15

14

+3VS+5VS

+12VS VCCA VPPA

C6840.1µ

C6620.1µ

11~13

10

95,63,4

C6500.1µ

C6610.1µ

17,51

18,52

P18

CAD9

CAD12

R219 0

R220 0

PCI_AD[0:31]

CAD[0:31]

-CCBE[0:3]

-CFRAME, -CIRDY, -CTRDY

-CDEVSEL, -CSTOP, CPAR

-CPERR, -CBLOCK, CVS1,2

-CSERR, -CREQ, -CINT

CAUDIO, CSTSCHG, -CCD1,2

R2_D2, R2_D14, R2_A18

-CGNT

CCLK R218 0

Card Bus Socket

+3VS

VCCA

C2030.1µ

R24910K

R7850

SUSPEND#

AUX_VCC

PCI_VCC[0:3]CORE_VCC[0:5]

SKT_VCC0,1

CLK_CARDPCI

From U508 Clock Generator

Q20DTC144WK

157


8.14 IEEE 1394 FailureAn error occurs when a IEEE 1394 device is installed.

IEEE1394 Fail

1. Check if the 1394 device is installedproperly.

2. Confirm 1394 driver is installed ok.

Yes

No

TestOK?

Correct it.

Correct it.Yes

No

Check if BIOS setup is ok.

Re-testOK?


ReplaceMotherboard


Parts: Signals

PCI_AD[0:31]PCI_C/BE# [0:3]PCI_REQ1#PCI_FRAME#PCI_IRDY#PCI_TRDY#PCI_DEVSEL#PCI_STOP#PCI_INTC#-PCIRST#PCI_GNT1#PCI_PARPCI_PERR#

PCI_SERR#1394_PME#CLK_1394PCISDATASCLKTPA+TPA-TPB+TPB-TPBIAS1+3VS+PHYVDD+PHYAVDD

U14U508U18U7J27L543L544R231R224R198R197R196R195R225X6

158


8.14 IEEE 1394 FailureAn error occurs when a IEEE 1394 device is installed.

U14


SiS961

IDSEL

U7

NM24C02N

J27

U18

IEEE 1394Controller

uPD72872P14 P15

PCI_AD22

PCI_C/BE#[0:3]

PCI_TRDY#, PCI_STOP#, PCI_PAR, PCI_PERR#

PCI_SERR#, PCI_REQ1#, 1394_PME#,

-PCIRST, PCI_GNT1#

PCI_INTC#

PCI_DEVSEL, PCI_FRAME#, PCI_IRDY#

R231100

R2240

P29

SDATA

SCLK

P29PCI_AD[0:31]

1394 Socket

CLK_1394PCI

From U508 Clock Gen.

6

TPBIAS1

R24156

101

100

99

98

96

TPB-

TPB+

TPA-

TPA+

R24356

C3030.01µ

C3040.01µ

R2395.1K

C302270P

R24056

R23856

R198 0

R197 0

R196 0

R195 0

4

3

2

1

JS506

1394_GND

GND1,2

116

117

R862.7K

R872.7K

R2420

R2360

C930.1µ

5

6

7

8

+3VS

L543

+3VS +PHYVDD

C2330.1µ

C8590.1µ

C2310.1µ

C8574.7µ

L544

+3VS +PHYAVDD

C2350.1µ

C8614.7µ

C2410.1µ

C2520.1µ

C2390.1µ

C8630.1µ 3

24

1

C29922P

C30022PX6

24.576MHZ

87

88 R225 1M

159


8575A ID3 14” 8575A ID3 14”Part Number Description Location(S)541667170052 AK;19-UN,BOX,8575A

346600000186 AL-FOIL/CONDUCTIVE ADHESIVE;T=0.

343671600014 AL-FOIL;HST-PANEL_15"-XGA,8175

441999900065 BATT ASSY OPTION;LI-ION,2000mAH

442671700003 BATT ASSY;11.1V/6AH,LI,ID3,MSL,8

441503900201 BATT ASSY;LI,9CELLS/6AH,8575ID3

541350390201 BATT KIT;8575ID3/11.1V,6AH,LI

344671720019 BEZEL;BATTERY,ID3,8575

221671640001 BOX;AK,8175

344600000544 BOX;PVC,0.5*218*240MM,T/P BUTTON

342671600007 BRACKET;LCD,14",8175

342671600005 BRACKET;LCD,R,14",8175

221600020123 CARTON;330*535*373MM,HOUSING CAS

221671220002 CARTON;NON-BRAND,MSL,8170

451671720091 CD-ROM ME KIT;TEAC,ID3,8575

331810006014 CON;MODULAR JACK,FM,6P4C,R/A,UK

346600000059 CONDUCTIVE TAPE;15MM,UCTP,PRC

340671720008 COVER ASSY;DIMM,ID3,8575

340671720001 COVER ASSY;ID3,8575

340671720004 COVER ASSY;KB,ID3,8575

340671720010 COVER ASSY;LCD,14",ID3,8575

344671720017 COVER;BATTERY,ID3,8575

344671720002 COVER;DUMMY,ID3,8575

344671720013 COVER;HDD,ID3,8575

344671720023 COVER;HINGE,ID3,8575

Part Number Description Location(S)344670500042 DUMMY CARD;PCMCIA,TETRA

523499999054 DVD COMBO ASSY OPTION;8575,ID3

523467172012 DVD COMBO ASSY;MATSUSHITA,ID3,85

523467120038 DVD-COMBO DRIVE;UJDA720,8170

227671600001 END CAP;14.1",8175

227671600008 END CAP;BATTERY,AK BOX,8175

227671600009 END CAP;FDD,AK BOX,8175

345671600018 GASKET;HEATSINK,K/B_PLATE,8175

344670500024 GRAIN;PLASTIC,ABS+PC,BLACK,TETRA

451671720071 HDD ME KIT;ID3,8575

340671600020 HINGE;L,14",8175

340671600018 HINGE;R,14",8175

340671720011 HOUSING ASSY;CDROM,ID3,8575

340671720007 HOUSING ASSY;ID3,8575

340671720003 HOUSING ASSY;LCD,14",ID3,8575

451671750001 HOUSING KIT;ID3,8575A

344671720018 HOUSING;BATTERY,ID3,8575

346671720002 INSULATOR;REAR,SCREW,ID3,8575

451671720032 LABEL KIT;N-B,8575 ID3

242671720002 LABEL;AGENCY-GLOBAL,ID3,8575

242671720001 LABEL;BATT 11.1V/6AH,LI,MSL,ID3,

242669900009 LABEL;BLANK,60*80MM,7170

441671720031 LCD ASSY;UNIPAC,XGA,14.1",ID3,85

451671720052 LCD ME KIT;UNIPAC,XGA,14.1",ID3,

413000020289 LCD;UB141X01,TFT,14.1",XGA,UNIPA

9. Spare Parts List - 1

160


8575A ID3 14” 8575A ID3 15”Part Number Description Location(S)416267175001 LT PF;UNIPAC,XGA,14.1",ID3,8575A

526267175010 LTXNX;8575A/T4XX/XXK/3XX1/L9D3C/

561567175001 MANUAL KIT;EN,8575A,N-B

561567175013 MANUAL;USER'S,EN,8575A,N-B

416267175901 NB PF OPTION;XGA,14.1",ID3,8575A

461503900201 PACKING KIT;8575ID3,BATT,LI

461671600002 PACKING KIT;N-B,14.1",8175

221671650014 PARTITION;AK BOX,8175

221671650004 PARTITION;FDD,AK BOX,8175

222668820001 PE BAG;ANTI-STATIC,170x270MM,ORC

411503900203 PWA;PWA-8575ID3/BATT GAUGE BD,LI

411503900201 PWA;PWA-8575ID3/BATT PROTECTION


345671720005 RUBBER;BTM SCREW,ESD,ID3,8575

565180626001 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO

565167000013 S/W;CD-ROM,B'S RECORDER GOLD2.0

370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N

370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8,

370102610805 SPC-SCREW;M2.6L8,K-HD,NIW/NLK

370102010302 SPC-SCREW;M2L3,NIW,K-HD,736

421671600006 WIRE ASSY;LCD,UNIPAC,14",XGA,817

P/N:526267175010

Part Number Description Location(S)541667170052 AK;19-UN,BOX,8575A


346671600021 AL-FOIL;CONDUCTIVE,LCD-SAM_XGA,8

441999900065 BATT ASSY OPTION;LI-ION,2000mAH

442671700003 BATT ASSY;11.1V/6AH,LI,ID3,MSL,8

441503900201 BATT ASSY;LI,9CELLS/6AH,8575ID3

541350390201 BATT KIT;8575ID3/11.1V,6AH,LI

344671720019 BEZEL;BATTERY,ID3,8575

221671640001 BOX;AK,8175

344600000544 BOX;PVC,0.5*218*240MM,T/P BUTTON

342671600006 BRACKET;LCD,L,15",8175

342671600004 BRACKET;LCD,R,15",8175

221600020123 CARTON;330*535*373MM,HOUSING CAS

221671220001 CARTON;MITAC,MSL,8170

451671720091 CD-ROM ME KIT;TEAC,ID3,8575

346600000177 CONDUCTIVE TAPE;UCTP,W=30MM,PRC

340671720008 COVER ASSY;DIMM,ID3,8575

340671720001 COVER ASSY;ID3,8575

340671720004 COVER ASSY;KB,ID3,8575

340671720009 COVER ASSY;LCD,15",ID3,8575

344671720017 COVER;BATTERY,ID3,8575

344671720002 COVER;DUMMY,ID3,8575

344671720013 COVER;HDD,ID3,8575

344671720023 COVER;HINGE,ID3,8575

344670500042 DUMMY CARD;PCMCIA,TETRA


161


8575A ID3 15” 8575A ID3 15”Part Number Description Location(S)523499999054 DVD COMBO ASSY OPTION;8575,ID3

523467172012 DVD COMBO ASSY;MATSUSHITA,ID3,85

523467120038 DVD-COMBO DRIVE;UJDA720,8170

227671600002 END CAP;15.1",8175


227671600009 END CAP;FDD,AK BOX,8175


344670500024 GRAIN;PLASTIC,ABS+PC,BLACK,TETRA

451671720071 HDD ME KIT;ID3,8575

340671600019 HINGE;L,15",8175

340671600017 HINGE;R,15",8175

340671720011 HOUSING ASSY;CDROM,ID3,8575

340671720007 HOUSING ASSY;ID3,8575


451671750001 HOUSING KIT;ID3,8575A

344671720018 HOUSING;BATTERY,ID3,8575

346671720002 INSULATOR;REAR,SCREW,ID3,8575

531099990213 KBD OPTION;87,RU,8575

531020237355 KBD;87,RU,K000918J1,8175

451671720031 LABEL KIT;MITAC,8575 ID3

242671720002 LABEL;AGENCY-GLOBAL,ID3,8575

242671720001 LABEL;BATT 11.1V/6AH,LI,MSL,ID3,

242669900009 LABEL;BLANK,60*80MM,7170

441671720034 LCD ASSY;SAMSUNG,XGA,15.1",ID3,8

451671720053 LCD ME KIT;SAMSUNG,XGA,15.1",ID3

Part Number Description Location(S)413000020265 LCD;LT150X3-124,TFT,15",LVDS,XGA

416267175902 LT PF OPTION;XGA,15",ID3,8575A

416267175003 LT PF;SAMSUNG,XGA,15.1",ID3,8575

526267175011 LTXMX;8575A/T5XX/XXK/3RU1/L9B2C/

561567175001 MANUAL KIT;EN,8575A,N-B


242670000005 NAMEPLATE;LOGO,MITAC,7521

461503900201 PACKING KIT;8575ID3,BATT,LI

461671600009 PACKING KIT;MITAC,15",8175




411503900203 PWA;PWA-8575ID3/BATT GAUGE BD,LI



345671720005 RUBBER;BTM SCREW,ESD,ID3,8575

565180626001 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO

565167000013 S/W;CD-ROM,B'S RECORDER GOLD2.0

370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8,

370102610805 SPC-SCREW;M2.6L8,K-HD,NIW/NLK

370102010302 SPC-SCREW;M2L3,NIW,K-HD,736

225600000029 TAPE;ACETUM ADHESIVE,W=20mm,BLK,

421671600002 WIRE ASSY;LCD,SAM,15",XGA,8175

P/N:526267175011


162


8575A ID4 14” 8575A ID4 14”Part Number Description Location(S)541667170038 AK;05-EU,BAG,8575A

441999900062 BATT ASSY OPTION;LI,9-CELL,8575

442671700002 BATT ASSY;11.1V/6AH,LI,MSL,8575

441503900001 BATT ASSY;Li,9CELLS/6AH,8575

541350390001 BATT KIT;8575/11.1V,6AH,Li

344671600020 BEZEL;BATTERY,8175

342671600007 BRACKET;LCD,14",8175

342671600005 BRACKET;LCD,R,14",8175

220671600002 CARRY BAG;N-B,8175

221671720004 CARTON;NEOBOOK,8575

431671760001 CASE KIT;ID4,8575A

451671600031 CD ROM ME KIT;8175


340671700001 COVER ASSY;8575

340671600012 COVER ASSY;DIMM,8175

340671600029 COVER ASSY;HDD,8175

340671600022 COVER ASSY;LCD,14",8175

344671600018 COVER;BATTERY,8175

344671600010 COVER;DUMMY,8175

344671600016 COVER;HDD,8175

344671600011 COVER;HINGE,8175

344671600043 DUMMY CARD;PCMCIA,8175

227671600001 END CAP;14.1",8175

227669900007 END CAP;IN BAG,7170


Part Number Description Location(S)451671600051 HDD ME KIT;8175

340671600020 HINGE;L,14",8175

340671600018 HINGE;R,14",8175

340671700002 HOUSING ASSY;8575

340671600039 HOUSING ASSY;CDROM,8175


451671760001 HOUSING KIT;ID4,8575A

344671600019 HOUSING;BATTERY,8175

346671700021 INSULATOR;REAR,SCREW,8575

531099990215 KBD OPTION;87,SP,8575

531020237362 KBD;87,SP,K000918J1,8175

340671700015 KEYBOARD COVER;ASSY-B,8575

451671700032 LABEL KIT;N-B,8575

242671700001 LABEL;AGENCY-GLOBAL,8575

242671700002 LABEL;BATT 11.1V/6AH,LI,PANASONI

441671730003 LCD ASSY;UNIPAC,XGA,14.1〃,ID4,8

451671730003 LCD ME KIT;UNIPAC,XGA,14.1〃,ID4


416267176001 LT PF;UNIPAC,XGA,14.1",ID4,8575A

526267176006 LTXNX;8575A/T4XX/XXX/3SP9/L9S4D/

561567175003 MANUAL KIT;EU,8575A,N-B


561567175015 MANUAL;USER'S,EU,8575A,N-B

242671730004 NAMEPLATE;NEOBOOK,8575

416267176901 NB PF OPTION;XGA,14.1",ID4,8575A


163


8575A ID4 14” 8575A ID4 15”Part Number Description Location(S)461503900001 PACKING KIT;8575,BATT,Li

461671700003 PACKING KIT;CALSA CARTON,N-B,14"

221671250002 PARTITION;CARRY BAG,8170

221671250001 PARTITION;IN BAG,8170

222668820004 PE BUBBLE BAG;190X190MM,ANTI-STA

411503900003 PWA;PWA-8575/BATT GAUGE BD,LI

411503900001 PWA;PWA-8575/BATT PROTECTION BD,


345671700034 RUBBER;BTM SCREW,ESD,8575



370102610801 SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1,


P/N:526267176006

Part Number Description Location(S)541667170038 AK;05-EU,BAG,8575A






541350390001 BATT KIT;8575/11.1V,6AH,Li

344671600020 BEZEL;BATTERY,8175

342671600006 BRACKET;LCD,L,15",8175

342671600004 BRACKET;LCD,R,15",8175

220671600002 CARRY BAG;N-B,8175

221671720004 CARTON;NEOBOOK,8575

431671760001 CASE KIT;ID4,8575A

451671600031 CD ROM ME KIT;8175


340671700001 COVER ASSY;8575

340671600012 COVER ASSY;DIMM,8175

340671600029 COVER ASSY;HDD,8175

340671600021 COVER ASSY;LCD,15",8175

344671600018 COVER;BATTERY,8175

344671600010 COVER;DUMMY,8175

344671600016 COVER;HDD,8175

344671600011 COVER;HINGE,8175

344671600043 DUMMY CARD;PCMCIA,8175

227671600002 END CAP;15.1",8175


164


8575A ID4 15” 8575A ID4 15”Part Number Description Location(S)227669900007 END CAP;IN BAG,7170


451671600051 HDD ME KIT;8175

340671600019 HINGE;L,15",8175

340671600017 HINGE;R,15",8175

340671700002 HOUSING ASSY;8575



451671760001 HOUSING KIT;ID4,8575A



531099990215 KBD OPTION;87,SP,8575

531020237362 KBD;87,SP,K000918J1,8175

340671700015 KEYBOARD COVER;ASSY-B,8575

451671700032 LABEL KIT;N-B,8575



441671730001 LCD ASSY;SAMSUNG,XGA,15〃,ID4,85

451671730001 LCD ME KIT;SAMSUNG,XGA,15〃,ID4,

413000020265 LCD;LT150X3-124,TFT,15",LVDS,XGA



526267176007 LTXNX;8575A/T5XX/XXX/3SP9/L9S4D/

561567175003 MANUAL KIT;EU,8575A,N-B


Part Number Description Location(S)561567175015 MANUAL;USER'S,EU,8575A,N-B

242671730004 NAMEPLATE;NEOBOOK,8575

461503900001 PACKING KIT;8575,BATT,Li

461671700002 PACKING KIT;CALSA CARTON,N-B,15"

221671250002 PARTITION;CARRY BAG,8170

221671250001 PARTITION;IN BAG,8170

222668820004 PE BUBBLE BAG;190X190MM,ANTI-STA









P/N:526267176007


165


8575A ID5 14” 8575A ID5 14”Part Number Description Location(S)541667170040 AK;07-GR,BOX,8575A


343671600014 AL-FOIL;HST-PANEL_15"-XGA,8175




541350390001 BATT KIT;8575/11.1V,6AH,Li

344671600020 BEZEL;BATTERY,8175

221671640001 BOX;AK,8175

342671600007 BRACKET;LCD,14",8175

342671600005 BRACKET;LCD,R,14",8175


431671770001 CASE KIT;ID5,8575A

451671600031 CD ROM ME KIT;8175

331810006010 CON;MODULAR JACK,FM,6P4C,R/A,GR


340671600012 COVER ASSY;DIMM,8175

340671600029 COVER ASSY;HDD,8175

340671740006 COVER ASSY;ID5,8575

340671740005 COVER ASSY;KB,ID5,8575

340671740004 COVER ASSY;LCD,14",ID5,8575

344671600018 COVER;BATTERY,8175

344671740107 COVER;DUMMY,ID5,8575

344671600016 COVER;HDD,8175

344671740106 COVER;HINGE,ID5,8575

Part Number Description Location(S)344671600043 DUMMY CARD;PCMCIA,8175

227671600001 END CAP;14.1",8175


227671600009 END CAP;FDD,AK BOX,8175

451671600051 HDD ME KIT;8175

340671600020 HINGE;L,14",8175

340671600018 HINGE;R,14",8175

340671700002 HOUSING ASSY;8575



451671770001 HOUSING KIT;ID5,8575A



531099990211 KBD OPTION;87,GR,8575

531020237349 KBD;87,GR,K000918J1,8175

451671700032 LABEL KIT;N-B,8575



242669900009 LABEL;BLANK,60*80MM,7170

441671740003 LCD ASSY;UNIPAC,XGA,14.1",ID5,85

451671740003 LCD ME KIT;UNIPAC,XGA,14.1",ID5,


416267177901 LT PF OPTION;XGA,14.1",ID5,8575A

416267177001 LT PF;UNIPAC,XGA,14.1",ID5,8575A

526267177015 LTXNX;8575A/T4XX/XXX/3GR4/L9D3E/


166


8575A ID5 14” 8575A ID5 15”Part Number Description Location(S)561567175005 MANUAL KIT;GR,8575A,N-B

561567175017 MANUAL;USER'S,GR,8575A,N-B


461671600002 PACKING KIT;N-B,14.1",8175












P/N:526267177015

Part Number Description Location(S)541667170040 AK;07-GR,BOX,8575A






541350390001 BATT KIT;8575/11.1V,6AH,Li

344671600020 BEZEL;BATTERY,8175

221671640001 BOX;AK,8175

342671600006 BRACKET;LCD,L,15",8175

342671600004 BRACKET;LCD,R,15",8175


431671770001 CASE KIT;ID5,8575A

451671600031 CD ROM ME KIT;8175

331810006010 CON;MODULAR JACK,FM,6P4C,R/A,GR


340671600012 COVER ASSY;DIMM,8175

340671600029 COVER ASSY;HDD,8175

340671740006 COVER ASSY;ID5,8575

340671740005 COVER ASSY;KB,ID5,8575

340671740003 COVER ASSY;LCD,15",ID5,8575

344671600018 COVER;BATTERY,8175

344671740107 COVER;DUMMY,ID5,8575

344671600016 COVER;HDD,8175

344671740106 COVER;HINGE,ID5,8575


167


8575A ID5 15” 8575A ID5 15”Part Number Description Location(S)344671600043 DUMMY CARD;PCMCIA,8175

227671600002 END CAP;15.1",8175


227671600009 END CAP;FDD,AK BOX,8175

451671600051 HDD ME KIT;8175

340671600019 HINGE;L,15",8175

340671600017 HINGE;R,15",8175

340671700002 HOUSING ASSY;8575


340671740001 HOUSING ASSY;LCD 15",ID5,8575

451671770001 HOUSING KIT;ID5,8575A



531099990211 KBD OPTION;87,GR,8575

531020237349 KBD;87,GR,K000918J1,8175

451671700032 LABEL KIT;N-B,8575



242669900009 LABEL;BLANK,60*80MM,7170

441671740001 LCD ASSY;SAMSUNG,XGA,15.1",ID5,8

451671740001 LCD ME KIT;SAMSUNG,XGA,15.1",ID5

413000020265 LCD;LT150X3-124,TFT,15",LVDS,XGA



526267177014 LTXNX;8575A/T5XX/XXX/3GR4/L9D3E/

Part Number Description Location(S)561567175005 MANUAL KIT;GR,8575A,N-B

561567175017 MANUAL;USER'S,GR,8575A,N-B


461671600010 PACKING KIT;N-B,15",8175












P/N:526267177014


168


8575A-ID3/ID4/ID5 Common Spare PartsPart Number Description Location(S)441999900205 AC ADPT ASSY OPTION;8575

442671200004 AC ADPT ASSY;19V/4.74A,DELTA,817

361400003030 ADHESIVE;ABS+PC PACK,G485,CEMIDA

361400003005 ADHESIVE;HEAT,TRANSFER,HTA-48(W)

541667170065 AK;EN,8575A,UTILITY ONLY

346600000531 AL-FOIL/ADHESIVE;T=0.1,W=220,PRC

346671700016 AL-FOIL;HDD,M/B,8575

338536010006 BATTERY;LI,3.6V/2.0AH,18650,PANA

242670800113 BFM-WORLD MARK;WINXP,7521N

340671600010 BRACKET ASSY;T/P,8175

340671600028 BRACKET ASSY;T/P,INSULATOR,8175

342671600003 BRACKET;HDD,8175

421015560001 CABLE ASSY;PHONE LINE,6P2C,W/Z C

272072153401 CAP;.015U ,CR,16V,10%,0603,X7R,S C152,C154,C172,C192

272075103403 CAP;.01U ,50V,10%,0603,X7R,SMT

272075103702 CAP;.01U ,50V,+80-20%,0603,Y5V,S C212,C213,C232,C26,C265,C

272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S PC16,PC20,PC27,PC541

272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S PC525,PC551

272005103401 CAP;.01U ,CR,50V,10%,0805,X7R PC501,PC583

272005103401 CAP;.01U ,CR,50V,10%,0805,X7R PC519

272073223401 CAP;.022U,CR,25V ,10%,0603,X7R,S PC10

272072473401 CAP;.047U,16V ,10%,0603,X7R,SMT

272072104702 CAP;.1U ,16V,+80-20%,0603,Y5V,S C143,C144,C145,C146,C147

272073104703 CAP;.1U ,25V,+80-20%,0603,X7R,S

272073104701 CAP;.1U ,25V,+80-20%,0603,Y5V,S PC4,PC502

Part Number Description Location(S)272075104701 CAP;.1U ,50V,+80-20%,0603,Y5V,S C106,C107,C108,C110,C111

272075104701 CAP;.1U ,50V,+80-20%,0603,Y5V,S C504,C506,C512,C513,C517

272075104703 CAP;.1U ,50V,+80-20%,0603,Y5V,S

272075104703 CAP;.1U ,50V,+80-20%,0603,Y5V,S

272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM PC542,PC572

272003104701 CAP;.1U ,CR,25V ,+80-20%,0805,Y C803,C805,PC22,PC23,PC25

272005104404 CAP;.1U,CR,50V,10%,0805,SMT PC529,PC538,PC545,PC557

272072334701 CAP;.33U ,CR,16V ,+80-20%,0603,Y

272072474701 CAP;.47U ,16V,+80-20%,0603,Y5V,S

272072474701 CAP;.47U ,16V,+80-20%,0603,Y5V,S

272002474401 CAP;.47U ,CR,16V ,10%,0805,X7R,S

272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S C101,C130,C151,C153,C155

627207510241 CAP;1000P,50V ,10%,0603,X7R,SMT

272030102405 CAP;1000P,CR,3KV,10%,1808,X7R,TU C501,C502,C577

272075102403 CAP;1000P,CR,50V,10%,0603,X7R,SM C1,C11,C534,C9,PC13,PC23

272075102403 CAP;1000P,CR,50V,10%,0603,X7R,SM PC28,PC29,PC521,PC527,PC

272075101701 CAP;100P ,50V ,+ -10%,0603,NPO,S PC22

272075101401 CAP;100P ,50V ,10%,0603,COG,SMT C1,C37,C579,C789,C791

272075101401 CAP;100P ,50V ,10%,0603,COG,SMT C4,C7

272075100701 CAP;10P ,50V ,+-10%,0603,NPO,SM C196,C291,C41,C43,C732

272075100302 CAP;10P ,CR,50V ,5%,0603,NPO,SM C701,C702

272021106501 CAP;10U ,10V ,20%,1210,X7R,SMT C100,C132,C133

272021106501 CAP;10U ,10V ,20%,1210,X7R,SMT PC31

272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S C10,C12,C14,C15,C16,C18,C

272012106701 CAP;10U ,16V ,+80-20%,1206,Y5U, C531,PC21


169


Part Number Description Location(S)272012106701 CAP;10U ,16V ,+80-20%,1206,Y5U, C698,PC24,PC27,PC533,PC5

272022106701 CAP;10U ,16V,+80-20%,1210,Y5V,S PC1,PC2

272023106501 CAP;10U ,25V ,20%,1210,Y5U,SMT PC546,PC577

272073151301 CAP;150P ,CR,25V,5% ,0603,NPO,SM PC573

272073151301 CAP;150P ,CR,25V,5% ,0603,NPO,SM PC9

272431157507 CAP;150U ,TPC,6.3V,20%,H1.9,7343 C17,C9,PC524,PC531,PC547

272431157507 CAP;150U ,TPC,6.3V,20%,H1.9,7343 PC12,PC29,PC30

272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 C10,C3,C509,C8

272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 C136,C137,C138,C139,C140

272001105402 CAP;1U ,CR,10V,10%,0805,X5R,SM PC5

272001105402 CAP;1U ,CR,10V,10%,0805,X5R,SM PC532

272002105403 CAP;1U ,CR,16V,10%,0805,X7R,SM

272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, PC550

272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, PC580

272002105701 CAP;1U ,CR,16V ,-20+80%,0805,Y5 C521,C546,PC566

272001225401 CAP;2.2U ,CR,10V ,10%,0805,X7R,S

272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y C283,C788,C804,C806

272012225702 CAP;2.2U ,CR,16V ,+80-20%,1206,Y C522

272012225702 CAP;2.2U ,CR,16V ,+80-20%,1206,Y C714

272075200302 CAP;20P ,CR,50V ,5% ,0603,NPO,S C290

272075222701 CAP;2200P,50V ,+/-20%,0603,X7R,S C23,PC548,PC562

272075221302 CAP;220P ,50V ,5% ,0603,NPO,SMT C519,C520,C549,C550,C798

272075221302 CAP;220P ,50V ,5% ,0603,NPO,SMT PC18,PC28

272431225501 CAP;220U ,TT,4V,20%,7243,OS-CON, PC20

272431227001 CAP;220U, 2.5V,TPE, 7343,18MR PC591,PC592,PC6,PC8

Part Number Description Location(S)272075220701 CAP;22P ,50V ,+ -10%,0603,NPO,S C299,C300,C504

272075220701 CAP;22P ,50V ,+ -10%,0603,NPO,S

272075220301 CAP;22P ,50V ,5% ,0603,COG,SMT C610,C651

272021226701 CAP;22U ,10V,+80-20%,1210,Y5V,S C109,C11,C21,C22,C255,C51

272075271401 CAP;270P ,50V,+-10%,0603,X7R,SMT C2,C5

272075271401 CAP;270P ,50V,+-10%,0603,X7R,SMT C302,C38,C81

272075270302 CAP;27P ,50V ,5%,0603,COG,SMT C65,C68

272075209001 CAP;2P ,CR,50V ,+-0.25PF,0603,

272073330701 CAP;33P ,25V ,+/-10%,0603,NPO,S C12,C13

272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y C756,C857,C861

272002475701 CAP;4.7U ,CR,16V ,+80-20%,0805,Y C286,C287

272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y C273,C648,C699

272012475502 CAP;4.7U ,CR,16V,20%,1206,Y5U,SM

272013475701 CAP;4.7U ,CR,25V ,+80-20%,1206,Y

272075471401 CAP;470P ,50V,10%,0603,X7R,SMT PC19

272075471401 CAP;470P ,50V,10%,0603,X7R,SMT PC541,PC556,PC563

272072471301 CAP;470P ,CR,16V ,5% ,0603,NPO,P

272075470701 CAP;47P ,50V ,+ -10%,0603,NPO,S C118,C121,C122,C125,C126

272431476502 CAP;47U ,6.3V,20%,SP-CON,7343,S PC11

272431476502 CAP;47U ,6.3V,20%,SP-CON,7343,S

272075681401 CAP;680P ,50V ,10%,0603,X7R,SMT PC596

272030680402 CAP;68P ,3KV,10%,1808,NPO,SMT,P

272075680302 CAP;68P ,50V ,5% ,0603,NPO,SMT C707,C710

221669950008 CARD BOARD;FRAME,PALLET,7170

221669950006 CARD BOARD;TOP,PALLET,7170


170


Part Number Description Location(S)221671620001 CARTION;BATTERY,20IN1

431671750001 CASE KIT;ID3,8575A

335152000044 CFM-BAT;FUSE THERMAL 98'C

313000020360 CHOKE COIL;1.25uH,+30-0%,4.5Ts,D PL1,PL2

273000111002 CHOKE COIL;120OHM/100MHZ,20%,321 L1,L4,L529,L530,L6

273000111002 CHOKE COIL;120OHM/100MHZ,20%,321 L508,L509,L518,L522

331000008038 CON;BAT,8P,2.5MM,SUYIN J14

291000001001 CON;BATTERY,10P,FM,2MM,R/A,SMT

331000007015 CON;BATTERY,FM,7P,R/A,8175,PRC

331720015006 CON;D,FM,15P,2.29,R/A,3ROW J2

331720025005 CON;D,FM,25P,2.775,R/A J3

291000153006 CON;FPC/FFC,15P*2,.8MM,BD/BD,ST, J18

291000142404 CON;FPC/FFC,24P,1MM,H8.2,ST,ACES J13

291000150804 CON;FPC/FFC,8P,1MM,R/A,2CONTAC,E J501

291000144004 CON;HDR,20P*2,1.0MM,H=4.6,ST,SMT J3

331040020004 CON;HDR,FM,10P*2,2.54MM,R/A,H8,4 J4

331030044013 CON;HDR,FM,22*2,2MM,ST,C16805

331040050013 CON;HDR,FM,25P*2,1.27X1.27MM,D/R J7

291000011024 CON;HDR,FM,5P*2,1.27MM,ST,H4.5,S J501

331040020005 CON;HDR,MA,10P*2,2.54MM,R/A,H8.4 PJ1

291000021101 CON;HDR,MA,11P*1,1.25,R/A,DF13-1

291000011209 CON;HDR,MA,12P*1,1.25,ST,SMT J6

291000024409 CON;HDR,MA,22P*2,2MM,R/A,SMT,ALL J19

331040050012 CON;HDR,MA,25P*2,1.27X1.27MM,D/R PJ2

291000020202 CON;HDR,MA,2P*1,1.25,R/A,SMT,HIR J508

Part Number Description Location(S)291000020204 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM

331040050010 CON;HDR,MA,50P,0.8MM,R/A,H1.1 J12

291000011030 CON;HDR,MA,5P*2,1.27MM,ST,H17,85 J6

291000020303 CON;HDR,SHROUD,MA,3P,1.25MM,R/A, J503

291000256823 CON;IC CARD PART;68P,0.635,H5,SM J11

331000004018 CON;IEEE1394,MA,4P,.8MM,R/A,LINK J27

331870004017 CON;MINI DIN,4P,R/A,W/GROND,C108 J1

291000810205 CON;PHONE JACK,2P,H=8.4,R/A,SMT J1

291000810808 CON;PHONE JACK,8P,H=12.59,R/A,RJ J9

331840010005 CON;POF MINI JACK,10P,W/SPDIF,2F J24

331910002006 CON;POWER JACK,2P,20VDC,5A,DIP J2

331840005013 CON;STEREO JACK,5P,R/A,28MF60-07 J28

331000004029 CON;USB,MA,R/A,4P*1,2551A-04G5T- J4,J5,J7,J8

291000410201 CON;WFR,MA,2P,1.25,ST,SMT/MB J21,J23,J25,J5

291000410301 CON;WFR,MA,3P,1.25,ST,SMT/MB J8

291000410401 CON;WFR,MA,4P,1.25MM,ST,SMT J502

291000410801 CON;WFR,MA,8P*1,1.25MM,ST,SMT J20



346600000039 CONDUCTIVE TAPE;5MM,UCTP/8269H,P

225600000290 CONDUCTIVE TAPE;U-TEK/UCTP,W=10M

225600000292 CONDUCTIVE TAPE;U-TEK/UCTP,W=20M

342503400302 CONTACT PLATE;W5L135T0.13,8170LI

342503400005 CONTACT PLATE;W5L24T0.13,7170LI,



171


Part Number Description Location(S)342503400006 CONTACT PLATE;W5L45T0.13,7170LI,



342503400002 CONTACT PLATE;W5L9T0.13,7170LI,P

342503400003 CONTACT PLATE;W7L7T0.13,7170LI,P

313000150093 CORE;LAN CORE,230OHM/100MHZ,LF-1

272625220401 CP;22P*4 ,8P,50V ,10%,1206,NPO,S CP501,CP502,CP503,CP504,

346600000142 DIALAMY;T=0.1,W=113,WHITE,PRC

331660020004 DIMM SOCKET;DDR SODIMM 200P, CA0 J505

331660020005 DIMM SOCKET;DDR SODIMM 200P, CA0 J506

288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D501,PD2,PD3,PD515,PD51

288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 PD506,PD507,PD510,PD517

288100054001 DIODE;BAT54,30V,200mA,SOT-23 D509,D510

288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23 D511

288100099001 DIODE;BAV99,70V,450MA,SOT-23 D1,D3,D4,D6

288100099001 DIODE;BAV99,70V,450MA,SOT-23 PD5,PD8

288100099001 DIODE;BAV99,70V,450MA,SOT-23

288100056003 DIODE;BAW56,70V,215mA,SOT-23 D3,D504

288100056003 DIODE;BAW56,70V,215mA,SOT-23 D514

288100084002 DIODE;BZX84C5V6,5.2~6V,350mA,SOT

288101004024 DIODE;EC10QS04,RECT,40V,1A,CHIP, PD1,PD2

288101004024 DIODE;EC10QS04,RECT,40V,1A,CHIP, PD1,PD4

288100112003 DIODE;EC11FS2-TE12L,SCHOTTKY,200 PD503,PD504,PD511

288100112003 DIODE;EC11FS2-TE12L,SCHOTTKY,200 PD504,PD505

288103104001 DIODE;EC31QS04-TE12L,40V,3A,SMT PD3,PD4,PD501,PD502,PD5

Part Number Description Location(S)288103104001 DIODE;EC31QS04-TE12L,40V,3A,SMT PD505,PD506,PD514

288104148001 DIODE;RLS4148,200MA,500MW,MELF,S D11,D14,D15,D16,D17,D513

288100020001 DIODE;RLZ20C,ZENER,19.23V,5%,SMT PD511

288100024002 DIODE;RLZ24D,ZENER,23.63V,5%,SMT PD501

288100056001 DIODE;RLZ5.6B,ZENER,5.6V,5%,LL34 D10,D5,D508

288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM D516

288100018003 DIODE;UDZS18B,ZENER,18V,SOD-323,

272602107501 EC;100U,16V,M,6.3*5.5,-55+85'C,S C245,C280,C289

312271006358 EC;100U,25V,RA,M,D6.3*7,SGX,SANY PC15,PC17,PC18

312271006358 EC;100U,25V,RA,M,D6.3*7,SGX,SANY PC25

312271005357 EC;10U,25V,20%,RA,6.3*6.8,+105 PC11,PC12,PC14

312271005357 EC;10U,25V,20%,RA,6.3*6.8,+105 PC2,PC3

312273361501 EC;330U ,6.3V ,RA,M,6.3*7,+105C PC1,PC6

312304705351 EC;47U,25V,20%,D10X10.5,105'C,SY PC31,PC32,PC33

312374705351 EC;47U,25V,20%,D10X10.5,85,SYO

312278206152 EC;820U ,4V,+-20%,10X10.5,FPCAP PC3,PC5,PC7,PC9

481672400002 F/W ASSY;KBD CTRL,SCORPIO U509

481671750001 F/W ASSY;SYS/VGA BIOS,8575A U10

481672400001 F/W ASSY;SYS/VGA BIOS,SCORPIO U10

340671200020 FAN ASSY;8170

273000610019 FERRITE ARRAY;130OHM/100MHZ,3216 FA501

273000610019 FERRITE ARRAY;130OHM/100MHZ,3216 FA501

273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L27,L504,L523,L554,PL5,PL

273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L504,L512,L514,L516,L520,L

273000130039 FERRITE CHIP;130OHM/100MHZ,1608, L1,L4,L513,L515


172


Part Number Description Location(S)273000130039 FERRITE CHIP;130OHM/100MHZ,1608, L16,L17,L18,L19,L20,L21,L2

273000150001 FERRITE CHIP;220OHM/100MHZ,2012,

273000150036 FERRITE CHIP;32OHM/100MHZ,2012,S L34,L35,L40,L545,L546,L547

273000130038 FERRITE CHIP;600OHM/100MHZ,1608, L28,L39,L43,L44,L45,L531,L

422665400002 FFC ASSY;TOUCH PAD,CASE KIT,VENU

341671200010 FINGER;EMI GROUND SMD FINGER,H=4 E501,E502

341671200010 FINGER;EMI GROUND SMD FINGER,H=4 E511,E518,E519

342671700001 FINGER;EMI GROUNDING SMD FINGER E1,E10,E2,E4,E5,E7,E8,E9

342672400007 FINGER;EMI GROUNDING SMD FINGER E501,E502,E503,E507,E520

288003600001 FIR;HSDL3600#007,FRONT VIEW,10P, U2

295000010105 FUSE;1A,NORMAL,1206,SMT F1,F501,F503,F504

295000010057 FUSE;228R,139C',5A/250V,SMT,PRC

295000010116 FUSE;FAST, 10A, 86VDC, 6125,SMT PF501

295000010116 FUSE;FAST, 10A, 86VDC, 6125,SMT PF502

295000010029 FUSE;FAST,.75A,63V,1206,THIN FIL PF501

295000010114 FUSE;FAST,1.75A,63VDC,1206,SMT,P

335152000062 FUSE;LR4-730,POLY SWITCH,PRC

345671700009 GASKET;BRACKET T/P,8575

345671700033 GASKET;BTM SHD,ESD,8575

345671700032 GASKET;HEATSINK,ESD,8575

345671700029 GASKET;HOUSING,ESD,8575

345671700011 GASKET;KB PLATE-1,8575

345671700031 GASKET;LAN,ESD,8575

345671600016 GASKET;LCD-HINGE,8175

345671700019 GASKET;MIC,8575

Part Number Description Location(S)345671700030 GASKET;PHONE JACK,ESD,8575

345671700004 GASKET;USB,8575

230000010004 GLUE;9001B,BLACK,PRC

230000010003 GULE;9001A,BLACK,PRC

340671700006 HEATSINK ASSY;N/B,8575

340671750001 HEATSINK ASSY;P4,CPU,ID3,8575A

344600000425 HOUSING;HIROSE/DF13-4S-1.25C,PRC

344600000842 HOUSING;HRS/DF13-11S-1.25C,PRC



344600000577 HOUSING;JAE/F1-S20S,PRC

344600000863 HOUSING;JST//SHDR-40V-S-B,PRC

344600000824 IC CARD CON PART;68P,IC11SA-BD-P

291000614793 IC SOCKET;UPGA479M,479P,MOLEX U1

282574373004 IC;74AHC373,OCT D-TRAN,TSSOP,20P U8

282574186002 IC;74AHCT1G86,SINGLE,XOR,SOT23,S U513

282074338402 IC;74CBTD3384,10 BIT BUS SW,TSOP U11

282574164002 IC;74VHC164,SIPO REGISTER,TSSOP, U517

284501032001 IC;ADM1032,TEMPERATURE MTR,SO8 U2

284500202003 IC;ALC202,AUDIO CODEC,TQFP,48P U15

286308800006 IC;AME8800AEEV,VOL REG.,SOT23-5, U17

286308801002 IC;AME8801MEEV,VOL REG.,SOT23-5, U512

286002040001 IC;BQ2040,GAS GAUGE,SO,16P,SMT

284508500002 IC;CM8500,3A BUS TERMINATOR,PTSS PU10

283400000003 IC;EEPROM,NM24C02N,2K,SO,8P U7


173


Part Number Description Location(S)283400000003 IC;EEPROM,NM24C02N,2K,SO,8P

283450083001 IC;FLASH,256K*8-70,PLCC32,ST39SF

283450083001 IC;FLASH,256K*8-70,PLCC32,ST39SF

284583437003 IC;H8/F3437S,KBD CTRL,TQFP,100P, U509

284583437003 IC;H8/F3437S,KBD CTRL,TQFP,100P,

286317812001 IC;HA178L12UA,VOLT REGULATOR,SC- PU507

284501893001 IC;ICS-1893,LAN-PHY,TQFP,64P,SMT U5

284593722001 IC;ICS93722,DDR ZERO DELAY CLOCK U9

284595200101 IC;ICS952001,TIMING CTL HUB FOR U508

286300811002 IC;IMP811,RESET CIRCUIT,4.38,SOT U515

286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P PU514

286302951015 IC;LP2951ACM,VOLTAGE REGULATOR,S U506

286303707001 IC;LTC3707,PWM SWITCH REG,SOOP,2 PU4

286303707001 IC;LTC3707,PWM SWITCH REG,SOOP,2 PU510

286303716001 IC;LTC3716,PWM,QSOP,36P PU508

286104173001 IC;MAX4173F,I-SENSE AMP,SOT23,6P PU1

286300809002 IC;MAX809S,RESET CIRCUIT,2.9V,SO U12

286305258001 IC;MIC 5258-1.2BM5,LV12,LDO REG, U502

286301414001 IC;MM1414,PROTECTION,TSOP-20A,PR

286300965001 IC;OZ965R,CCFL CTRL,TSSOP16,O2

284501284001 IC;PAC1284-01Q,TERMIN. NETWK,QSO U501,U502

284587393002 IC;PC87393F,TQFP,100P U511

284501410008 IC;PCI1410AGGU,BGA144P U6

286309701001 IC;RT9701,POWER DISTRI SW,SOT23- U1,U3

286381250001 IC;S-81250,DECECTOR,SOT-89,PRC

Part Number Description Location(S)286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT2 PQ510

284500301004 IC;SIS301LV,TV ENCODER/LVDS,128P U504

284500650002 IC;SIS650,N.B.,BGA702 U4

284500961003 IC;SIS961 HM-I/O,S.B.,BGA371 U14

286300594001 IC;TL594C,PWM CONTROL,SO,16P PU511

286100202001 IC;TPA0202,AUDIO AMP,2W,TSSOP,24 U16

286302211001 IC;TPS2211,POWER DISTRI SW,SSOP1 U505

284572872001 IC;UPD72872;IEEE1394;PQFP120,2PO U18

273000990012 INDUCTOR;10UH,CDRH127,SUMIDA,SMT PL2

273000990012 INDUCTOR;10UH,CDRH127,SUMIDA,SMT PL4

273000990031 INDUCTOR;10UH,CDRH127B,SUMIDA,SM PL3

273000990054 INDUCTOR;10UH,D124C,+/-20%,TOKO, PL3

273000990115 INDUCTOR;3.3uH,3A,CSS054D,SMT PL8

273000990021 INDUCTOR;33uH,CDRH124,SUMIDA,SMT PL6

273000150106 INDUCTOR;4.7UH,10%,2012,30mA,SMT L2,L3

346671200036 INSULATOR,MDC,8170

346600000464 INSULATOR/2ADHESIVE;FIBER/W204,T



346600000414 INSULATOR/ADHESIVE;FIBER/W204,T=



346503100005 INSULATOR;5,BATTERY ASSY,7521Li

346671700001 INSULATOR;AL-FOIL,M/B BOTTOM,857

346503400504 INSULATOR;BATT ASSY,L125,8175


174


Part Number Description Location(S)346503400502 INSULATOR;BATT ASSY,L22R9.2,8175

346503200006 INSULATOR;BATT ASSY,ONE ROUND,GR

346503400503 INSULATOR;BATT ASSY,W7L13,8175

346671700006 INSULATOR;CD-ROM,M-B,8575

346503400301 INSULATOR;FOR 3 CELLS,DOUBLE-FA,

346503400501 INSULATOR;FOR 4 CELL,DOUBLE-FACE

346503200002 INSULATOR;FOR 4 CELLS,GRAMPUS

346669900004 INSULATOR;INVERTER,7170

346671700023 INSULATOR;M/B,ESD,8575

346671750002 INSULATOR;MINIPCI,ID3,8575A

346503400203 INSULATOR;ONE ROUND,STINGRAY

346503900001 INSULATOR;PCB ASSY,W15L52,8575

346671600015 INSULATOR;PCMCIA,8175

346671700022 INSULATOR;PHONE JACK,8575

346671600009 INSULATOR;T/P,BRACKET,8175

346600000403 INSULATOR;TWO DIALAMY,T=0.1,W=60

346503400303 INSULATOR;W13MML52MM,8170Li,PRC

242600000145 LABEL;10*10,BLANK,COMMON



242600000457 LABEL;20*7MM,COMMON,PRC

242662300009 LABEL;25*10MM,3020F

242662300009 LABEL;25*10MM,3020F

242662300009 LABEL;25*10MM,3020F

242600000434 LABEL;25*6MM,COMMON

Part Number Description Location(S)242668300017 LABEL;4*3MM,HI-TE

242668300017 LABEL;4*3MM,HI-TE


242600000157 LABEL;BAR CODE & S/N,13.5*75,COM

242600000364 LABEL;BLANK,6*6MM,HI-TEMP

242600000452 LABEL;BLANK,7MM*7MM,PRC

242600000452 LABEL;BLANK,7MM*7MM,PRC

242664800013 LABEL;CAUTION,INVERT BD,PITCHING

242600000315 LABEL;RED ARROW HEAD,PRC

242600000195 LABEL;SOFTWARE,INSYDE BIOS-M

294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190

294011200001 LED;GRN,H1.5,0805,PG1102W,SMT D18,D19,D20,D21,D22,D23

294011200070 LED;RED/GREEN,19-22SRVGC/TR8,LED

421671600051 MICROPHONE ASSY;8175

291000001203 MINIPCI SOCKET;124P,0.8MM,H=6,SM J509

346600000446 MYLAR/3M-467;T=0.1,W=46,BLACK,PR

346600000465 MYLAR/ADHESVIE;MYLAR/W204,T=0.1,

346600000074 MYLAR;T=0.1,W=110,BLACK,PRC



346600000321 MYLAR;T=0.2,W=72.4,BLACK,PRC

375102030010 NUT-HEX;M2,2,NIW

375120262008 NUT-HEX;M2.6,NCG

227671600003 PAD;LCD/KB,ANIT-STATIC,8175

224670830002 PALLET;1250*1080*130,7521N


175


Part Number Description Location(S)221671650009 PARTITION;BATTERY,8575N

221671250005 PARTITION;HDD CASE,8170

221671250003 PARTITION;PALLET,8170

221671650010 PARTITION;TOP/BTM,8575N

412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/

316671200005 PCB;PWA-8170/ESB BD R01

316503400501 PCB;PWA-8175/BATT GAUGE BD

316503400502 PCB;PWA-8175/BATT PROTECTION BD

316671700002 PCB;PWA-8575/DD BD R0B

316671700003 PCB;PWA-8575/TOUCHPAD BD R00

316671750001 PCB;PWA-8575A/MOTHER BD R01

316503400101 PCB;PWA-STINGRAY/INVERTER BD

222600020049 PE BAG;50*70MM,W/SEAL,COMMON

222600020310 PE BAG;70X100MM,W/SEAL,COMMON

222667220003 PE BAG;L560XW345,CERES

222670000001 PE BUBBLE BAG;BATTERY,7521

222503220001 PE BUBBLE BAG;BATTERY,GRAMPUS

222671620001 PE BUBBLE BAG;CD-ROM HOUSING,817

230000000003 PEN;OIL,BLUE,PRC

273000150033 PHASEOUT;FERRITE CHIP,120OHM/100 L12,L13,L14,L15,L22,L24,L2

343671600006 PLATE;KB,8175

411671200007 PWA;PWA-8170,ESB BD

411671700007 PWA;PWA-8575,D/D BD R0A,SMT

411671700006 PWA;PWA-8575,D/D BD R0A,T/U

411671700009 PWA;PWA-8575,T/P BD

Part Number Description Location(S)411671750010 PWA;PWA-8575A,MOTHER R00 BD

411671750012 PWA;PWA-8575A,MOTHER R00 BD,SMT

411671750011 PWA;PWA-8575A,MOTHER R00 BD,T/U

411503400201 PWA;PWA-STINGRAY/INVERTER BD

411503400202 PWA;PWA-STINGRAY/INVERTER BD,SMT

332810000034 PWR CORD;250V/2.5A,2P,BLK,EU,175

271046037103 RES;.003,1.5W,1%,2512,SMT PR501,PR503

271046057102 RES;.005,1.5W,1%,2512,SMT PR502,PR504

271045087101 RES;.008 ,1W ,1% ,2512,SMT PR16

271045107101 RES;.01 ,1W ,1% ,2512,SMT PR4,PR506

271045107101 RES;.01 ,1W ,1% ,2512,SMT PR525

271045157101 RES;.015 ,1W ,1% ,2512,SMT PR515

271586026101 RES;.02 ,2W,1%,2512,SMT PR13

271046257101 RES;.025 ,2W ,1% ,2512,SMT,PRC

271002000301 RES;0 ,1/10W,5% ,0805,SMT L2

271002000301 RES;0 ,1/10W,5% ,0805,SMT L513

271071000002 RES;0 ,1/16W,5% ,0603,SMT C305,C723,L538,PR32,PR52

271071000002 RES;0 ,1/16W,5% ,0603,SMT PR17,PR522,PR523,R1,R511

271071152101 RES;1.5K ,1/16W,1% ,0603,SMT R579

271071152101 RES;1.5K ,1/16W,1% ,0603,SMT

271071152302 RES;1.5K ,1/16W,5% ,0603,SMT R64

271071100302 RES;10 ,1/16W,5% ,0603,SMT PR1,PR2,PR521,R100,R101,

271071100302 RES;10 ,1/16W,5% ,0603,SMT PR3

271071100302 RES;10 ,1/16W,5% ,0603,SMT

271071102211 RES;10.2K,1/16W,1% ,0603,SMT


176


Part Number Description Location(S)271071101101 RES;100 ,1/16W,1% ,0603,SMT R522,R536

271071101301 RES;100 ,1/16W,5% ,0603,SMT R231,R548,R566,R74,R789,R

271071101301 RES;100 ,1/16W,5% ,0603,SMT

271071101301 RES;100 ,1/16W,5% ,0603,SMT

271071104101 RES;100K ,1/16W,1% ,0603,SMT PR557,PR563

271071104101 RES;100K ,1/16W,1% ,0603,SMT

271071104101 RES;100K ,1/16W,1% ,0603,SMT

271071104101 RES;100K ,1/16W,1% ,0603,SMT

271071104302 RES;100K ,1/16W,5% ,0603,SMT PR15,PR27,PR28,PR3,PR538

271071104302 RES;100K ,1/16W,5% ,0603,SMT PR508,PR518

271071104302 RES;100K ,1/16W,5% ,0603,SMT

271071104302 RES;100K ,1/16W,5% ,0603,SMT

271071103101 RES;10K ,1/16W,1% ,0603,SMT PR12,PR19

271071103101 RES;10K ,1/16W,1% ,0603,SMT PR507,PR513,PR527,PR540,

271071103101 RES;10K ,1/16W,1% ,0603,SMT

271071103302 RES;10K ,1/16W,5% ,0603,SMT PR574,R125,R138,R149,R15

271071103302 RES;10K ,1/16W,5% ,0603,SMT R10,R516

271071103302 RES;10K ,1/16W,5% ,0603,SMT

271071106301 RES;10M ,1/16W,5% ,0603,SMT R189

271071111101 RES;110 ,1/16W,1% ,0603,SMT R20

271071113101 RES;11K ,1/16W,1% ,0603,SMT PR530

271071113101 RES;11K ,1/16W,1% ,0603,SMT PR8

271071121211 RES;12.1K,1/16W,1% ,0603,SMT R578,R731,R732,R733,R734

271071127211 RES;12.7K,1/16W,1%,0603,SMT PR508

271071137271 RES;13.7K,1/16W,.1%,0603,SMT PR10,PR558

Part Number Description Location(S)271071131101 RES;130 ,1/16W,1% ,0603,SMT R545

271071134701 RES;130K ,1/16W,0.1% ,0603,SMT PR560

271071134101 RES;130K ,1/16W,1% ,0603,SMT PR575

271071147011 RES;147 ,1/16W,1% ,0603,SMT R549

271071151101 RES;150 ,1/16W,1% ,0603,SMT R109,R116,R21,R508,R553,R

271071151302 RES;150 ,1/16W,5% ,0603,SMT R503

271071154101 RES;150K ,1/16W,1% ,0603,SMT

271071153101 RES;15K ,1/16W,1% ,0603,SMT PR13,PR14

271071153101 RES;15K ,1/16W,1% ,0603,SMT PR528,PR532,R720,R722

271071153101 RES;15K ,1/16W,1% ,0603,SMT

271071153301 RES;15K ,1/16W,5% ,0603,SMT R107,R114,R269,R270

271071153301 RES;15K ,1/16W,5% ,0603,SMT R502,R503,R504,R505,R508

271071164301 RES;160K ,1/16W,5% ,0603,SMT

271071182214 RES;18.2K,1/16W,1%,0603,SMT PR519

271071187311 RES;187K ,1/16W,1% ,0603,SMT PR20

271071102102 RES;1K ,1/16W,1% ,0603,SMT PR19,R556,R95

271071102102 RES;1K ,1/16W,1% ,0603,SMT

271071102302 RES;1K ,1/16W,5% ,0603,SMT PR517

271071102302 RES;1K ,1/16W,5% ,0603,SMT PR537,R1,R174,R194,R43,R5

271071105101 RES;1M ,1/16W,1% ,0603,SMT PR550

271071105101 RES;1M ,1/16W,1% ,0603,SMT

271071105301 RES;1M ,1/16W,5% ,0603,SMT PR5,PR539,PR545,PR6,PR60

271071105301 RES;1M ,1/16W,5% ,0603,SMT PR509,PR521,PR6,PR7,R528

271071222102 RES;2.2K ,1/16W,1% ,0603,SMT PR511

271071222302 RES;2.2K ,1/16W,5% ,0603,SMT R552,R558,R672,R674


177


Part Number Description Location(S)271071225301 RES;2.2M,1/16W,5% ,0603,SMT

271071249111 RES;2.49K,1/16W,1% ,0603,SMT PR546

271012278101 RES;2.7 ,1/8W,1% ,1206,SMT R14

271071272101 RES;2.7K ,1/16W,1% ,0603,SMT PR531

271071272101 RES;2.7K ,1/16W,1% ,0603,SMT PR9

271071272301 RES;2.7K ,1/16W,5% ,0603,SMT R86,R87

271071200101 RES;20 ,1/16W,1% ,0603,SMT R544

271072201101 RES;200 ,1/10W,1% ,0603,SMT R57

271071201301 RES;200 ,1/16W,5% ,0603,SMT R246,R524,R63,R748,R749,R

271071201301 RES;200 ,1/16W,5% ,0603,SMT

271071204101 RES;200K ,1/16W,1% ,0603,SMT PR18

271071203701 RES;20K ,1/16W,.1%,0603,SMT PR7

271071203101 RES;20K ,1/16W,1% ,0603,SMT PR12,PR21,PR581

271071203101 RES;20K ,1/16W,1% ,0603,SMT

271071203302 RES;20K ,1/16W,5% ,0603,SMT R679,R719,R721

271071215211 RES;21.5K,1/16W,1% ,0603,SMT PR526

271071221302 RES;22 ,1/16W,5% ,0603,SMT R117,R118,R119,R129,R130

271071226311 RES;226K ,1/16W,1% ,0603,SMT PR551

271071223302 RES;22K ,1/16W,5% ,0603,SMT PR522,R49

271071244301 RES;240K ,1/16W,5% ,0603,SMT

271071249311 RES;249K ,1/16W,1% ,0603,SMT PR547

271071267211 RES;26.7K,1/16W,1% ,0603,SMT PR29

271071270301 RES;27 ,1/16W,5% ,0603,SMT R509

271071202301 RES;2K ,1/16W,5% ,0603,SMT PR573,R577,R727,R728,R83

271071205101 RES;2M ,1/16W,1% ,0603,SMT

Part Number Description Location(S)271071205301 RES;2M ,1/16W,5% ,0603,SMT PR26,PR34,PR35

271071301301 RES;300 ,1/16W,5% ,0603,SMT R267

271071301011 RES;301 ,1/16W,1% ,0603,SMT R12,R62

271071301311 RES;301K ,1/16W,1% ,0603,SMT PR564

271071324211 RES;32.4K,1/16W,1% ,0603,SMT PR5

271071330302 RES;33 ,1/16W,5% ,0603,SMT R16,R166,R167,R171,R172,R

271071330302 RES;33 ,1/16W,5% ,0603,SMT R9

271071333301 RES;33K ,1/16W,5% ,0603,SMT PR16,PR552,R697

271071333301 RES;33K ,1/16W,5% ,0603,SMT R2,R3,R506,R7

271071390302 RES;39 ,1/16W,5% ,0603,SMT R532

271072302301 RES;3K ,1/10W,5% ,0603,SMT R739

271002472301 RES;4.7K ,1/10W,5% ,0805,SMT PR516

271071472302 RES;4.7K ,1/16W,5% ,0603,SMT PR14,PR4,PR561,R120,R144

271071499111 RES;4.99K,1/16W,1% ,0603,SMT PR11

271071412311 RES;412K ,1/16W,1% ,0603,SMT PR22

271071432211 RES;43.2K,1/16W,1% ,0603,SMT PR518

271071471101 RES;470 ,1/16W,1% ,0603,SMT

271071471302 RES;470 ,1/16W,5% ,0603,SMT R137,R156,R157,R200,R201

271071474301 RES;470K ,1/16W,5% ,0603,SMT PR507,PR510

271071474301 RES;470K ,1/16W,5% ,0603,SMT R505,R683,R7

271071475011 RES;475 ,1/16W,1% ,0603,SMT R85

271071473301 RES;47K ,1/16W,5% ,0603,SMT PR544,R134,R159

271071473301 RES;47K ,1/16W,5% ,0603,SMT R4,R5,R518,R8

271071487211 RES;48.7K,1/16W,1% ,0603,SMT

271071487311 RES;487K ,1/16W,1% ,0603,SMT PR9


178


Part Number Description Location(S)271071499811 RES;49.9 ,1/16W,1% ,0603,SMT R533,R535,R636,R640,R645

271071518301 RES;5.1 ,1/16W,5% ,0603,SMT PR17,PR514

271071512101 RES;5.1K ,1/16W,1% ,0603,SMT R239

271002515302 RES;5.1M ,1/8W ,5% ,0805,SMT,PRC

271071562301 RES;5.6K ,1/16W,5% ,0603,SMT R131,R140

271071510301 RES;51 ,1/16W,5% ,0603,SMT R512,R513,R514,R515,R516

271071511812 RES;51.1,1/16W,1% 0603,SMT R14,R521

271071513301 RES;51K ,1/16W,5% ,0603,SMT R184

271071536211 RES;53.6K,1/16W,1% ,0603,SMT PR18

271071560101 RES;56 ,1/16W,1% ,0603,SMT R276,R41,R46,R605,R676

271071560301 RES;56 ,1/16W,5% ,0603,SMT R238,R240,R241,R243,R587

271071561101 RES;560 ,1/16W,1% ,0603,SMT

271071576311 RES;576K ,1/16W,1% ,0603,SMT PR556

271071604111 RES;6.04K,1/16W,1% ,0603,SMT R550

271071619111 RES;6.19K,1/16W,1% ,0603,SMT PR543

271071682301 RES;6.8K ,1/16W,5% ,0603,SMT R185,R186,R187

271071604811 RES;60.4 ,1/16W,1% ,0603,SMT R50

271071619811 RES;61.9 ,1/16W,1% ,0603,SMT R27,R30

271071620102 RES;62,1/16W,1% 0603,SMT R10,R11,R528

271071681101 RES;680 ,1/16W,1% ,0603,SMT R534

271071683101 RES;68K ,1/16W,1% ,0603,SMT

271071698311 RES;698K ,1/16W,1% ,0603,SMT

271071750101 RES;75 ,1/16W,1% ,0603,SMT R25,R562

271071750302 RES;75 ,1/16W,5% ,0603,SMT R31,R35,R525,R537,R538,R5

271071754301 RES;750K ,1/16W,5% ,0603,SMT PR23

Part Number Description Location(S)271071822301 RES;8.2K ,1/16W,5% ,0603,SMT R190

271071866111 RES;8.66K,1/16W,1% ,0603,SMT PR549

271071820301 RES;82 ,1/16W,5% ,0603,SMT R205,R207,R210,R777

271071887211 RES;88.7K,1/16W,1% ,0603,SMT

271071909101 RES;9.09K,1/16W,1% ,0603,SMT R228

271071909011 RES;909 ,1/16W,1% ,0603,SMT

271071976311 RES;976K ,1/16W,1% ,0603,SMT PR8

271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP1,RP2,RP3,RP4

271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP48,RP501,RP503,RP504,R

271571000301 RP;0*8 ,16P ,1/16W,5% ,1606,SM RP13,RP14,RP15

271611100301 RP;10*4 ,8P ,1/16W,5% ,0612,SMT FA502,FA503,FA504,FA505,F

271571100301 RP;10*8 ,16P ,1/16W,5% ,1606,SM RP10,RP11,RP12,RP16,RP17

271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT RP3,RP4,RP40,RP518,RP529

271611102301 RP;1K*4 ,8P ,1/16W,5% ,0612,SMT RP1

271621102302 RP;1K*8 ,10P,1/32W,5% ,1206,SMT RP2,RP507

271611220301 RP;22*4 ,8P ,1/16W,5% ,0612,SMT RP5,RP512,RP6

271611330301 RP;33*4 ,8P ,1/16W,5% ,0612,SMT RP43,RP528

271571330301 RP;33*8 ,16P ,1/16W,5% ,1606,SM RP21,RP22,RP23,RP24,RP25

271611472301 RP;4.7K*4,8P ,1/16W,5% ,0612,SMT RP36,RP46,RP47,RP511,RP5

271621472303 RP;4.7K*8,10P,1/16W,5% ,1206,SMT RP514,RP519

271621471301 RP;470*4,8P,1/16W,5%,1206,SMT RP7

271621473301 RP;47K*8 ,10P,1/16W,5% ,1206,SMT RP513,RP517

271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP5

271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP502

271621822302 RP;8.2K*8,10P,1/32W,5% ,1206,SMT RP37,RP38,RP39


179


Part Number Description Location(S)345671600002 RUBBER PAD;LCD,LOWER,8175

345671600001 RUBBER PAD;LCD,UPPER,8175

345503400001 RUBBER;2MM,ROUND,STINGRAY

565167170001 S/W;CD ROM,SYSTEM DRIVER,8575

340671200013 SCREW ASSY;CPU,8170

340671200014 SCREW ASSY;IC,82845,8170

371102011502 SCREW;M2L15,FLT(+),NIW/NLK

340671750002 SHIELDING ASSY;TOP,ID3,8575A

341671700001 SHIELDING;AUDIO,8575

333050000119 SHRINK TUBE;600V,105'C,D0.8*6MM,

333050000120 SHRINK TUBE;600V,105'C,D0.8*9MM,

333050000107 SHRINK TUBE;UL,600V,105'C,ID2.5*



333050000098 SHRINK TUBE;ULCSA,125'C,D0.7MM,B

561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY&

361400003021 SOLDER CREAM;NOCLEAN,P4020870980

370102610302 SPC-SCREW;M2.6L3,NIB,K-HD,NYLOK

370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK

370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK

370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK



370102010309 SPC-SCREW;M2L3.0,NIW/NLK,HD07

370102010407 SPC-SCREW;M2L4,K-HD,NIB/NLK

Part Number Description Location(S)370102010407 SPC-SCREW;M2L4,K-HD,NIB/NLK

370102010401 SPC-SCREW;M2L4,NIB,FLT(+),NL,731

370102010606 SPC-SCREW;M2L6,K-HD(t0.2),NIB/NL

370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3

370103010604 SPC-SCREW;M3L6,NIB,K-HD,t0.8,NYL

340671700003 SPEAKER ASSY,L,8575

340671700008 SPEAKER ASSY;R,8575

226600030149 SPONGE/2ADHESIVE;CR-RUBBER/G9000

226600030058 SPONGE;CR,T=1.5MM,W=8MM,PRC

377244010002 STANDOFF;#4-40DP3.5H5L5.5,NIW

341668300008 STANDOFF;MDC MODEM,NLK,HOPE

297120101007 SW;DIP,SPST,4P,24VDC,.025A,SMT SW503

297120100008 SW;DIP;SPST,8P,24VDC,25MA,SMT,FH SW6

297040105012 SW;PUSH BUTTOM,4P,SP,12V/50MA,H2 SW1,SW2,SW3,SW4,SW5,SW

297040105012 SW;PUSH BUTTOM,4P,SP,12V/50MA,H2 SW502

297040105010 SW;PUSH BUTTOM,5P,SPST,12V/50MA, SW1,SW2,SW3,SW4

297030102001 SW;TOGGLE,SPST,5V/0.2mA,H10.7MM, SW1

225600000309 TAPE;3M-467/DOUBLE RELEASE PAPER

225600000032 TAPE;ACETURM ADHESTIVE,W=4mm,BLK

225600000032 TAPE;ACETURM ADHESTIVE,W=4mm,BLK

225600000034 TAPE;ACETURN ADHESI,W=10mm,PRC

225600000061 TAPE;ADHENSIVE,DOUBLE-FACE,W20,U

225600000310 TAPE;ADHENSIVE,DOUBLE-FACE,W8,UL

622200000008 TAPE;CARTON,2.5"W,30M/RL,PRC

225671700006 TAPE;CONDUCTIVE,20X20,PLATE,KB


180


Part Number Description Location(S)225671700009 TAPE;CONDUCTIVE,BTM SHD,ESD,8575

225671700008 TAPE;CONDUCTIVE,KB COVER,ESD,857

225671700007 TAPE;CONDUCTIVE,KB,ESD,8575

225600000375 TAPE;CONDUCTIVE/DOUBLE RELEASE P

225600000004 TAPE;DOUBLE SIDE,12MM*15M

225600000237 TAPE;G9000,W=110,PRC

225600000312 TAPE;G9000,W=113,PRC

225600000344 TAPE;G9000,W=220,PRC

225600000268 TAPE;G9000,W=72,PRC

225600000054 TAPE;INSULATING,POLYESTER FILM,1

225600000027 TAPE;INSULATOR,W10T0.06,UL-510

225600000143 TAPE;SONY G9000,W=10,T=0.15,PRC

225600000177 TAPE;T=0.05MM,W=7MM,KAPTON/ADHES

333334000046 TERMINAL;HRS/DF13-2630SCF,PRC

333334000046 TERMINAL;HRS/DF13-2630SCF,PRC

333334000084 TERMINAL;JAE/FI-C3-A1-15000,PRC

333334000099 TERMINAL;JST/SSH-003T-P0.2,PRC

346671750001 THERMAL PAD;MOS,ID3,8575A

345671700003 THERMAL PAD;SIS301,8575

310111103013 THERMISTOR;10K,1%,RA,DISK,103AT-

442164900010 TOUCH PAD MODULE;TM41PD-350

288227002006 TRANS;2N7002LT1,N-CHANNEL FET,ES PQ10,PQ4,PQ504,PQ505,PQ

288227002001 TRANS;2N7002LT1,N-CHANNEL FET,SO PQ2,PQ501,PQ502,PQ503

288227002001 TRANS;2N7002LT1,N-CHANNEL FET,SO Q3,Q4,Q501,Q502,Q505,Q50

628820014401 TRANS;DTA144EKA,PNP,100MA,50V,SO

Part Number Description Location(S)288200144002 TRANS;DTA144WK,PNP,SMT PQ506,Q529

288200114001 TRANS;DTC114TKA,10K,N-MOSFET,SOT Q13

288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23 Q10,Q11,Q17,Q18,Q19,Q2,Q

288200144001 TRANS;DTC144WK,NPN,SOT-23,SMT PQ509,Q20,Q5,Q510,Q9

288206612003 TRANS;FDD6612A,30V,30A,.028hm,N- PU501,PU502,PU515,PU516

288206676004 TRANS;FDD6676,30V,78A,.0085hm,N- PU1,PU2,PU3,PU4,PU5,PU6

288202222001 TRANS;MMBT2222AL,NPN,TO236AB PQ3

288203904010 TRANS;MMBT3904L,NPN,Tr35NS,TO236 PQ511,Q12,Q15,Q516,Q517,

288203906002 TRANS;MMBT3906L,40V,200mA,SOT23,

288203906018 TRANS;MMBT3906L,PNP,Tr35NS,TO236 Q14

288207002001 TRANS;NDC7002N,N-MOSFET,SSOT-6 PQ2

288202301001 TRANS;SI2301DS,P-MOSFET,SOT-23 PQ1

288202301001 TRANS;SI2301DS,P-MOSFET,SOT-23 Q1,Q509,Q511,Q6,Q8

288202302001 TRANS;SI2302DS,N-MOSFET,SOT-23 Q534

288204416001 TRANS;Si4416DY,N-MOSFET,.028OHM, PU2,PU5

288204416001 TRANS;Si4416DY,N-MOSFET,.028OHM, PU507,PU509

288204425002 TRANS;SI4425DY,PMOS,8.5A/30V,0.0 PU502

288204425002 TRANS;SI4425DY,PMOS,8.5A/30V,0.0 PU512,PU513

288204425002 TRANS;SI4425DY,PMOS,8.5A/30V,0.0

288204532001 TRANS;SI4532DY,N&P-MOSFET,SO8,PR

288204788001 TRANS;SI4788CY,P-MOS,5A1.8~5.5V, PU504,PU505

288204810001 TRANS;SI4810DY,N-MOS,.0155OHM,SO PU3,PU6

288204810001 TRANS;SI4810DY,N-MOS,.0155OHM,SO PU7,PU8

288204835001 TRANS;SI4835DY,PMOS,6A/30V,.035, PQ1

288204925001 TRANS;SI4925DY,P-MOSFET,SO-8 PU9


181


Part Number Description Location(S)288209410001 TRANS;SI9410DY,N-MOSFET,.04OHM,S Q503

273001050039 TRANSFORMER;10/100 BASE,LF-H80P, U3

271911103906 VR;10K,20%,0.05W,RN101GAC10KPGJ- VR1

421671700002 WIRE ASSY;ANTENNA,8575

421668300005 WIRE ASSY;BIOS,BATTERY,HOPE J508

421671600010 WIRE ASSY;INVERT,8175

421671700004 WIRE ASSY;MDC,EMI,8575

421671700001 WIRE ASSY;TOUCHPAD,8575

332110020057 WIRE;#20,UL1007,122MM,RED,PRC

332110020028 WIRE;#20,UL1007,50MM,RED,PRC

332110020050 WIRE;#20,UL1007,55MM,BLK,PRC

332110020020 WIRE;#20,UL1007,BLK,PRC

332110020019 WIRE;#20,UL1007,RED,PRC

332110020019 WIRE;#20,UL1007,RED,PRC

332110026096 WIRE;#26,UL1007,165MM,WHITE,PRC

332110026097 WIRE;#26,UL1007,55MM,BLACK,PRC

332110026099 WIRE;#26,UL1007,93MM,YELLOW,PRC

332110026008 WIRE;#26,UL1007,BLACK,PRC

332110026016 WIRE;#26,UL1007,WHITE,PRC

332110026013 WIRE;#26,UL1007,YELLOW,PRC

332110030058 WIRE;#30,UL1571,OD0.6mm,BLACK,PR

332110030052 WIRE;#30,UL1571,OD0.6mm,BLUE,PRC

332110030059 WIRE;#30,UL1571,OD0.6mm,BROWN,PR

332110030055 WIRE;#30,UL1571,OD0.6mm,GREEN,PR

332110030050 WIRE;#30,UL1571,OD0.6mm,GREY,PRC

Part Number Description Location(S)332110030057 WIRE;#30,UL1571,OD0.6mm,ORANGE,P

332110030060 WIRE;#30,UL1571,OD0.6mm,ORANGE/B

332110030053 WIRE;#30,UL1571,OD0.6mm,PURPLE,P

332110030056 WIRE;#30,UL1571,OD0.6mm,RED,PRC

332110030051 WIRE;#30,UL1571,OD0.6mm,WHITE,PR

332110030054 WIRE;#30,UL1571,OD0.6mm,YELLOW,P

332110032036 WIRE;#32,1571,BLACK/RED/#28,DRAI

332110032014 WIRE;#32,UL1571,BLK,PRC

332110032006 WIRE;#32,UL1571,BLK/WHT,PRC

332110032005 WIRE;#32,UL1571,BROWN/WHT,PRC

332110032002 WIRE;#32,UL1571,GRAY,PRC

332110032003 WIRE;#32,UL1571,ORANGE/BLK,PRC

332110032004 WIRE;#32,UL1571,RED/WHT,PRC

332110032001 WIRE;#32,UL1571,WHT,PRC

273001050062 XSFORMER;CI8.5,SIT16260,16/2600T

274011431408 XTAL;14.318M,50PPM,32PF,7*5,4P,S X502

274011431422 XTAL;14.318MHZ,16PF,20PPM,8*4.25 X501

274011600408 XTAL;16MHZ,16PF,50PPM,8*4.5,2P X503

274012457405 XTAL;24.576M,50PPM,16PF,7*5,4P,S X6

274012500401 XTAL;25MHZ,30PPM,18PF,4P,SMT X1,X4

274013276103 XTAL;32.768KHZ,20PPM,12.5PF,CM20 X5


PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

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A

A

B

B

2 2

1 1

DRAW DESIGN CHECK ISSUED

MODEL : 8575 A Revision 01

-REQ0/-GNT0CHIP

INTB#

IDSELAD20

REQ/GNT

CHIPINTA#

CHIP

INTC#

PCIINT

TI1410

X

X

X

LOW

STR

LOW

-SUSC HIGH

X+5V

+12V O

O

+5V

+12V

+5VA

X

+12V

+1.8V

X+3V

+3.3V

STATESTD

O

O

O

X

O

+1.8V

X

+2.5V_DDR

+VCC_CORE

+3VS

LOW

OADP

+5VS

X

HIGH

X

X

O

O

+5V

VOTAGE

O

HIGH

MEC-OFF

O

LOW

O

0

O+3.3V

O

O

0

LOW

-SUSB

O

+3VA

+VCC_RTC

O

X

O

-

OO

+12VS

BATTERY

O

O

X

X

FULL ON

X

X X

SIGNAL

POWER STATES

X

O

REMARK

O

+1.75V

0

XO

+19V

O

-

O

O

O

+12V

+2.5V

IDSEL BUS MASTER

PCIINTSIS 650PCMCIA (TI1410)

+1.8V

+1.8VS O X X X

XXOO

+3.3V

+3.3V

O

ContextsTitle Page

P4-CPU (1/2)P4-CPU (2/2)SIS650(1/3)

SIS961(2/3)

IDE INETRFACE

SIS650(3/3)

SIS961(1/3)

PCI 1410 / PU2211

23456789

101112

System Block Diagram1

13

SUPER I/O, T/P & BUTTON

14151617

Power Block Diagram

DDR SODIMMs

192021

SIS961(3/3)

18

MICROCONTROLLER (H8) 22

SIS650(2/3)

23BATTERY CONNECT AND +1.25V

COVER SHEET & SCREW HOLE

TV/LVDS ENCODER(SiS301LV)LCD/VGA INTERFACE & LEDsMAIN CLOCK & CLOCK BUFFER

DDR TERMINATION

LAN PHY (ICS 1893) & MDCAUDIO CODEC & AUDIO AMP

2.5v_DDR / +1.8VSCHARGERCPU CORE

242526

1394 (UPD72872)

TI1410

272829

D/D CONNECTORMINI PCI SLOTNEC UPD72872 IEEE1394

AD22 1394 (UPD72872) -REQ1/-GNT1 1394 (UPD72872)

+5V

Revision 30

01

8575A COVER SHEET & SCREW HOLE

1 30Monday, June 17, 2002

C BD 311671750001 & TU 411671750012

Title

Size DocumentNumber

Rev

Date: Sheet of

+1.8VS

+3VS+3VS

+3V+5VS

+3V

AGND

MTG20ID4.9/OD7.6

1

E9TOUCHPAD_METAL10

1

E502TOUCHPAD_METAL10

1

E10TOUCHPAD_METAL10

1


1

MTG17ID2.8/OD6.0

456

7 9

10

1238

111213


1


1

TP514TOUCHPAD_METAL8

1

MTG6ID3.0/OD4.0

1

MTG12ID3.0/OD4.0

1

MTG32ID3.0/OD4.0

1

MTG7ID3.2/OD6.0

1

�FD501FIDUCIAL-MARK

1

�FD1FIDUCIAL-MARK

1 ��FD2FIDUCIAL-MARK

1


1��FD503FIDUCIAL-MARK

1

E4TOUCHPAD_METAL10

1

�FD4FIDUCIAL-MARK

1TP507TOUCHPAD_METAL8

1

MTG13ID3.0/OD6.0

1

MTG11ID3.0/OD6.0

1


1

�FD3FIDUCIAL-MARK

1

MTG9ID3.2/OD6.0

1

MTG8ID3.2/OD6.0

1

EC5010.1U/NA

50V0603

12

EC5020.1U/NA

50V0603

12

EC20.1U/NA

50V0603

12

TP505TOUCHPAD_METAL8

1

MTG22ID2.8/OD7.6

456

7 9

10

1238

1112


1

MTG10ID3.0/OD6.0

1


1

MTG5ID2.8/OD7.6

456

7 9

10

1238

1112

E5TOUCHPAD_METAL10

1

MTG21ID2.8/OD7.6

456

7 9

10

1238

1112


1


1

MTG3ID2.8/OD7.6

456

7 9

10

1238

1112


1

E1TOUCHPAD_METAL10

1

MTG14ID2.8/OD7.6

456

7 9

10

1238

1112

E2TOUCHPAD_METAL10

1


1

E7TOUCHPAD_METAL10

1

E8TOUCHPAD_METAL10

1

MTG4ID2.8/OD6.5

456

7 9

10

1238

1112

MTG15ID2.8/OD6.0

456

7 9

10

1238

111213

MTG16ID2.8/OD6

4

5 6

7

12

3 8

A

A

B

B

2 2

1 1

SO-DIMM

TPS211

SSOP 16

AD

[0..3

1]

PCMCIA

PCI 1410CONTROLLER

Con

trol

uBGA 144

PCI BUS

Micro-FCPGA 479 pin

8575 A System Block Diagram

Primary EID

E (HD

D)

USB

Secondary EIDE

(CD

RO

M/D

VD)

Audio CodecAC Link

Amplifier

H8-3437S Keyboard

Touch PAD

Cover Switch

JACK

M.D.C.Connect

Power Button

FAN1 For CPU

-HD

[0..6

3]

-HA

3..3

1]

Con

trol

Pentium 4

A[0

..25]

D[0

..15]

IC CARDSocket

Con

trol

16MHz

ADM 1032

PQFP 100

Realtek ALC201PQFP 48

TPA 0202

C.P.U.

Micro Controller

Power Switch

Thermal Recorder

SPDIF

RJ-11

InternalSpeaker

InternalMicrophone

ExternalMicrophone

AD

[0..3

1]

Con

trol

RJ-45Connector

EEPROMNM24C02N

(30 pin)

TQFP 100PIN

PC87393

Willamette/Northwood

FAN2 For D/D

Super I/O

LPC

ISA BUS

Flash ROM512KB

PLCC 32

PRINTERPORT

HP-3600IR Module

4

1

5

5

MINI 1394CONNECTOR

HUB[0..11]

Con

trol

13

Sis 650

200 Pin DDR SO-DIMM Socket*2DDR SDRAMMemory Bus / 266MHz

SDRAM

HOST

Hyper Zip

AGP

LocalMemory

TV

Pannel

CRT

HyperZipData Bus 266MHz512MB/sec

SiS 961

LAN PHY10/100 MICS1893

DUAL USB

LAN

AC'97

USB

LPC

IDE

HyperZipPCI

FWH

FWH82802

702-Balls BGA

TV

LVDS

SIS301LV

128-pin LQFP

371-Balls BGA

MII

Ultra DMA 33/66/100

Ultra DMA 33/66/100

PC2100/PC1600IEEE 1394

AD

[0..3

1]

Con

trol

NECUPD72872PQFP120

AD

[0..3

1]

Con

trol

MINI PCISLOT

Pentiun 4 Processor-M

DDR ClockGeneratorICS93722

ClockGenerator

ICS952001

Fan 2

Fan 1

InternalKeyboard

Touch Pad

Mic-inConnector

Speed Step!

VIDD/D Power Components

HDDCD-ROMDVD-ROMCD-RWCombo

DDRAM Slot * 2(200PinsSO-DIMM)

H8-3437

01

8575A SYSTEM BLOCK DIAGRAM


BD 311671700001 & TU 411671700011

Title

Size DocumentNumber

Rev

Date: Sheet of

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

POWER DIAGRAM OF THE PROJECT 8575

PWRJACK

SI4835DY

MAX4173FEUT

+5VAS

2N7002LEARNING

VMAIN

MAX1632

PWR_ON

ALWAYS

LP2951 SI2301DS

H8_AVREF1

SI2301DS

+5VA

DTC 144WK SW_+5VA

H8F3437

SI4788+5V +5VS

SI2301

SI4788

+12V +12VS

+3V +3VS

PSON

MAX809

LTC1628CG

-SUSC

+2.5V_DDR

+1.8VS

PWR_ON

LTC1709EG

CPU_CORE_EN

H_PWRGD

-POWERBTN

SIS_PWRBTN

SIS961H8_PWRON

SIS650

1

+VCC_CORE

2

2 3

4

5

+VCC_RTC

BATOKcircuit

BATOK

RTC BAT

BATOK

AUXOKcircuit

AUXOK

CPU

AUXOK

CPUPWRGD

PSON#-SUSC

MIC5248

+5VS

視線輔助線

電子訊號線

+VCC_RTCcircuit

+VCC_RTC

SIS_PWRBTN#

+3VS

PWROK

S3AUXSW#

3

4

6

PSON

PSON

PSON

LEVEL SHIFT-SUSB

H8_PWROK

BD 311671700001 & TU 411671700011 01

8575A POWER BLOCK DIAGRAM


Title

Size DocumentNumber

Rev

Date: Sheet of

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PLL SUPPLY FILTERGTL Reference CKT

One 220PF for each GTL REF Pin

PLACE THESE INSIDE SOCKET CAVITY

PRECISION FSB COMPENSATION RESISTORS

REQUEST NEW PART NUMBER FOR 51.1 Ohm, 1%

PLACE CLOSE TO CPU SOCKET

PLACE AT CPU END

CPU SIGNAL TERMINATION

1.5" MAX.

Close to CPU socket

PLACE AT CPU END

DESIGN GUIDE PAGE 236DESCRIPTION(NO extra pull-upresistors required)

PLACE CLOSE TO J515

CP1812_7243 SHAPE

1

1

0

1

0.6

0

0.875

1

0.8

1

1

0

0

1

11

0

1.601.65

1

0

1

0.7

0

00

1.45

1.15

0.825

1

0

0

1

1

1

1

0

0.75

1

0

0

0

1

0

1

0

0

0

0.85

0

1

0

1

1

0

VID2

1

0

1.70

0

1.100

1

1.350

1

1

1

1

1

VID0

0

0 1

0

1.40

0

0

0

0

1

0

1

1

1.25

0 0

0

1.50

0

1

1

1

01

0

11

VID3

1

0

0

1

0

1

0

10

1 01

0

0.925

1

1

VID4

1

0

1

1

1

1

1

1.000

11

1

10

0

10

1.2000

1

1

0

0

0

0

0

0.725

1

1

1

0

0

0

VOLT.

0

1

0.950

VID1

1.75

1

0

0

0

0 1

1.050

0.651

0.9

1

0

0.975

1

01

1

0

10

1 1

0

1

1.30

1

1.55

1

0

0

0.775

0

0

0

0

10.675

0

00

1

0

1

0

0.625

BD 311671700001 & TU 411671700011 01

8575A PENTIUM4 (1/2)


Title

Size DocumentNumber

Rev

Date: Sheet of

HA#3HA#4HA#5HA#6HA#7HA#8HA#9HA#10HA#11HA#12HA#13HA#14

HA#18HA#17HA#16HA#15



HA#31

HA#27

HA#30

HA#28

H_REQ#4H_ADSTB#0H_ADSTB#1

HA#29

HA#[3..31]

H_REQ#3H_REQ#2H_REQ#1H_REQ#0

H_ADS#

H_BNR#

TESTHI8TESTHI9TESTHI10H_BR#0

H_BPRI#

H_DBSY#H_DEFER#H_DRDY#H_HIT#H_HITM#

H_INIT#

H_LOCK#

H_RS#2CPURST#

H_RS#1H_RS#0

H_TRDY#

HD#31HD#30HD#29HD#28HD#27HD#26

HD#24HD#25

HD#23HD#22

HD#20HD#21

HD#19

HD#17HD#16

HD#18

HD#15HD#14

HD#12HD#13

HD#11

HD#9HD#8

HD#10

HD#5HD#4

HD#0HD#1

HD#7

HD#3

HD#6

HD#2

HD#32HD#33HD#34HD#35HD#36HD#37

HD#39HD#38

HD#40HD#41

HD#43HD#42

HD#44

HD#47

HD#45HD#46

HD#48HD#49

HD#51HD#50

HD#52

HD#55

HD#53HD#54

HD#60

HD#58

HD#63

HD#57HD#56

HD#62HD#61

HD#59

H_REQ#[0..4]H_RS#[0..2]

DBI#0DBI#1DBI#2DBI#3

DSTBN#0DSTBN#1DSTBN#2DSTBN#3

DSTBP#0DSTBP#1DSTBP#2DSTBP#3

DBI#[0..3]

DSTBN#[0..3]

DSTBP#[0..3]

H_COMP0

H_COMP1

H_INIT#

HD#[0..63]

-ITP_TRST

CPUPWRGD

H_BR#0

CPURST#

TESTHI8

-H_BMP1_ITP

-H_BMP0_ITP

ITP_TDI

TESTHI9TESTHI10

TESTHI5TESTHI4

TESTHI7TESTHI6

TESTHI0

TESTHI2TESTHI1

TESTHI3

-THRMTRIP

PLL_VSSA

H_IGNNE#

VID4_R

HCLK_CPU

H_SMI#H_NMI

H_STPCLK#

VID1_R

PLL_VCCA

PLL_VSSA

H_A20M#

VID3_R

PLL_VCCA

H_INTR

CPU_THERMDA

-H_BPM4_PRDY

VID0_R

CPU_THERMDC

HCLK_CPU#

H_GTLREF2_3

H_FERR#

-THRMTRIP

CPU_GTLREF

VID2_R

H_FERR#

VCCIO_PLL

VCCIO_PLL

VID0VID1VID2VID3

VID0_RVID1_RVID2_RVID3_R

VID4_RVID4

VID[0..4]

CPURST#

-H_BMP0_ITP

-H_BPM4_PRDY

-H_BPM5_PREQ

CPU_THERMDA

CPU_THERMDC

DBR#

ITP_CLK0ITP_CLK1

ITP_CLK0ITP_CLK1

H_FERR#

H_INTR

H_STPCLK#

G_LO/HI#H_DPSLP#

H_NMI

H_A20M#

H_IGNNE#H_SMI#H_SLP#

-H_BMP1_ITP

ITP_TMS

ITP_TCK

ITP_TDO

-H_BPM5_PREQ

-H_PROCHOT

H_DPSLP#

H_COMP1

TESTHI2

TESTHI5

TESTHI0

TESTHI3

SLP#-H_PROCHOT

SKTOCC#

CPUPWRGDTESTHI1

DBR#

-H_BMP0_ITP

H_COMP0

TESTHI6

-ITP_TRST

-H_BMP1_ITP

ITP_TDO

ITP_TCK

ITP_TMS

TESTHI7

-H_BPM4_PRDY

TESTHI4

-H_BPM5_PREQ

ITP_TDI

H_GTLREF2_3

CPU_GTLREF

+VCC_CORE+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

GND

GND

+3VS

+3VS

GND

+VCC_CORE

+3VS

+VCC_CORE

GND

L34.7UH2012

12

R63200 06031 2

L24.7UH2012

12

+ C21

33U16V

7343

20%12

+C22

33U16V

7343

20%12

R526510603

12

R277

4700603D

1 2

R5201K 0603

1 2

R11620603

12

R527510603

12

R1351/NA0603

12

TP512 1

TP502 1

R529510603

12

U1A

WMT478/NWD_14BGA_PGA479_SKT

G1AC1V5AA3G2

L25K26K25J26

U6W4Y3H6

D2

H5E2H2F3E3

AC3

W5

G4

V6

AB25F4G5F1AB2J6

N5N4N2M1N1M4M3L2

M6L3K1L6K4K2

L5H3J3J4K5J1

AB1Y1

W2V3

U4T5

W1R6V2T4U3P6U1T2R3P4P3R2T1

R5

ADS#AP#0AP#1

BINIT#BNR#

DP#3DP#2DP#1DP#0

TESTHI8TESTHI9

TESTHI10BR#0

BPRI#

DBSY#DEFER#

DRDY#HIT#

HITM#

IERR#

INIT#

LOCK#

MCERR#

RESET#RS#2RS#1RS#0RSP#

TRDY#

A#16A#15A#14A#13A#12A#11A#10A#9A#8A#7A#6A#5A#4A#3

ADSTB#0REQ#4REQ#3REQ#2REQ#1REQ#0A#35A#34A#33A#32

A#31A#30A#29A#28A#27A#26A#25A#24A#23A#22A#21A#20A#19A#18A#17

ADSTB#1

TP501

1

R5346800603

12

U1C


AD6AD5A6L24P1

AB4AA5Y6AC4AB5AC6

AD24AE25AD25

AA6F6AA21F20

AC23AC24AC20AC21AB22AA20

AA2AB23C3AB26

D4C1D5F7E6

AF22AF23AC26AD26

C6B6B2

D1E5B5Y4

AE1AE2AE3AE4AE5

AF2

AF4AD20

A5AE23AD22

A4

AE21A22A7B3C4A2

AD3AF25AD2

AF24

AF3

AF26

BSEL0BSEL1

TESTHI11COMP0COMP1

BPM#5BPM#4BPM#3BPM#2BPM#1BPM#0

TESTHI0DBR#

TESTHI12

GTLREF3GTLREF2GTLREF1GTLREF0

TESTHI5TESTHI4TESTHI3TESTHI2TESTHI7TESTHI6

TESTHI1PWRGOODPROCHOT#

SLP#

TCKTDI

TDOTMS

TRST#

BCLK0BCLK1ITP_CLK0ITP_CLK1

A20M#FERR#IGNNE#

LINT0LINT1SMI#STPCLK#

VID4VID3VID2VID1VID0

VCC

VCCVIDVCCAVCCSENSEVCCIOPLLVSSAVSSSENSE

RSVDRSVDRSVDTHRMDATHRMDCTHRMTRIP#

RSVDRSVDRSVDRSVD

RSVD

SKTOCC#

R531

0/NA0603

12

R533

49.9 06031%

1 2

RP507

1K*8 1206

12345 6

78910

R24810 06031 2

R521

51.1 06031%

1 2

U2

ADM1032SO8

1

23

4

87

65 VDD

D+D-

THEPM

SCLKSDATA

ALERTGND

RP2

1K*8 1206

12345 6

78910

RP506

0*4 1206

1234

8765

R246200 06031 2

R5081500603

12

R2754700603D

12

R535

49.9 06031%

1 2

R524

2000603

12

TP11

R52210006031%

12

R14

51.1 06031%

1 2

R600 0603

1 2

C5461U08055%

12

C550220P06035%

12

R530510603

12

C549220P06035%

12

Q12MMBT3904L

B

EC

R53610006031%

12

TP5201 R247

10 06031 2

R750200 06031 2

R10620603

12

R751200 06031 2

C232200P

0603D

12

R754200 06031 2

RP310K*41206

1234

8765

C519220P06035%

12

R748200 06031 2

R528

6206031%

12

R504150/NA0603

12

R276561%0603D

12

R123010603

12

R514510603

12

C240.1U

50V0603

12

R512510603

12

C520220P06035%

12

R532390603

12

R5070 0603

1 2

TP21

R525750603

12

C5211U08055%

12

R752200 06031 2

R5061.5K/NA06031%

12

R749200 06031 2

R516510603

12

R5031500603

12

R2673000603D

12

R523510603

12

R753200 06031 2

R515510603

12

R513510603

12

R5092706031%

12

TP503

1

TP504

1

Q7MMBT3904L

B

EC

U1B


M23N22P21M24N23M26N26N25R21P24R25R24T26T25T22T23

P26

R22

P23

U26U24U23V25U21V22V24W26Y26W25Y23Y24Y21AA25AA22AA24

V21

W22

W23

B21B22A23A25C21D22B24C23C24B25G22H21C26D23J21D25

E21

E22

F21

H22E24G23F23F24E25F26D26L21G26H24M21L22J24K23H25

G25

K22

J23

D#32D#33D#34D#35D#36D#37D#38D#39D#40D#41D#42D#43D#44D#45D#46D#47

DBI#2

DSTBN#2

DSTBP#2


DBI#3

DSTBN#3

DSTBP#3


DBI#0

DSTBN#0

DSTBP#0


DBI#1

DSTBN#1

DSTBP#1

HA#[3..31]6

HD#[0..63]6

H_REQ#[0..4]6

H_ADSTB#06H_ADSTB#16

H_ADS# 6

H_BNR# 6

H_BPRI# 6

H_BR#0 6

H_DBSY# 6

H_DRDY# 6

H_LOCK# 6

H_TRDY# 6

CPURST# 6

H_INIT# 15

H_HIT# 6H_HITM# 6

H_RS#[0..2] 6

DBI#[0..3]6

DSTBN#[0..3]6

DSTBP#[0..3] 6

H_DEFER# 6

H_STPCLK#15H_SMI#15H_NMI15

HCLK_CPU11

H_INTR15

VCCPVID5

H_IGNNE#15

H_A20M#15H_FERR#

HCLK_CPU#11

-THRMTRIP22

VID[0..4]26

VCC_SENSE26

VSS_SENSE26

SCL_THRM 22

-THERM_ERR 22

SDA_THRM 22

H_961_FERR#15

CPUPWRGD 6

CPU_DPSLP# 15

G_LO/HI# 15

H_SLP# 15

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

0603/0805CO-LAYOUT

Place these caps atCPU north side Place these caps at

CPU south side

Place these caps atCPU solder side

BD 311671700001 & TU 411671700011 01

8575A PENTIUM4 (2/2)


Title

Size DocumentNumber

Rev

Date: Sheet of

VCCPVID

+VCC_CORE

+VCC_CORE

+5VS +5VS

+VCC_CORE

+VCC_CORE+VCC_CORE

+VCC_CORE

+5VS

C53310U

10V1206

12

C55710U

10V1206

12

C2010U

10V1206

12

C53710U

10V1206

12

C1810U

10V1206

12

C1510U

10V1206

12

C51610U

10V1206

12

C55410U

10V1206

12

C1122U

10V1210

12

C55522U

10V1210

12

C51710U

10V1206

12

U502

MIC5248SOT25

1

23

4

5

IN

GNDEN

PG

OUT

C1210U

10V1206

12

C510U

10V1206

12

C52910U

10V1206

12

C52510U

10V1206

12

R89400603

12

C54310U

10V1206

12

C54510U

10V1206

12

C51510U

10V1206

12

C810U

10V1206

12

C52710U

10V1206

12

C52310U

10V1206

12

C52810U

10V1206

12

+C17150U

10V7343

12

C52610U

10V1206

12

+C9150U

10V7343

12

C1010U

10V1206

12

R51710K0603

12

C54410U

10V1206

12

C53410U

10V1206

12

C51210U

10V1206

12

C1910U

10V1206

12

C54210U

10V1206

12

C53910U

10V1206

12

C710U

10V1206

12

C5140.1U

50V0603

12

C51810U

10V1206

12

C6010.1U/NA

50V0603

12

C55310U

10V1206

12

C5480.1U

50V0603

12

C5320.1U

50V0603

12

C5520.1U

50V0603

12

C5300.1U

50V0603

12

C1610U

10V1206

12

C5360.1U

50V0603

12

C5400.1U

50V0603

12

C130.1U

50V0603

12

C5380.1U

50V0603

12

C5470.1U

50V0603

12

C5310.1U

50V0603

12

C5131U0603

12

C54110U

10V1206

12

U1D


AE7AE24AE22AE19AD14AD12AD10AD8AD4AD1AD23AD21AE17AE15AE13AE11AE9AE26AB20AC17AC15AC13AC11AC9AC7AC5AC2AC25AC22AC19AD18AD16AA4AA1AA23AA19AB18AB16AB14AB12

N6N3

N24N21

P5P2

P25P22R26R4R1

R23T6T3

T24T21U5U2

U25U22V26G21H26H4H1

H23J5J2

J25J22K6K3

K24K21L26L4L1

L23M5M2

AB10AB8AB6AB3AB24AB21V4V1V23W6W3W24W21Y5Y2Y25Y22AA17AA15AA11

M25M22E11E9

E26E7E4E1

E23E19F18F16F14F12F10F8F5F2

F25F22 AA9

AA26AA7

G6G3

G24

C5

C2

C25

C22

C19

D18

D16

D14

D12

D10

D8

D6

D3

D24

D21

D20

E17

E15

E13

A3 A24

A21

A19

B18

B16

B12

B10

B26

B8 B4 B23

B20

C17

C15

C13

C11

C9

C7

AF18

AF16

AF14

AF12

AF10

AF8

AF6

AF1

AF20

A17

A15

A13

A11

A9 A26

AD11

AD9

AD7

AE18

AE16

AE14

AE12

AE10

AE8

AE6

AE20

AB15

AB13

AB11

AB9

AB7

AB19

AC18

AC16

AC14

AC12

AC10

AC8

AD17

AD15

AD13

E14

E12

E10

E8 E20

F17

F15

F13

F11

F9 F19

AA18

AA16

AA14

AA12

AA10

AA8

AB17

B13

B11

B9B7 B19

C18

C16

C14

C12

C10

C8

C20

D17

D15

D13

D11

D9

D7

D19

E18

E16

AF17

AF15

AF13

AF11

AF9

AF7

AF5

AF21

AF19

A18

A16

A14

A12

A10

B17

B15

A20

A8 AD19

AA13

B14

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS VSS

VSSVSS

VSSVSSVSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

C55610U

10V1206

12

C1410U

10V1206

12

C52410U

10V1206

12

C55110U

10V1206

12

C53510U

10V1206

12

C51122U

10V1210

12

C622U

10V1210

12

VCCPVID 4

CPU_CORE_EN 26

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

A A

B B

C C

D D

60 OHM 1%

112 OHM 1%

SIS650(1/3)

Place thiscap under650 solderside

BD 311671700001 & TU 411671700011 01

8575A SIS650 (1/3)

C


Title

Size DocumentNumber

Rev

Date: Sheet of

AGPRCOMP

HVR

EF

HPCOMP

HNCOMP

VBDEVADE

CPUAVSS

CPURST#

VAD

1

VAD

9

DSTBP#2

AGPRCOMP

HD

#18

HD

#39

HD

#41

HA#6

HA#19

VAD

6

VBD

7

DBI

#1

HD

#9

HD

#31

HD

#34

HD

#47

HA#31

H_ADSTB#0

H_RS#[0..2]

BGCLK#

AGCLK#

HD

#12

HD

#59

HA#4

HA#27

HA#30

H_HIT#

PHYAVSS

VBD

E

HD

#1

HD

#4

HD

#6

HD

#32

HD

#45

HA#17

HA#28

H_RS#0

VAD

0

VBD

8

VBD

6

AGPVREF

HD

#10

HD

#48

HD

#53

HA#8

H_REQ#2

BVSY

NC

DBI

#2

HD

#0

HD

#13

HD

#15

HA#12

H_RS#2

DSTBP#[0..3]

AGPAVSS2

DSTBP#1

HD

#21

HD

#25

HD

#26

HD

#43

HD

#58

H_ADSTB#1

H_REQ#0

H_REQ#3

DBI#[0..3]

CPUPWRGD

VBD

9

AHSY

NC

VAD

10

HN

CVR

EF

HD

#42

HA#15

AGPAVDD1VA

D3

VBD

11

VBD

4

PHYA

VDD

CPU

AVD

D

DSTBN#1

DBI

#3

HD

#11

HD

#19

HD

#22

HD

#50

HD

#51

HD

#54

HD

#56

HA#5

BHSY

NC

VAD

E

VAD

5

BGCLK

HD

#7

HD

#24

HD

#63

H_DBSY#

DSTBN#[0..3]

PHYAVDD

HNCVREF

PHYA

VSS

AGPAVSS1

HD

#27

HD

#38

HD

#40

HD

#46

HD

#49

HD

#52

H_REQ#4

H_DEFER#H_LOCK#

VBD

10

VBD

2

HPC

OM

P

HD

#3

HD

#14

HD

#16

HD

#33

HD

#60

HD

#62

HA#20HA#21

HA#25

VAD

8VA

D7

VBD

1

HN

CO

MP

DSTBN#0

AGPAVDD2

HD

#2

HD

#23

HD

#29

HD

#35

HD

#55

HD

#61

HA#18

HA#29

H_REQ#1

VAD

11

VBD

0

DSTBN#2

AGCLK

HD

#5

HD

#28

HA#3

HA#10

H_DRDY#

H_ADS#

HA#[3..31]

AGPAVDD2

H_BR#0

H_TRDY#

VAD

2

AVSY

NC

VBD

3

VBD

5

CPU

AVSS

DSTBP#0

AGP_CLK

HD

#8

HD

#17

HD

#20

HD

#57

HA#14

HA#23

H_RS#1

H_REQ#[0..4]

AGPAVSS1

CPUAVDD

H_BPRI#

DSTBP#3

DSTBN#3

HD

#30

HD

#37

HD

#44

HA#7

HA#9

HA#22

HA#24

HA#26

H_BNR#

HD#[0..63]

VAD

4AGPAVSS2

AGPAVDD1

BHCLK

DBI

#0

HD

#36

HA#11

HA#13

HA#16

H_HITM#

HVREF

VBGCLK

BGCLK#

BGCLK

AVSYNC VAVSYNC

BCAD VBCAD

VBC

TL1

VBC

TL0

BCLK

VBCTL0VBCTL1

VBHCLK

VBCLK

VBGCLK#

BCLK

AGPVREF

VBD3VBD2

VBD0VBD1

AGCLK VAGCLK AGCLK# VAGCLK#

VAD2VAD1

VAD8

VAD5

VAD0

VAD4

VAD7

VAD3

VAD6

VAD9

VAD11VAD10

FC_VAD0FC_VAD1FC_VAD2FC_VAD3



BVSYNC

VBHSYNCBHSYNC

AHSYNC VAHSYNC

VBVSYNC

VBD11VBD10VBD9VBD8 FC_VBD8

FC_VBD11

VBD5

FC_VBD0

FC_VBD5

FC_VBD3

VBD6

FC_VBD10

FC_VBD4

FC_VBD6FC_VBD7

FC_VBD9

VBD4

FC_VBD2

VBD7

FC_VBD1

GND

+3VS

+3VS

GND

GND

+3VS

GND

+VCC_CORE

+VCC_CORE

+3VS

+3VS

+VCC_CORE

+3VS

GNDGND

GND

GND

GND

GND GND

GND GND

GND GND GND

GND

R2322

1 2

CP51022P*4/NA1206

1234

8765

CP51122P*4/NA1206

1234

8765

FA505 10*4 12061234

8765

CP51222P*4/NA1206

1234

8765

JL502

JP_NET20

1 2

R544

20 1% 0603D

1 2

R22 01 2

C8210U

10V1206

12

R56275

1%0603D

12

C260.01U0603

12

R50

60.4 1% 0603D

1 2

R24 221 2

R21150

0603D1%

12

R29 221 2

CP50722P*4/NA1206

1234

8765

CP50822P*4/NA1206

1234

8765

JL500

JP_NET20

1 2

CP50922P*4/NA1206

1234

8765

C5970.1U

50V0603

12

L14

120Z/100M2012

1 2

C270.01U0603

12

C6280.01U0603

12

FA503 10*4 12061234

8765

C56310U

10V1206

12

R19 01 2

U4A

SIS650BGA540_77_85

AJ26AH26

T24T26U29

V28T28U28W26V24V27

W28W29W24W25Y27

AD24AA24

AF26AE25AH28AD26AG29AE26AF28AC24AG28AE29AD28AC25AD27AE28AF27AB24AB26AC28AC26AC29AA26AB28AB27AA25AA29AA28

Y26Y24Y28

B21

F19

A21

E19

D22

D20

B22

C22

B23

A23

D21

F22

D24

D23

C24

B24

E25

E23

D25

A25

C26

B26

B27

D26

B28

E26

F28

G25

F27

F26

G24

H24

G29

J26

G26

J25

H26

G28

H28

J24

K28

J29

K27

J28

M24

L26

K26

L25

L28

M26

P26

L29

N24

N26

M27

N28

P27

N29

R24

R28

M28

P28

R26

R29

E21

A27

H27

R25

F6F3H4K5

C9A6G2G1G3G4H5H1

H3

E8F8D9

D10B3C4

B5A4

K1L1

C1D1

B10

M1

B9A9

B8A8

M3M2

F20F23K24P24

F21F24L24N25

AH25

AJ25

AH27

AJ27

U21

T21

P21

N21

J17

B20

B19

A19

A7 F9 B7 M6

M5

M4

L3 L6 L4 K6 L2 K3 J3 K4 J2 J6 J4 J1 H6

F4 F1 G6

E3 F5 E2 E4 E1 D3

D4

C2

F7 C3

E6 B2 D5

D8

D6

A3 D7

C5

A5 C6

C7

U24U26V26C20D19T27U25

CPUCLKCPUCLK#

RS2#RS1#RS0#

ADS#HITM#HIT#DRDY#DBSY#BNR#

HREQ4#HREQ3#HREQ2#HREQ1#HREQ0#

ADSTB1#ADSTB0#

HA31#HA30#HA29#HA28#HA27#HA26#HA25#HA24#HA23#HA22#HA21#HA20#HA19#HA18#HA17#HA16#HA15#HA14#HA13#HA12#HA11#HA10#HA9#HA8#HA7#HA6#HA5#HA4#HA3#

HD

63#

HD

62#

HD

61#

HD

60#

HD

59#

HD

58#

HD

57#

HD

56#

HD

55#

HD

54#

HD

53#

HD

52#

HD

51#

HD

50#

HD

49#

HD

48#

HD

47#

HD

46#

HD

45#

HD

44#

HD

43#

HD

42#

HD

41#

HD

40#

HD

39#

HD

38#

HD

37#

HD

36#

HD

35#

HD

34#

HD

33#

HD

32#

HD

31#

HD

30#

HD

29#

HD

28#

HD

27#

HD

26#

HD

25#

HD

24#

HD

23#

HD

22#

HD

21#

HD

20#

HD

19#

HD

18#

HD

17#

HD

16#

HD

15#

HD

14#

HD

13#

HD

12#

HD

11#

HD

10#

HD

9#H

D8#

HD

7#H

D6#

HD

5#H

D4#

HD

3#H

D2#

HD

1#H

D0#

DBI

3#D

BI2#

DBI

1#D

BI0#

AC/BE3#AC/BE2#AC/BE1#AC/BE0#

AREQ#/VBCADAGNT#

AFRAME#AIRDY#

ATRDY#ADEVSEL#

ASERR#ASTOP#

APAR

RBF#/VBHCLKWBF#/VGPIO2PIPE#/VGPIO3

AGP8XDETADBIHADBIL

SB_STBSB_STB#

AD_STB0/VAGCLKAD_STB0#/VAGCLK#

AD_STB1/VBGCLKAD_STB1#/VBGCLK#

AGPCLK

AGPRCOMP

AGPAVDD1AGPVSS1

AGPVDD2AGPVSS2

AGPVERFAGPVSSREF

DSTBN3#DSTBN2#DSTBN1#DSTBN0#

DSTBP3#DSTBP2#DSTBP1#DSTBP0#

CPU

AVSS

CPU

AVD

D

PHYA

VSS

PHYA

VDD

HVR

EF0

HVR

EF1

HVR

EF2

HVR

EF3

HVR

EF4

HPC

OM

PH

NC

OM

PH

CO

MPV

REF ST

0ST

1ST

2AD

0/VB

D7

AD1/

VBD

6AD

2/VB

D5

AD3/

VBD

4AD

4/VB

D3

AD5/

VBD

2AD

6/VB

D1

AD7/

VBD

0AD

8/VA

D6

AD9V

AD5

AD10

/VAD

4AD

11/V

AD7

AD12

/VAD

8AD

13/V

AD9

AD14

/VAD

10AD

15/V

AD11

AD16

/VAD

EAD

17/V

AVSY

NAD

18/V

AHSY

NC

AD19

/VBD

11AD

20/V

BD10

AD21

/VBD

8AD

22/V

BD9

AD23

/VAD

1AD

24/V

AD0

AD25

/VAD

2AD

26/V

AD3

AD27

/VBD

EAD

28/V

BCTL

0AD

29/V

BCTL

1AD

30/V

BHSY

NC

AD31

/VBV

SYN

C

SBA1

SBA7

SBA6

SBA5

SBA4

SBA3

SBA2

SBA0

HLOCK#DEFER#HTRDY#CPURST#CPUPWRGDBPRI#BREQ0#

C770.01U0603

12

C780.1U

50V0603

12

R108 0/NA1 2

R2575

1%0603D

12

R42 221 2

C6380.01U0603

12

R45 22/NA1 2

L15

120Z/100M2012

1 2

L507

120Z/100M2012

1 2

C280.1U

50V0603

12

L511

120Z/100M2012

1 2

R33 221 2

R563150

0603D1%

12

R34 22/NA1 2

R37 221 2

C4310P060310%

12

C760.01U0603

12

FA506 10*4 12061234

8765

C5010P/NA060310%

12

R36 221 2

C790.1U

50V0603

12

C330.01U0603

12

C8010U

10V1206

12

JL503

JP_NET20

1 2

JL504

JP_NET20

1 2

R110 0/NA1 2

C290.1U

50V0603

12

R20

110 1% 0603D

1 2

C340.01U0603

12

FA507 10*4 12061234

8765

C55910U

10V1206

12

FA504 10*4 12061234

8765

R6230106031%

12

FA502 10*4 12061234

8765

R5720006031%

12

C560.1U

50V0603

12

H_HIT#4

HCLK_SIS650#11

HA#[3..31]4

H_RS#[0..2]4

H_DRDY#4

CPUPWRGD4

DSTBN#[0..3] 4

DSTBP#[0..3] 4

H_HITM#4

HD#[0..63]4

HCLK_SIS65011

H_DBSY#4

H_REQ#[0..4]4

DBI#[0..3] 4

H_ADSTB#14

H_BNR#4

H_ADS#4

H_BR#04

H_ADSTB#04

VBDE 9VADE 9

H_DEFER#4

H_BPRI#4

H_TRDY#4CPURST#4

AGP_CLK 11

H_LOCK#4

VBGCLK 9

VBGCLK# 9

VAVSYNC 9

VBCAD 9

VBHCLK 9

VBCAD 9

VBCTL0 9VBCTL1 9

VBCLK 9

FC_VBD[0..11] 9

VAGCLK 9 VAGCLK# 9

FC_VAD[0..11] 9

VBVSYNC 9

VBHSYNC 9

VAHSYNC 9

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

A A

B B

C C

D D

0650 Debug Mode Disable/Enable (0/1)TRAP0

0

1(DDR)

RSYNCVideo Bridge Disable/Enable (0/1)

LSYNC

0

Yes

PANEL ID0CSYNC

1

Yes

NB Hardwre Trap Table

DRAM_SEL

0

DLLEN#

PANEL ID2

embedded pull-low(30〜50K Ohm)

TRAP1

Enable PLL

Yes

PANEL ID1

SDR

Default

DDR

1

Disable PLL

0

0

MA13 --> MEM_MA11

MA11 --> BANK SELECT 0

MA14 --> MEM_MA12

MA12 --> BANK SELECT 1

SIS650(2/3)

BD 311671700001 & TU 411671700011 01

8575A SIS650 (2/3)

C


Title

Size DocumentNumber

Rev

Date: Sheet of

DACAVDD2

ECLKAVDD

VVBWN

VCOMP

ZVREF

DCLKAVDD

SDAVDD

DDRAVDD

VRSET

DDRVREFA

DDRVREFB

DDR_DQM0DDR_DQM1DDR_DQM2DDR_DQM3DDR_DQM4DDR_DQM5DDR_DQM6DDR_DQM7 DRAM_SEL

SDAVSS

DDR_MD11

DDR_MA9

DDR_MA11

DDR_MD49

DDR_MD5

DDR_DQM3

DDR_MD50

DDR_MD34

DDR_MD24

DDR_MD7

DDR_MD46

DDR_MA10

DRAM_SEL

DDR_MA6DDR_MD12

DDR_DQM4

DDR_DQM1

DDR_MA7

DDR_MD36

DDR_MD3

DDR_MD17

DDR_MD58

DDR_MD55

DDR_MD56

DDR_DQM7

DDR_MD57

DDR_MA4

DDR_MD16

DDR_MD61

DDR_MD21

SDAVSS

DDR_MD38

DDR_MD42

DDR_MD39

DDRAVSS

DDR_DQM5

DDR_MD31

DDR_MD35

SDAVDD

DDR_MD45

DDR_MD52

DDR_MD4

DDRVREFA

DDR_MA2

DDR_MD47

DDR_MD37

DDR_MD10DDR_MD9

DDR_DQM6

DDR_MD19

DDR_MD6

DDR_MD14

DDR_MD54

DDR_MD20

DDR_MD0

DDR_MA8DDR_MD13

DDR_MD28

DDR_MD41

DDR_MA0

DDR_MD27

DDRVREFB

DDR_MD23

DDR_MD8

DDR_MD40

DDR_MD1

DDR_MD60

DDR_MD62

DDR_DQM0

DDR_MD15

DDR_MA3

DDR_MD26

DDR_MA5

DDRAVDD

DDR_MD2

DDR_MD44

DDR_MD53

DDR_MD30

DDR_MD43

DDR_MA12

DDR_MD59

DDR_MD32

DDR_MA1

DDR_MD25

DDR_MD48

DDR_MD29

DDR_MD51

DDR_MD18

DDR_MD63

DDR_MD22

DDR_MD33

S3AUXSW#

DACAVSS1

PID2

VVBWN

DCLKAVSS

ECLKAVSS

ZVREF

VDDZCMP

ZCMP_P

PID1

DACAVDD2

DLLEN#

TRAP0

DCLKAVDDVSSZCMP

DACAVDD1

Z4XAVDD

RSYNC

Z1XAVDD

VRSET

DACAVSS2

Z1XAVSS

VCOMP

ECLKAVDD

ZCMP_N

Z4XAVSS

VDDZCMP

ZCMP_N

DDRAVSS

ZCMP_P

Z4XAVDD Z1XAVDD

FWDSDCLKO

ZAD5

ZAD8ZAD7

ZAD10

ZAD2

ZAD13ZAD12

ZAD[0..15]

ZAD3

ZAD6

ZAD14

ZAD4

ZAD15

ZAD11

ZAD1

ZAD9

ZAD0

VSSZCMP

DCLKAVSS

DACAVSS2

Z4XAVSS

ECLKAVSS

Z1XAVSS

RSYNC

DLLEN#

TRAP0

DDR_DQS4

DDR_DQM2

DDR_DQS3

DDR_DQS1

DDR_DQS2

DDR_DQS0

DDR_DQS7

DDR_DQS6

DDR_DQS5

DACAVDD1

DACAVSS1

PWROK

AUXOK

PWROK

CKE3CKE2CKE0CKE1

PID2

PID1 LCD_ID1

LCD_ID0PID0

PID0

LCD_ID2+3VS

+3VS

GND

+1.8VS

GND

GND

+3VS

GND

GND

+3VS

+2.5V_DDR

GND

+2.5V_DDR

GND

+3VS

GND

GND

GND

+1.8VS

GND

+3VS

GND

+3VS

GND

+1.8VS

GND

GND

GNDGND

GND

+3VS

+2.5V_DDR

TP5101

R18 4.7K1 2

R614 221 2

R829 0 0603D_DFS1 2

TP5091

R599 4.7K1 2

R5571500603D1%

12

R570 4.7K/NA1 2

C6070.1U

50V0603

12

R830 0 0603D_DFS1 2

C350.01U0603

12

C59910U

10V1206

12

L515

120Z/100M2012

1 2

C310.1U

50V0603

12

JL513

JP_NET20

1 2

C5890.1U

50V0603D

12

C6310U

10V1206

12

R5544.7K0603D

12

L12

120Z/100M2012

1 2

C63210U

10V1206

12

JL512

JP_NET20

1 2

C6230.01U0603

12

L505

120Z/100M2012

1 2

U4C

SIS650BGA540_77_85

V3

U6U1

T3T1

P1P3

T4R3T5T6R2R6R1R4P4N3P5P6N1N6N2N4

U3

V5U4U2V6

W1W2

V2V1

C15

A12B13A13

F13E13

D13D12

B11

E12A11

E14D14F14

B12C12

C13C14

B15A15

B14A14

F12

D11

E10

A10

F11

C11

E11

F10

Y3 W4

W6

ZCLK

ZUREQZDREQ

ZSTB0ZSTB0#

ZSTB1ZSTB1#

ZAD0ZAD1ZAD2ZAD3ZAD4ZAD5ZAD6ZAD7ZAD8ZAD9ZAD10ZAD11ZAD12ZAD13ZAD14ZAD15

ZVREF

VDDZCMPZCMP_NZCMP_PVSSZCMP

Z1XAVDDZ1XAVSS

Z4XAVDDZ4XAVSS

VOSCI

ROUTGOUTBOUT

HSYNCVSYNC

VGPIO0VGPIO1

INTA#

CSYNCRSYNC

VCOMPVRSET

VVBWN

DACAVDD1DACAVSS1

DACAVDD2DACAVSS2

DCLKAVDDDCLKAVSS

ECLKAVDDECLKAVSS

LSYNC

TRAP

1TR

AP0

TEST

MO

DE2

TEST

MO

DE1

TEST

MO

DE0

DLL

EN#

ENTE

ST

PCIR

ST#

PWR

OK

AUXO

K

R548 1001 2

L506

120Z/100M2012

1 2

R566 1001 2

C6240.1U

50V0603

12

JL507

JP_NET20

1 2

C700.01U0603

12

L516

120Z/100M2012

1 2

C593

0.1U 50V0603D

1 2

JL506

JP_NET20

1 2

R6131500603D1%

12

C5841U0603

12

JL505

JP_NET20

1 2

C670.01U0603

12

R546 331 2

C56210U

10V1206

12

C6890.01U0603D

12

L518

120Z/100M2012

1 2

C63010U

10V1206

12

C360.01U0603

12

JL511

JP_NET20

1 2

D15

RLS4148

AK

R5531500603D1%

12

R547 331 2

C6410.01U0603

12

C654

0.1U

50V

0603

1 2

C6880.01U0603D

12

R596 561 2

TP508 1

R571 4.7K/NA1 2

U12MAX809 SOT23N

2 3

1

RESET# VCC

GN

D

C300.1U

50V0603

12

L13

120Z/100M2012

1 2

C5830.1U

50V0603D

12

R587 561 2

TP6 1

C690.1U

50V0603

12

TP7 1

C2230.1U

50V0603

12

R6121500603D1%

12

C667

0.1U

50V

0603

1 2

C6060.01U0603

12

JL510

JP_NET20

1 2

R145100K0603

12

C6370.1U

50V0603

12

C691

10P/NA0603

1 2

C600

0.1U 50V0603D

1 2

U4B

SIS650BGA540_77_85

AJ23AG22AH21AJ21AD23AE23AF22AF21

AD21AG20AE19AF19AE21AD20AD19AH19

AF18AG18AH17AD16AD18AD17AF17AJ17

AD14AG14AJ13AE13AJ15AF14AD13AF13

AD10AH10

AE9AD8

AG10AF10AH9AF9

AH5AG4AE5AH3AG6AF6AF5AF4

AE4AD6AE2AC5AG2AG1AF3AC6

AB6AD3AA6AB3AC4AE1AD2AC1

AD22

AF20

AE17

AH13

AD9

AH4

AD4

AB4

AH22

AH20

AH18

AH14

AJ9

AJ3

AF2

AC2

AH8AJ7AH7

AE7AF7AH6AJ5AF8AD7

AB2AA4AB1Y6AA5Y5Y4

AA3

AD11

AE11

Y1

Y2

AA1

AA2

AJ19AH2

W3

AH11AF12AH12AG12AD12AH15AF15AH16AE15AD15AF11AG8AJ11AG16AF16

MD0/SMD63MD1/SMD30MD2/SMD29MD3/SMD59MD4/SMD31MD5/SMD62MD6/SMD60MD7/SMD28


MD16/SMD22MD17/SMD53MD18/SMD20MD19SMD19MD20/SMD54MD21/SMD21MD22/SMD51MD23/SMD50

MD24/SMD18MD25/SMD17MD26/SDQM7MD27/SDQM6MD28/SMD49MD29/SMD48MD30/SDQM3MD31/SDQM2

MD32/SDQM5MD33/SDQM4MD34/SMD47MD35/SMD45MD36/SDQM1MD37/SDQM0MD38/SMD46MD39/SMD14




DQM0/SMD61

DQM1/SMD25

DQM2/SMD52

DQM3/SMD16

DQM4/SMD15

DQM5/SMD11

DQM6//SMD38

DQM7/SMD2

DQS0/CSB0#

DQS1/CSB1#

DQS2/CSB2#

DQS3/CSB3#

DQS4/CSB4#

DQS5/CSB5#

DQS6/CSB6#

DQS7/CSB7#

SRAS#SCAS#SWE#

CS0#CS1#CS2#CS3#CS4#CS5#

CKE0CKE1CKE2CKE3CKE4CKE5

S3AUXSW#

SDCLK

FWDSDCLKO

SDRCLKI

SDAVDD

SDAVSS

DDRAVDD

DDRAVSS

DDRVREFADDRVREFB

DRAM_SEL

MA0MA1MA2MA3MA4MA5MA6MA7MA8MA9

MA10MA11MA12MA13MA14

L514

120Z/100M2012

1 2

C7110U

10V1206

12

C58010U

10V1206

12

R545130

1%0603D

12JL509

JP_NET20

1 2

C5950.1U

50V0603D

12

C660.1U

50V0603

12

C56110U

10V1206

12

C6920.01U0603D

12

R6151500603D1%

12

R6161500603D1%

12

D14

RLS4148

AK

TP5131

R828 0 06030603D_DFS1 2

RP7

470*41206

1234

8765

C6930.01U0603D

12

TP5111

DDR_DQM[0..7]12

DDR_DQS[0..7]12

DDR_WE# 12

DDR_CS2# 12

S3AUXSW# 15,22

DDR_CAS# 12

DDR_MD[0..63]12

DDR_BA0 12

DDR_CS3# 12

DDR_CS1# 12

DDR_BA1 12

CKE1 12

SDRAMCLK 11

DDR_RAS# 12

DDR_MA[0..12] 12

CKE2 12

DDR_CS0# 12

CKE3 12

CKE0 12

ZSTB1#14

ZCLK011

ZSTB014

AUXOK15

-PCIRST9,14,17,18,21,28,29

ZSTB0#14

CRT_DDCK 10

ZAD[0..15]14

CRT_BLUE 10ZSTB114

ZDREQ14

REFCLK0 11ZUREQ14

PCI_INTA# 9,14,17

CRT_HSYNC 10

CRT_DDDA 10

CRT_RED 10CRT_GREEN 10

PWROK15

FWDSDCLKO 11

CRT_VSYNC 10

PWROK15

H_PWRGD26

LCD_ID1 10

LCD_ID2 10

H8_PWROK22

LCD_ID0 10

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

A A

B B

C C

D D

FORAUX1.8 FOR OVDD &

PVDD

FOR AUX3.3 &PVDDM

FOR VDDM

SIS650(3/3)

FOR VTT

FOR VTT FORVDDM

FOR VDDQ

BD 311671700001 & TU 411671700011 01

8575A SIS650 (3/3)

C


Title

Size DocumentNumber

Rev

Date: Sheet of

+3V

+3V

+1.8V

+1.8V

+3VS

+2.5V_DDR

+2.5V_DDR

+1.8VS +3VS

+1.8VS

+1.8VS

+1.8VS

+3V+3VS

+3VS

+1.8VS +2.5V_DDR

+1.8VS

+3VS

+3V

GND

GND

GND

GND

+VCC_CORE

+VCC_CORE

GND

GND

GNDGND

GND

GND

GND

GND

+VCC_CORE

GND

GND

GND

GND

GND

GND

GND

GND

GND

+VCC_CORE

C655 0.1U1 2

C604 0.1U1 2

C609 0.1U1 2

C672 1U 06031 2 C668 1U 06031 2

C671 0.1U1 2

C670 0.1U1 2

C649 0.1U1 2

C677 0.1U1 2

C65910U

10V1206

12

C66610U

10V1206

12

C618 0.1U1 2

C613 0.1U1 2

C587 0.1U1 2

C594 0.1U1 2

C598 0.1U1 2

C626 0.1U1 2

C617 0.1U1 2

C591 0.1U1 2

C647 1U 06031 2

C634 0.1U1 2

C690 0.1U1 2

C646 0.1U1 2

C657 0.1U1 2

C68010U

10V1206

12

C612 0.1U1 2

U4D

SIS650BGA540_77_85

A16A17A18B16B17B18C16C17C18D15D16D17D18E15E16E17E18F15F16F17F18

H21

H22

J16

J20

J21

J22

K16

K17

K18

K19

K20

K21

L20

M20

N20

P20

R20

R21

T20

U20

V20

W20

Y20

Y21

AA20

AA21

AA22

AB21

AB22

AB5AD5AE6AE8

AE10AE12AE14AE16AE18AE20AE22

V10V11

W18Y9

Y10Y12Y14Y16Y18Y19AA8AA9

AA10AA13AA14AA15AA16AA17

AB8AB9

AB13AB17

E5E7E9G5J5L5H8H9J8J9

J10J13K9

K11K13L10N9

N10

N5R5U5W5P9

P10R9

R10T9

T10T11

L12

L14

L15

L16

L18

M11

M19

N11

P19

R11

T19

U11

V19

W11

W13

W15

W17

P11

J14

J15

K15

K10

K12

K14

M10

W10

Y11

Y13

Y15

Y17

U10U9

A20A22A24A26C19C21C23C25C27E20E22E24F25H25K25M25P25T25V25Y25AB25AD25E27G27J27L27N27R27U27W27AA27AC27AE27D29F29H29K29M29P29T29V29Y29AB29AD29AF29AE24AG25B4B6C8C10D2F2H2K2P2T2V4AD1AF1AC3AE3AG3AG5AG7AG9AG11AG13AG15AG17AG19AG21AG23AJ4AJ6AJ8AJ10AJ12AJ14AJ16AJ18AJ20AJ22AJ24AG27

L17

L19

N19

R19

U19

W19

M12

M13

M14

M15

M16

M17

M18

N12

N13

N14

N15

N16

N17

N18

P12

P13

P14

P15

P16

P17

P18

R12

R13

R14

R15

R16

R17

R18

T12

T13

T14

T15

T16

T17

T18

U12

U13

U14

U15

U16

U17

U18

V12

V13

V14

V15

V16

V17

V18

B25

C28

C29

D27

D28

E28

E29

AF23

AF24

AF25

AG24

AG26

AH23

AH24

VTT_0VTT_1VTT_2VTT_3VTT_4VTT_5VTT_6VTT_7VTT_8VTT_9VTT_10VTT_11VTT_12VTT_13VTT_14VTT_15VTT_16VTT_17VTT_18VTT_19VTT_20

VTT_

21VT

T_22

VTT_

23VT

T_24

VTT_

25VT

T_26

VTT_

27VT

T_28

VTT_

29VT

T_30

VTT_

31VT

T_32

VTT_

33VT

T_34

VTT_

35VT

T_36

VTT_

37VT

T_38

VTT_

39VT

T_40

VTT_

41VT

T_42

VTT_

43VT

T_44

VTT_

45VT

T_46

VTT_

47VT

T_48

VTT_

49

VDDM_0VDDM_1VDDM_2VDDM_3VDDM_4VDDM_5VDDM_6VDDM_7VDDM_8VDDM_9VDDM_10VDDM_11VDDM_12VDDM_13VDDM_14VDDM_15VDDM_16VDDM_17VDDM_18VDDM_19VDDM_20VDDM_21VDDM_22VDDM_23VDDM_24VDDM_25VDDM_26VDDM_27VDDM_28VDDM_29VDDM_30VDDM_31VDDM_32

VDDQ_0VDDQ_1VDDQ_2VDDQ_3VDDQ_4VDDQ_5VDDQ_6VDDQ_7VDDQ_8VDDQ_9VDDQ_10VDDQ_11VDDQ_12VDDQ_13VDDQ_14VDDQ_15VDDQ_16VDDQ_17

VDDZ_0VDDZ_1VDDZ_2VDDZ_3VDDZ_4VDDZ_5VDDZ_6VDDZ_7VDDZ_8VDDZ_9VDDZ_10

IVD

D_0

IVD

D_1

IVD

D_2

IVD

D_3

IVD

D_4

IVD

D_5

IVD

D_6

IVD

D_7

IVD

D_8

IVD

D_9

IVD

D_1

0IV

DD

_11

IVD

D_1

2IV

DD

_13

IVD

D_1

4IV

DD

_15

IVD

D_1

6

PVD

DZ

OVD

D_0

OVD

D_1

OVD

D_2

PVD

D_0

PVD

D_1

PVD

D_2

PVD

D_3

PVD

DM

_0PV

DD

M_1

PVD

DM

_2PV

DD

M_3

PVD

DM

_4 AUX1.8AUX3.3

VSS_0VSS_1VSS_2VSS_3VSS_4VSS_5VSS_6VSS_7VSS_8VSS_9

VSS_10VSS_11VSS_12VSS_13VSS_14VSS_15VSS_16VSS_17VSS_18VSS_19VSS_20VSS_21VSS_22VSS_23VSS_24VSS_25VSS_26VSS_27VSS_28VSS_29VSS_30VSS_31VSS_32VSS_33VSS_34VSS_35VSS_36VSS_37VSS_38VSS_39VSS_40VSS_41VSS_42VSS_43VSS_44VSS_45VSS_46VSS_47VSS_48VSS_49VSS_50VSS_51VSS_52VSS_53VSS_54VSS_55VSS_56VSS_57VSS_58VSS_59VSS_60VSS_61VSS_62VSS_63VSS_64VSS_65VSS_66VSS_67VSS_68VSS_69VSS_70VSS_71VSS_72VSS_73VSS_74VSS_75VSS_76VSS_77VSS_78VSS_79VSS_80VSS_81VSS_82VSS_83VSS_84PV

DD

P_0

PVD

DP_

1PV

DD

P_2

PVD

DP_

3PV

DD

P_4

PVD

DP_

5

VSS_

85VS

S_86

VSS_

87VS

S_88

VSS_

89VS

S_90

VSS_

91VS

S_92

VSS_

93VS

S_94

VSS_

95VS

S_96

VSS_

97VS

S_98

VSS_

99VS

S_10

0VS

S_10

1VS

S_10

2VS

S_10

3VS

S_10

4VS

S_10

5VS

S_10

6VS

S_10

7VS

S_10

8VS

S_10

9VS

S_11

0VS

S_11

1VS

S_11

2VS

S_11

3VS

S_11

4VS

S_11

5VS

S_11

6VS

S_11

7VS

S_11

8VS

S_11

9VS

S_12

0VS

S_12

1VS

S_12

2VS

S_12

3VS

S_12

4VS

S_12

5VS

S_12

6VS

S_12

7VS

S_12

8VS

S_12

9VS

S_13

0VS

S_13

1VS

S_13

2VS

S_13

3VS

S_13

4VS

S_13

5VS

S_13

6VS

S_13

7VS

S_13

8VS

S_13

9VS

S_14

0VS

S_14

1VS

S_14

2VS

S_14

3VS

S_14

4VS

S_14

5VS

S_14

6VS

S_14

7

C631 10U1 2

C586 0.1U1 2 C608 0.1U1 2

C635 0.1U1 2

C67410U

10V1206

12

C682 0.1U1 2

C681 0.1U1 2

C686 0.1U1 2

C620 0.1U1 2

C685 0.1U1 2

C658 1U 06031 2

C558 10U1 2

C644 1U 06031 2

C633 1U 06031 2

C605 1U 06031 2C565 10U1 2

C596 0.1U1 2C590 10U1 2

C653 0.1U1 2

C616 1U 06031 2

C611 1U 06031 2

C603 10U1 2

C665 10U1 2

C629 0.1U1 2

C639 0.1U1 2

C636 1U 06031 2

C622 0.1U1 2

C645 0.1U1 2

C621 0.1U1 2

C673 1U 06031 2 C669 1U 06031 2

C585 0.1U1 2

C619 0.1U1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

14x20LQFP

SiS301LV/Chrontel CH7019

SiS301LV/CH7019

0GPIOA

1GPIOB

VGA YUV TV SCARTNormal

TV

0

1 1

1

0

0

GPIOC

GPIOD 0

1

1

00

0

1

1

NormalTV

YUV TV

NormalPAL

PAL-M PAL-N NormalNTSC

525I 525P 750P 1080I

CLOSE TO CH7017

CLOSE TO CH7017

CLOSE TO CH7017

FS0 and SR0 HAVEINTERNALPULL_UP 100KOhm

Spread Range SelectionFS0 SR0 Spreading Range Input Frequency Modulation Rate

11 1

100

0

0

+/- 1.50%+/- 2.50%+/- 1.25%+/- 2.00% 20 MHz to 35 MHz

20 MHz to 35 MHz10 MHz to 20 MHz10 MHz to 20 MHz (Fin/10)*20.83 KHz

(Fin/10)*20.83 KHz(Fin/10)*20.83 KHz(Fin/10)*20.83 KHz

140 CH7019

2.4K CH7019

10K CH7019

R40

SiS301LV CH7019

R51

NA 75 ohm

NA 4.7K ohm

R55 NA 0 ohm

R59 0 ohm NA

R60 0 ohm 10K ohm

R63 NA 10K ohm

R76 0 ohm NA

R79 0 ohm NA

R248 0 ohm NA

R550 6.04K ohm 2.4K ohm

R541

R542

NA 0 ohm

0 ohm NA

R549 147 ohm 140 ohm

R586 0 ohm 10K ohm

R588 NA 10K ohm

R589 0 ohm NA

R597 0 ohm NA

R598 NA 0 ohm

R600 0 ohm NA

R603 0 ohm NA

R602 0 ohm NA

R834 NA 75 ohm

R835 2K ohm NA

C32 NA 0.1u

C72 NA 0.1u

C307 0.1u NA

C887 0.1u NA

C888 1u NA

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

R604

R601

R111

NA

NA

NA0 ohm

0 ohm

10K ohm

37

36

22 ohm

35

34

NA

22 ohm NA

0 ohm

R110

22 ohm

R23

NA

R22

NA

R45 NA

NA

R19

R108

38 R34

33

32

PAGE 06

0 ohm

0 ohm

NA 0 ohm

BD 311671700001 & TU 411671700011 01

8575A TV/LVDS ENCODER (SiS301LV)

C


Title

Size DocumentNumber

Rev

Date: Sheet of

-PCIRST

MOD_XOUT

ENABKL

GPIOC

GPIOD

+LVDD0/1

+LPLL_VDD

DD2

VBHCLK

FC_VBD11

FC_VAD3

GPI

OD

TXOUT0-TXOUT0+

TX2OUT0-

TX2OUT2+

GPIO3

GPIO3

FC_VAD7

MO

D_X

OU

T

HPD

AS

FC_VBD2

FC_VBD9D

D2

TXOUT1+

VBCAD

FC_VAD1

GPI

OC

TXOUT1-

TX2OUT1-

GPIO4

+VREF2

+DAC_VDD

TXCLK-

+LVDD2

ENAVDD

FC_VBD0

FC_VBD6

VBDE

+VDDV

FC_VAD2

GPI

OB

DC2

GPIOB

+TVPLL_VDD

FC_VBD1

FC_VBD7

TX2OUT0+

FC_VBD10

TX2CLK+

+VREF1

GPIO2

FC_VAD0

DC

2

GPIO2

VADE

FC_VBD8

FC_VAD8

GPI

OA

FC_VAD[0..11]

GPIOA

FC_VBD4FC_VBD5

FC_VAD4

FC_VAD11

AS

+LPLL_VDD

FC_VAD10

TXOUT2+

TX2OUT1+

GPIO5

FC_VBD3

FC_VAD5

TXCLK+

FC_VAD6

TXOUT2-

FC_VBD[0..11]

FC_VAD9

TX2OUT2-

TX2CLK-

MOD_XOUT

+LVDD3

+TVPLL_VCC

TVPLL_GND

+LVDD0/1

+3VS

+3VS

+3VS

+3VS

+DVDD

LGND

+3VS

+3VS

+3VS

+DVDD

+3VS

+3VS

+5VS

DGND

LGND1

LGND2

LPLLGND

DAC_GND

TVPLL_GND +5VS

+DVDD

+DVDD

+DVDD

DGND

+3VS

+3VS

+3VS

+5VS

+3VS

+3VS

+DAC_VDD

+DVDD

GND

GNDGND +DAC_VDD

R84 33/NA0603

1 2

R79 00603

1 2

C6140.1U

50V0603

12

L542

120Z/100M2012

1 2

R106 33/NA0603

1 2

C8870.1U

50V0603

12

C400.1U0603

12

R835

2K 0603

1 2

R82 0/NA0603

1 2

R76 00603

1 2

C5780.1U

50V0603

12

C888

1U 0603

1 2

X501

14.318MHZ

1 2

R510 0 06031 2

C5810.1U

50V0603

12

R115 10K/NA0603

1 2

R543750603

12

R549

1471 2

U522

P2010/NASO8

1234 5

678XIN

XOUTFS0VSS SSON

MODOUTSR0VDD

R122 4.7K/NA0603

1 2

U504CH7017PQFP128A_0.5MM

1234567891011121314151617181920212223242526272829303132333435363738

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

102101100

9998979695949392919089888786858483828180797877767574737271706968676665

LPLL_VDDLPLLCAP

LPLL_GNDLGND0

LL2CLL2C*

LVDD0LDC7

LDC7*LGND1

LDC6LDC6*

LVDD1LDC5

LDC5*LGND2

LDC4LDC4*

LVDD2LVDD3

LDC3LDC3*

LGND3LL1C

LL1C*LVDD4

LDC2LDC2*

LGND4LDC1

LDC1*LVDD5

LDC0LDC0*

LGND5VSWING

DAC_VDDISET

DVD

D0

DE2

FLD

/STL

2AS SP

DSP

CH

INVI

NVR

EF2

SDD

SDC

DD

1D

C1

DD

2D

C2

V5V

HO

UT

VOU

TH

PDH

PIN

T*G

PIO

[0]

GPI

O[1

]G

PIO

[2]

GPI

O[3

]EN

AVD

DEN

ABKL

DVD

D1

DE1

FLD

/STL

1VR

EF1

VDD

VP-

OU

TR

ESET

*G

PIO

[5]

GPI

O[4

]TV

PLL_

VDD

TVPL

L_VC

CXO

XI /

FIN

TVPL

L_G

ND

BCO

/VSY

NC

C/H

SYN

CD

AC_G

ND

0D

ACA[

3]D

ACB[

3]D

ACA[

2[D

ACB[

2]D

ACA[

1]D

ACB[

1]D

ACA[

0]D

ACB[

0]D

AC_G

ND

1

V2H2DGND0D2[11]D2[10]D2[9]D2[8]D2[7]D2[6]XCLK2DGND1XCLK2*D2[5]D2[4]D2[3]D2[2]D2[1]D2[0]DVDD2DVDD3D1[11]D1[10]D1[9]D1[8]D1[7]D1[6]XCLK1DGND2XCLK1*D1[5]D1[4]D1[3]D1[2]D1[1]D1[0]DGND3H1V1

R53 10K/NA 06031 2

R586 0

0603

1 2

R597 00603

1 2

C5127P/NA06035%

12

R54 10K/NA 06031 2

R589 00603

1 2

R604 0/NA0603

1 2

C5527P/NA

06035%

12

R133 10K/NA 06031 2

R588 10K/NA0603

1 2

R112 4.7K/NA0603

1 2

JL537

JP_NET201 2

C5730.1U

50V0603

12

R8331M/NA0603

12

JL540

JP_NET201 2

C5701U0603

12

C6250.1U

50V0603

12

R524.7K0603

12

C579100P060310%

12

C6400.1U0603

12

C6020.1U

50V0603

12

R831 0 06031 2

TP518

1

R113

00603

1 2

R40 00603

1 2

C66410U

25V1206

12

C56910U

25V1206

12

R514.7K/NA0603

12

R8 0/NA0603

1 2

R78 10K/NA 06031 2

R123

10K/NA0603

1 2

C6970.1U0603

12

R9 00603

1 2

R77 357K/NA 06031 2

R278 0/NA0603

1 2

C56610U

25V1206

12

R593 10K/NA 06031 2

C6271U0603

12

C74010U

25V1206

12

R124 357K/NA 06031 2

R592 357K/NA 06031 2

C720.1U/NA

50V0603

12

C7380.1U

50V0603

12

JL533

JP_NET20

1 2

C320.1U/NA

50V0603

12

C5750.1U

50V0603

12

L528

120Z/100M2012

1 2

C7310U

25V1206

12

L540

120Z/100M2012

1 2

R5400/NA 0805

1 2

R603 00603

1 2

C564

2.2U/NA0805C

12

R550

6.04K1 2

R565

0/NA0603

1 2

U503

AME8800AEEV/NASOT25

1234

5 GND0VIN

VOUTNC1

NC0

R47 357K/NA 06031 2

JL539

JP_NET20

1 2

C5741U0603

12

C65210U

25V1206

12

C56710U

25V1206

12

R559

10K/NA0603

1 2C5721U0603

12

R48 357K/NA 06031 2

R59 00603

1 2

R518

00603

1 2

C3070.1U

50V0603

1 2

JL534

JP_NET201 2

C5600.1U

50V0603

12

C57110U

25V1206

12

JL538

JP_NET20

1 2

L512

120Z/100M2012

1 2

R105 0/NA0603

1 2

R83475/NA0603

12

R111 4.7K/NA0603

1 2

L25

120Z/100M2012

1 2

C5761U0603

12

R814.7K/NA0603

12R594 0

06031 2

JL541

JP_NET201 2

L519

120Z/100M2012

1 2

R1044.7K/NA0603

12

L513

120Z/100M2012

1 2

C390.1U0603

12

R8321M/NA0603

12

C750.1U50V0603

12

L509

120Z/100M2012

1 2

RP508

75*4/NA 1206

1234

8765

R542 00603

1 2

C56810U

25V1206

12

C5821U0603

12

L510

120Z/100M2012

1 2

C420.1U0603

12

R541 0/NA0603

1 2

C7390.1U/NA0603

1 2

R600 00603

1 2

R55 0/NA1 2

L508

120Z/100M2012

1 2

R51175/NA0603

12

C61510U

25V1206

12

C65122P06035%

12

R7410006031 2

TP5211

C72710U

25V1206

12

C61022P06035%

12

L541

120Z/100M2012

1 2

VBHSYNC6

VAGCLK6

VBVSYNC6

VAGCLK#6

VBGCLK#6

FC_VBD[0..11]6

VAHSYNC6VAVSYNC6

VBDE6

VADE6 ENAVDD 10

TXOUT0+ 10

TXOUT2+ 10VBGCLK6 TXOUT2- 10

TXOUT1- 10

TXCLK- 10

TXOUT1+ 10

TXOUT0- 10

TXCLK+ 10

TV_CRMA 27

VBHCLK6VBCAD6

TV_LUMA 27

TX2OUT0- 10TX2OUT0+ 10



TX2CLK- 10TX2CLK+ 10

-PCIRST7,14,17,18,21,28,29

ENABKL 22,27

14.318MHZ_TV11

VBCLK6

VBCTL16

FC_VAD[0..11]6

PCI_INTA# 7,14,17

-PCIRST 7,14,17,18,21,28,29

VBCTL06

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

74VH

C16

4

Exte

rnal

VG

ACo

nnec

tor

Close to VGA Connector

LCD & CRT INTERFACE

W/S=16/12/12/12/16 mils

GND_CRT15GND_CRT15 GND_CRT15 GND_CRT15 GND_CRT15

D16 D15 D13 D14 D15

CDROM HDD NUM CAP SCROLL

LED INDICATOR

GND_CRT15

DDC2B 1Amp(40mil-60mil)

GND_CRT15

(NA D10,D8,D9,D11,D15,R586,R211,R212,R213,R96, For LCD 15")

Close to VGA Connector

㆕組各自平行走線等長

LCD CONNECTOR

as short as possibleS/W/W/S=12/6/6/12 mils

Layout Note:

Close to LCD Connector

CLOSE TO NDS 9410

LCD 14" 330mA,15"800mA

DISPLAY LCD_ID2 LCD_ID1 LCD_ID0 UNIQAC 0 0 1HYUNDAI 0 1 0HANNSTAR 0 1 1CMO 1 0 0

GND_CRT15 BD 311671700001 & TU 411671700011 01

8575A LCD/VGA INTERFACE

10 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

-BATT_G-H8_RESET

LED_CLK-BATT_R

LED_DATA

-AC_POWER

CRT_DDDA

BATT_POWER#

DDC2BCRT_GREEN

CRT_RED

-CAP-NUM-SCROLL

ENAVDD

TX2OUT0+

TX2OUT2-

TXCLK+

TXOUT2+

TXOUT0-

TX2OUT1+

TXOUT0+

LCDVCC

TX2CLK-

LCDVCC

TXCLK-

LCD_ID1

TXOUT1+

TX2OUT2+

TX2CLK+

TX2OUT0-

LCD_ID0

LCD_ID2

TXOUT1-

TX2OUT1-

TXOUT2-

CRT_BLUE

CRT_DDCK

CRT_VSYNC

CRT_HSYNC

-BATT_LED

BATT_POWER#

ACPILED

BATT_POWER#

-BATT_LED

MPCI_PD

+5VA

+5VS

+5VS

+5VS

+5VS

+5VS

+3VS

+3VS

+12VS

+3V+3V+3V

GND GNDGND

+3V

+3VS

+3V

GND

+5VS

R723

1M/NA0603

1 2C8101U0603

12

R740

220K/NA0603

1 2

C8081U0603

12

R1 Q527DTC144TKA/NA

2

13

C8071U0603

12

U516A

74AHC14_V/NATSSOP14

1 2

147

F503mircoSMDC11012

R5522.2K0603

12

J3

MA/20PX2/STACES87216-4000

13579

11131517

246810121416182019

GND1GND2

2123252729

2224262830

3133353739

3234363840

R5582.2K0603

12

C8024.7U/NA

16V0805C_1206

12

DS

Q505

2N7002

G

DS

D501EC11FS2/NA

AK

C30.1U

50V0603

12

DS

Q501

2N7002

G

DS

C51010U

10V1206

12

FA501130OHM/100MHZ

1234 5

678

D2

BAV99_NA

1

23

U517

74VHC164TSSOP14

12

8

9

345610111213

7 14

AB

CLK

CLR

QAQBQCQDQEQFQGQH

GND VCC

J2VGASUYIN7535S-15G2T-05

192

103

114

125

136

147

158

17

16

DS

Q506

2N7002

G

DS

U501

PACDN006/NA SSOP8

1

2

3

4

8

7

6

5

R2100K0603

12

DS

Q502

2N7002

G

DS

C1100P060310%

12

R1

1K0603

1 2

R1Q2

DTC144TKA

2

13

D20PG1102WAK

D23

PG1102W

AK

R1 Q21DTC144TKA

2

13

CP122P*4/NA1206

1234

8765

R2644700603

12

R86910K0603

12

CP50222P*41206

1234

8765

F502mircoSMDC110/NA

12

CP50122P*41206

1234

8765

D21PG1102WAK

C50310U_NA

10V1206

12

R505 470K0603

1 2

L502130Z/100M 16081 2

RP4010K*41206

1234

8765

RP1

1K*41206

1234

8765

L501130Z/100M 16081 2

JL1

SHORT-SMT3

1 2

JL501

SHORT-SMT3

1 2

G

DS

Q503NDS9410 SO8

876

4

523

1

C8090.1U

50V0603

12

C21000P0603

12

L504120Z/100M 2012

1 2

D22PG1102WAK

R2014700603

12

C5060.1U

50V0603

12

RP50275*41206

1234

8765

L503130Z/100M 16081 2

R19910K0603

12

R1 Q17DTC144TKA

2

13

C50810U_NA

10V1206

12

R1574700603

12

U516C

74AHC14_V/NATSSOP14

5 6

147

R1564700603

12

U516B

74AHC14_V/NATSSOP14

3 4

147

C5091000P0603

12

R1 Q526

DTC144TKA/NA

2

13

C5070.1U

50V0603

12

LED_DATA22

-H8_RESET22

LED_CLK22

CRT_RED7

CRT_HSYNC7

CRT_BLUE7

CRT_VSYNC7

CRT_DDDA7

CRT_GREEN7

CRT_DDCK7

-AC_POWER 27

-BATT_R 27-BATT_G 27

-SCROLL22-NUM22-CAP22

LCD_ID07

ENAVDD 9

TX2OUT2+9TXOUT0- 9

TXCLK+ 9

TXOUT2-9TXOUT2+9

TXCLK- 9

TX2OUT1- 9

TX2CLK-9

TX2OUT2-9

LCD_ID17

TX2OUT1+ 9

TX2CLK+9

LCD_ID27

TXOUT0+ 9

TX2OUT0+9

TXOUT1+ 9TXOUT1- 9

TX2OUT0-9

PSON15,24,27

-BATT_LED 27

ACPILED15

CRT_IN# 15

MPCI_PD15,28

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

A A

B B

C C

D D

Layout note: Place crystal within500 mils of CLK Gen.

CLOCK GEN/BUFFER

Bit 7 Bit 6 Bit 4 Bit 5FS4 FS3 FS2 FS1 FS0

CPU(MHz)

SDRAM(MHz)

ZCLK(MHz)

AGP(MHz)

0 0 0 0 0100 0000 00 1

0 00 110 0 00 1

10 00 100 011

10 1 10

100

01 11

0

01

0 0

01

1

00

00

1

00 11 01010 1

11 00 111 10 1

66.67 66.67 66.67 66.67100.00 100.00 66.6766.67

66.67100.00 200.00 66.67133.33 66.67 66.67100.00

100.00 150.00 60.00 60.00100.00 125.00 62.50 62.50100.00100.00

160.00 66.6766.67133.33 66.6780.00

66.67 66.67200.00100.00100.00 166.67 62.5062.50

166.67100.00 71.43 83.3366.6766.67133.3380.00

80.00 66.67 66.67133.3395.00 95.00 63.33 63.33

66.67 66.67 50.00 50.0063.3363.33126.6795.00

Bit 2

V

CLOSETOU525

USE WIRE JUMPING WHEN DEBUG PORT IS INSTALLED

BD 311671700001 & TU 411671700011 01

8575A MAIN CLOCK & CLOCK BUFFER

C

11 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

HCLK_CPU#

REFCLK1

REFCLK1

ZCLK1

HCLK_CPU

FS3

REFCLK0

FS3

HCLK_CPU#

USBCLK_SB

REFCLK0

ZCLK0

CLK_SBPCI

HCLK_SIS650#

CLK_CARDPCI

CLK_SIO

HCLK_SIS650

CLK_SIO

HCLK_SIS650

SDRAMCLK

HCLK_SIS650#

BF_OUT

CLK_SBPCI

FS4

USBCLK_SB

FS1

HCLK_CPU

ZCLK0

CLK_LPC33

AGP_CLK

FS4

FS0

SDRAMCLK

FS2

ZCLK1

CLK_LPC33

CLK_CARDPCI

SMBCLKSMBDATA

BF_OUT

CLK_DDR0

CLK_DDR4

CLK_DDR3#CLK_DDR3

CLK_DDR4#

CLK_DDR1CLK_DDR1#

CLK_DDR5

CLK_DDR2#

CLK_DDR0#

CLK_DDR5#

CLK_DDR2

CBVDD

FWDSDCLKO

FS0

REFCLK3

SMBCLKSMBDATA

VDDZ

VDDAGPVDDCPU

VDDA48

VDDREF

VDDZ

VDDAGP

VDDSD

VDDPCI

VDDREF

VDDA48

VDDCPU

VDDSD

VDDPCI

CBVDDACBVDD

CBVDDA

CLK_DDR0#

CLK_DDR0

CLK_DDR1

CLK_DDR1#

BF_OUT

CLK_DDR4

CLK_DDR3#

CLK_DDR2

CLK_DDR2#

CLK_DDR3

CLK_DDR4#

CLK_DDR5

CLK_DDR5#

14.318MHZ_AUDIO

14.318MHZ_AUDIO

REFCLK3

AGP_CLK

FS1

14.318MHZ_TV

14.318MHZ_TV

CLK_1394PCI

CLK_1394PCI

FS2

CLK_MINIPCI

CLK_MINIPCI

SMBCLK

SMBDATA

CPU_STP#

+VCC_CORE

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+2.5V_DDR +2.5V_DDR

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

+3VS

+3VS

R645 49.9 1% 0603D1 2

L20

130Z/100M1608

1 2

R85 4750603

1%1 2

C8522U

10V1210

12

R635 331 2

C10922U

10V1210

12

C196 10P 0603D1 2

C9722U

10V1210

12

C104 10P/NA 0603D1 2

R650 4.7K1 2

R93 01 2

R625 331 2

R88 01 2

C1130.1U

50V0603

12

R648 331 2

C70110P06035%

12

L17

130Z/100M1608

1 2

C1140.1U

50V0603

12 R268

10K0603

12

C1070.1U

50V0603

12

L23

130Z/100M1608

1 2

R94 01 2

L22

120Z/100M2012

1 2

R101 01 2

R669 4.7K1 2

C7181000P0603

12

R637 4.7K1 2

R667 221 2

R624 4.7K1 2

C900.1U

50V0603

12

R638 331 2

C706 10P/NA 0603D1 2

R630 331 2

Q516MMBT3904L

B

EC

R656 331 2

C713 10P/NA 0603D1 2

R90 01 2

C725 10P/NA 0603D1 2

R670 221 2

R102 01 2

R649 49.9 1% 0603D1 2

C1011000P0603

12

R639 331 2

R641 221 2

C9910U

10V1206

12

R640 49.9 1% 0603D1 2

C720 10P/NA 0603D1 2

C910.1U

50V0603

12

C724 10P/NA 0603D1 2

C7190.1U

50V0603

12

Q517MMBT3904L

B

EC

C704 10P/NA 0603D1 2

R103 01 2

C812 10P/NA 0603D1 2

C717 10P/NA 0603D1 2

R636 49.9 1% 0603D1 2

R83 331 2

X502

14.318MHZ

1 324

R644 331 2

C89 10P/NA 0603D1 2

R98 01 2

D520 RLS4148/NAAK

L520

120Z/100M2012

1 2

R628 33/NA1 2

R67810K0603

12

C705 10P/NA 0603D1 2

R629 33/NA1 2

R626 4.7K1 2

R89 01 2

C721 10P/NA 0603D1 2

C1080.1U

50V0603

12

R836 4.7K 06031 2

R99 221 2

R756 331 2

C960.1U

50V0603

12

R837 4.7K 06031 2

R632 221 2

L19

130Z/100M1608

1 2

R633 331 2

C92 10P/NA 0603D1 2

C1110.1U

50V0603

12

C813 10P/NA 0603D1 2

R661 221 2

C980.1U

50V0603

12

C703 10P/NA 0603D1 2

C134 10P/NA 0603D1 2

C1100.1U

50V0603

12

R622 49.9/NA1% 0603D1 2

C197 10P/NA 0603D1 2

C7150.1U

50V0603

12

R623 49.9/NA1% 0603D1 2

C195 10P/NA 0603D1 2

U9

ICS93722SSOP28A

12

45

7

1314

1617

19

20

22

2425

2627

3

8

9

10

12

1821

23

6111528

CLKC0CLKT0

CLKT1CLKC1

SCLK

CLKT2CLKC2

CLKC3CLKT3

FB_OUTT

FBINT

SDATA

CLKT4CLKC4

CLKT5CLKC5

VDD0

CLK_INT

N/C2

VDDA

VDD1

N/C1N/C0

VDD2

GND0GND1GND2GND3

R668 331 2

C135 10P/NA 0603D1 2

R91 01 2

C1120.1U

50V0603

12

C194 10P/NA 0603D1 2

R97 01 2

C1500.1U

50V0603

12

C199 10P/NA 0603D1 2

R660 331 2

C200 10P/NA 0603D1 2

C711 10P/NA 0603D1 2

R646 221 2

C198 10P/NA 0603D1 2

L24

120Z/100M2012

1 2

C70210P06035%

12

U508

ICS952001SSOP48

1

234

5

6 7

8

910

11

12

13

14151617

18

19

20212223

2425

2627

2829

3031

32

33

3435

36

37

38

3940

41

42

434445

46

47

48

VDDREF

**FS0/REF0**FS1/REF1**FS2/REF2

GNDREF

X1 X2

GNDZ

ZCLK0ZCLK1

VDDZ

*PCI_STOP#

VDDPCI0

**FS3/PCICLK_F0**FS4/PCICLK_F1

PCICLK0PCICLK1

GNDPCI0

VDDPCI1

PCICLK2PCICLK3PCICLK4PCICLK5

GNDPCI1GND48

24_48MHZ/MULTISEL*48MHZ

VDDA48VDDAGP

AGPCLK1AGPCLK0

GNDAGP

PD#*/VTT_PWRGD

SDATASCLK

VDDA

GNDA

IREF

CPUCLKC_0CPUCLKT_0

GNDCPU

VDDCPU

CPUCLKC_1CPUCLKT_1CPU_STOP#*

GNDSD

SDRAM

VDDSD

R662 331 2

C722 10P/NA 0603D1 2

C105 10P/NA 0603D1 2

R87510K0603

12

R658 331 2

R67310K0603

12

C102 10P/NA 0603D1 2

L21

130Z/100M1608

1 2

R755 331 2

C103 10P/NA 0603D1 2

L16

130Z/100M1608

1 2

L18

130Z/100M1608

1 2

R100 01 2

C940.1U

50V0603

12

R66410K0603

12

C950.1U

50V0603

12

SMBDATA 12,15SMBCLK 12,15

CLK_DDR0 12

CLK_DDR1# 12

CLK_DDR2 12

CLK_DDR5# 12

CLK_DDR4 12

CLK_DDR5 12

CLK_DDR1 12

CLK_DDR3# 12CLK_DDR3 12

CLK_DDR2# 12

CLK_DDR0# 12

CLK_DDR4# 12

ZCLK0 7

CLK_LPC33 21

REFCLK0 7REFCLK1 15

USBCLK_SB 16

ZCLK1 14

CLK_SBPCI 14

HCLK_CPU 4HCLK_CPU# 4

HCLK_SIS650 6HCLK_SIS650# 6

CLK_CARDPCI 18

AGP_CLK 6

CLK_SIO 21

SDRAMCLK 7

REFCLK3 1514.318MHZ_AUDIO 20

14.318MHZ_TV 9

FWDSDCLKO7

CLK_1394PCI 29

CLK_MINIPCI 28

CPU_STP#15

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

DDR SODIMM

PLACE CLOSE TO J507

PLACE CLOSE TO J508

PLACE CLOSE TO J507PLACE CLOSE TO J508

BD 311671700001 & TU 411671700011 01

8575A DDR SO-DIMMs

C

12 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

CKE0CKE1CKE2CKE3

CLK_DDR0#CLK_DDR0

CLK_DDR1CLK_DDR1#

CLK_DDR3CLK_DDR3#

CLK_DDR2#CLK_DDR2

CLK_DDR5

CLK_DDR4CLK_DDR4#

CLK_DDR5#

DDR_CAS#DDR_WE#

DDR_CS3#DDR_CS2#

MD42

CS0#

MA12

MD52

MD38

DQM1

CLK_DDR0#

DQS5

MA5

DQM7

MD44

MD11MD10

MD35

MD34

WE#

CKE1

MA0

MD29

SMBCLK

MD41DQM5

CAS#

CKE0

MD14

MD12

MD0

MD51

MD43

MD32

MA3

MA9

CLK_DDR1#

MD47

BA1

DQM2

MD8

MD2

MD1

MD40

MD46

MD20

MD63

MD53

MA4

MD22

MD13

MD6

DQS6

MD48

MD54

RAS#

MD4

MD9

MD58

MD56

MA1

MD24

MD16

MD60MD55

MA2

MD30

DQS7

MD37

MA11

MD50

MD19

MA8

MD28

MD15

MD57

MD49

MD18

MD17

MD45

DQS0

MD59

MD33

MA10

MD27

MD25

DQM4

MD31

MD21

MD62

MD61

MD39

MD23

MD7

CLK_DDR0

MA7

DQM0

DQS1

MD3

SMBDATA

BA0

MD26

DQS3

DQS2

DQM6

CLK_DDR1

CS1#

MA6

MD5

DQS4

CLK_DDR2#CLK_DDR2

MD36

DQM3

MD42

CS2#

MA12

MD52

MD38

DQM1

CLK_DDR3#

DQS5

MA5

DQM7

MD44

MD11MD10

MD35

MD34

WE#

CKE3

MA0

MD29

SMBCLK

MD41DQM5

CAS#

CKE2

MD14

MD12

MD0

MD51

MD43

MD32

MA3

MA9

CLK_DDR4#

MD47

BA1

DQM2

MD8

MD2

MD1

MD40

MD46

MD20

MD63

MD53

MA4

MD22

MD13

MD6

DQS6

MD48

MD54

RAS#

MD4

MD9

MD58

MD56

MA1

MD24

MD16

MD60MD55

MA2

MD30

DQS7

MD37

MA11

MD50

MD19

MA8

MD28

MD15

MD57

MD49

MD18

MD17

MD45

DQS0

MD59

MD33

MA10

MD27

MD25

DQM4

MD31

MD21

MD62

MD61

MD39

MD23

MD7

CLK_DDR3

MA7

DQM0

DQS1

MD3

SMBDATA

BA0

MD26

DQS3

DQS2

DQM6

CLK_DDR4

CS3#

MA6

MD5

DQS4

CLK_DDR5#CLK_DDR5

MD36

DQM3

DDR_DQM3

DQS6

DQS0DDR_DQS0

DDR_DQS3

DQS5

DDR_DQM2

DQS3

DDR_DQM0

DQS1

DDR_CS0#DDR_CS1#

DDR_DQM5

DDR_DQS6

DDR_DQM6

DDR_DQS5

DDR_MD38

DDR_MD53

DDR_MD46

DDR_MD61DDR_MD57

DDR_MD41

DDR_MD25

DDR_MD6

DDR_MD43

DDR_MD42

DDR_MD28

DDR_MD63DDR_MD59

DDR_MD45

DDR_MD21

DDR_MD52

DDR_MD58

DDR_MD23

DDR_MD1

DDR_MD48

DDR_MD47

DDR_MD39

DDR_MD40

DDR_MD49

DDR_MD5

DDR_MD24

DDR_MD0

DDR_MD31

DDR_MD29

DDR_MD51

DDR_MD62

DDR_MD7

DDR_MD27

DDR_MD55

DDR_MD44

DDR_MD19

DDR_MD22

DDR_MD54

DDR_MD50

DDR_MD60

DDR_MD56

DDR_MD30

DDR_DQM7

DDR_MD26

DDR_DQS7

DDR_MD4

MD0

MD48

MD31

MD51

MD12

MD47

MD13

MD3

MD58

DQM3

MD29

MD8

MD6

DQM5

MD7

MD46

MD63

MD45

MD49

MD57

DQS7

MD30

MD50

MD60

MD26

MD5

MD24

MD28

DQM6

DQM0

MD43

MD56

MD42

MD44

MD62

DQM1

DQM2

MD39

MD9

MD38

MD22

MD25

MD2

MD19

MD4

MD59

MD52

MD23

MD40

MD54

MD61

MD41

MD21

MD53

MD18

MD1

MD55

MD27

DQM7

CAS#WE#

CS3#CS2#CS0#CS1#

DDR_MD15

DDR_MD14

DDR_MD16

DDR_MD11

DDR_MD17

DDR_MD10

DDR_MD20DDR_DQS2

MD17

MD15

MD14

DQS2MD20

MD11

MD16

MD10

DDR_MD2

DDR_DQM1

DDR_MD13

DDR_MD9

DDR_MD8

DDR_MD18

DDR_MD12

DDR_MD3

DDR_DQS1

DQM4

DDR_MD34

MD32

MD34MD33

DDR_MD32DDR_MD37

DDR_MD33MD36

MD35

DQS4MD37

DDR_DQM4DDR_MD36

DDR_MD35

DDR_DQS4

MA3DDR_RAS#

DDR_MA9

MA2

MA6

MA10

DDR_MA3

DDR_MA1

MA5

MA9

DDR_MA5

DDR_MA7MA11

DDR_MA2

DDR_MA6

MA12

DDR_MA4

DDR_MA0

DDR_BA0

BA1DDR_MA11

MA1

DDR_MA10

MA7

BA0

MA8DDR_MA12DDR_MA8

MA0

MA4

RAS#

DDR_BA1

GNDGND

+2.5V_DDR+2.5V_DDR

GNDGND

GND

+2.5V_DDR

+DDRVREF +DDRVREF

+DDRVREF+2.5V_DDR

GND GND GND

+2.5V_DDR

GND+2.5V_DDR

C1470.1U

0603D

12

C1460.1U

0603D

12

C1060.1U

50V0603

12

C1450.1U

0603D

12

C1440.1U

0603D1

2

J505

0.6MM/200P/H5.2AMP1376408-1

13579

111315171921232527293133353739

246810121416182022242628303234363840

4244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144146148150152154156158160162164166168170172174176178180182184186188190192194196198200

414345474951535557596163656769717375777981838587899193959799

101103105107109111113115117119121123125127129131133135137139141143145147149151153155157159161163165167169171173175177179181183185187189191193195197199

C1421U

0603D

12

C1371U

0603D

12

C1361U

0603D

12

C1411U

0603D

12

C1391U

0603D

12

RP12 10*8 RPX812345678 9

10111213141516

C1401U

0603D

12

C5881000P0603

12

C1301000P0603

12

RP18 10*8 RPX812345678 9

10111213141516

RP13 0*8 RPX812345678 9

10111213141516

RP20 10*8 RPX812345678 9

10111213141516

RP14 0*8 RPX812345678 9

10111213141516

RP15 0*8 RPX812345678 9

10111213141516

RP19 10*8 RPX812345678 9

10111213141516

RP17 10*8 RPX812345678 9

10111213141516

RP16 10*8 RPX812345678 9

10111213141516

RP11 10*8 RPX812345678 9

10111213141516

RP10 10*8 RPX812345678 9

10111213141516

C13210U

10V1210

12

C10010U

10V1210

12

C13310U

10V1210

12

C1381U

0603D

12

RP9 10*8 RPX812345678 9

10111213141516

RP8 10*8 RPX812345678 9

10111213141516

J506

0.6MM/200P/H5.2AMP1376409-1

13579

111315171921232527293133353739

246810121416182022242628303234363840

4244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144146148150152154156158160162164166168170172174176178180182184186188190192194196198200

414345474951535557596163656769717375777981838587899193959799

101103105107109111113115117119121123125127129131133135137139141143145147149151153155157159161163165167169171173175177179181183185187189191193195197199

C1430.1U

0603D

12

C1480.1U

50V0603

12

R951K06031%

12

R5561K06031%

12

SMBCLK11,15

CKE07CKE17CKE27CKE37

CLK_DDR011CLK_DDR0#11CLK_DDR111

CLK_DDR1#11

CLK_DDR2#11CLK_DDR211

CLK_DDR3#11CLK_DDR311

CLK_DDR5#11

CLK_DDR411CLK_DDR4#11CLK_DDR511

SMBCLK11,15SMBDATA11,15 SMBDATA11,15

DDR_CS0#7DDR_CS1#7

DDR_WE#7DDR_CAS#7

DDR_CS3#7DDR_CS2#7

CAS# 13WE# 13

CS3# 13CS2# 13CS0# 13CS1# 13

MD32 13MD37 13DQS4 13DQM4 13

DDR_MD357

DDR_MD327

DDR_DQM47DDR_MD367

DDR_MD177

DDR_MD207

DDR_MD147

DDR_MD157DDR_MD167

DDR_DQS27

DDR_MD117DDR_MD107

MD16 13MD15 13

MD10 13MD11 13

MD17 13

MD20 13DQS2 13

MD14 13

DDR_MD67DDR_MD77

DDR_MD47DDR_MD57

DDR_DQM07DDR_MD07DDR_MD17

DDR_DQS07

DDR_MD247DDR_MD297

DDR_MD237DDR_DQM27DDR_MD227DDR_MD217DDR_MD197

DDR_MD307DDR_MD277DDR_MD287DDR_MD257DDR_DQS37DDR_MD317DDR_DQM37DDR_MD267

DDR_MD467DDR_MD427

DDR_MD397DDR_MD387DDR_MD457DDR_MD447DDR_MD407DDR_DQM57

DDR_MD417DDR_DQS57DDR_MD437DDR_MD477DDR_MD497DDR_MD557DDR_MD487DDR_MD547

DDR_MD577DDR_MD617

DDR_MD527DDR_DQM67DDR_MD537DDR_DQS67DDR_MD507DDR_MD517

DDR_MD627DDR_MD607DDR_DQM77DDR_DQS77DDR_MD637DDR_MD597DDR_MD567DDR_MD587

DDR_DQM17

DDR_MD97DDR_DQS17

DDR_MD137DDR_MD127

DDR_MD187

DDR_MD37DDR_MD87

DDR_MD27

MD4 13MD5 13DQM0 13MD0 13MD1 13DQS0 13MD6 13MD7 13

MD13 13

MD3 13

MD9 13MD12 13

MD8 13

MD2 13

DQM1 13DQS1 13

DQM2 13

MD19 13

MD18 13

MD22 13

MD23 13

MD24 13MD29 13

MD21 13

MD30 13

MD31 13DQS3 13

MD28 13MD27 13

MD26 13DQM3 13

MD25 13

MD45 13

MD46 13

MD40 13

MD42 13

MD38 13MD39 13

DQM5 13

MD44 13

DQS5 13

MD49 13MD47 13

MD48 13MD54 13

MD41 13

MD43 13

MD55 13

MD53 13

MD50 13

MD52 13

MD57 13

DQM6 13

DQS6 13

MD61 13

MD51 13

DQM7 13

MD63 13

MD62 13

MD56 13

MD60 13

DQS7 13

MD58 13

MD59 13

DDR_DQS47

MD33 13

DDR_MD377

DDR_MD337MD34 13DDR_MD347

MD36 13

MD35 13

RAS# 13

MA4 13

MA0 13DDR_MA107

DDR_BA07

DDR_MA87

DDR_BA17

DDR_MA57 MA5 13

DDR_MA07

MA6 13

MA2 13

DDR_RAS#7

DDR_MA17

DDR_MA77

MA3 13

BA0 13

BA1 13

MA10 13

DDR_MA37

DDR_MA97

MA12 13

MA9 13MA8 13

MA1 13

MA7 13DDR_MA117

DDR_MA127

DDR_MA27

DDR_MA67

MA11 13

DDR_MA47

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

THESE DECOUPLING CAPACITOR SHOULD BE PLACE WITHIN 150 Mils OF +1.25V THERMINATION R-PACKs

BD 311671700001 & TU 411671700011 01

8575A DDR TERMINATION

C

13 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

DQS4

MD33

MD32MD36

MD37

CS0#

CAS#

CS1#

WE#

CS2#CS3#

MA2MA6

BA0

MA10

MA4

DQM[0..7]

DQM4MD34MD35

DQS3

DQS0

DQS[0..7]

DQM3

DQM1

DQS6

DQS2

DQM0

DQM6

DQM7DQS7

DQM5

DQS5

DQS1

MA0

BA1RAS#

MA7MA5

MA9MA12

MA8MA11

MA1

MD18

MA3

DQM2

DQS5

DQS3DQS4

DQS6

DQS2DQS1DQS0

DQS7

DQM4

DQM2

DQM5

DQM3

DQM1

DQM6

DQM0

DQM7

MD24

MD57

MD55

MD61

MD56

MD25

MD39

MD10

MD22

MD19

MD38

MD43

MD17

MD11

MD42

MD2

MD[0..63]

MD1

MD48

MD46

MD51

MD44

MD4

MD28

MD47

MD16

MD12

MD63

MD58

MD31

MD62

MD40

MD0

MD52

MD13

MD53

MD15

MD20

MD3

MD30

MD6

MD45

MD5

MD14

MD54

MD7

MD50

MD9

MD41

MD27

MD60

MD21

MD29

MD49

MD59

MD26

MD8

MD23

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

+1.25V

+1.25V

+1.25V

+1.25V

+1.25V

+1.25V

+1.25V

C1781000P0603

12

C1740.1U

16V0603

12

C1771000P0603

12

C1540.015U0603

12

C1720.015U0603

12

C1920.015U0603

12

RP26 33*8 RPX8123456789

10111213141516 C162

0.1U

16V0603

12

C1790.1U

16V0603

12

C1821000P0603

12

RP25 33*8 RPX8123456789

10111213141516

C1511000P0603

12

RP33 33*8 RPX8123456789

10111213141516

C1551000P0603

12

C1531000P0603

12

C1931000P0603

12

C1570.1U

16V0603

12

C1660.1U

16V0603

12

C1851000P0603

12

RP23 33*8 RPX8123456789

10111213141516

C1680.1U

16V0603

12

RP27 33*8 RPX8123456789

10111213141516

C1650.1U

16V0603

12

C1610.1U

16V0603

12

C1590.1U

16V0603

12

RP21 33*8 RPX8123456789

10111213141516

RP29 33*8 RPX8123456789

10111213141516

RP22 33*8 RPX8123456789

10111213141516

RP24 33*8 RPX8123456789

10111213141516

C1830.1U

16V0603

12

C1580.1U

16V0603

12

C1861000P0603

12

C1710.1U

16V0603

12

C1631000P0603

12

C1690.1U

16V0603

12

C1810.1U

16V0603

12

RP32 33*8 RPX8123456789

10111213141516

RP30 33*8 RPX8123456789

10111213141516

C1670.1U

16V0603

12

RP31 33*8 RPX8123456789

10111213141516

RP28 33*8 RPX8123456789

10111213141516

C1760.1U

16V0603

12

C1641000P0603

12

C1880.1U

16V0603

12

C1911000P0603

12

C1601000P0603

12

C1890.1U

16V0603

12

C1750.1U

16V0603

12

C1560.1U

16V0603

12

C1800.1U

16V0603

12

C1840.1U

16V0603

12

C1701000P0603

12

C1520.015U0603

12

C1731000P0603

12

C1871000P0603

12

C1901000P0603

12

MD3212MD3612

DQS412

MD3312MD3712

MD[0..63]12

DQS[0..7]12

DQM[0..7]12

DQM412MD3412MD3512

WE#12CAS#12

CS1#12CS0#12

CS2#12CS3#12

MA1012MA612

BA012

MA212MA412

MA012RAS#12

BA112

MA1212MA912MA712MA512MA812MA1112MA312MA112

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Place near to 961 chip

SIS961(1/3)

BD 311671700001 & TU 411671700011 01

8575A SIS961 (1/3)

C

14 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

ZAD[0..15]

PCI_AD[0..31]

IDE_PDA1

PCI_INTA#

PCI_

AD22

PCI_C/BE#3

SZCMP_N

ZAD

5

IDE_SDA1

ZDREQ

ZAD

7

IDE_PDCS3#

PCI_GNT3#

PCI_STOP#

PCI_

AD1

PCI_

AD0

SZCMP_P

PCI_

AD26

PCI_

AD25

PCI_C/BE#0

SZ1XAVSS

ZAD

4

ZAD

1

IDE_SDCS1#

PCI_

AD18

IDE_SDDREQ

IDE_SDDACK#

PCI_

AD23

IDEAVDD

IDE_SIORDY

PCI_

AD15

SZ4XAVDD

PCI_

AD17

ZAD

6

PCI_REQ1#

PCI_

AD31

PCI_

AD7

SZCMP_N

PCI_DEVSEL#

IDE_PDIOR#

PCI_

AD2

IDE_IRQ15

IDE_PDIOW#

PCI_LOCK#

PCI_C/BE#1

IDE_SDCS3#

PCI_REQ0#

PCI_

AD10

PCI_

AD21

ZAD

11

PCI_

AD5

ZAD

13

ZAD

8

PCI_

AD3

ZSTB1

IDE_PDDACK#

PCI_INTD#

PCI_GNT4#

PCI_

AD14

PCI_

AD6

ZUREQ

SVDDZCMP

PCI_SERR#

PCI_

AD29

PCI_C/BE#2

PCI_REQ2#

SZ4XAVSS

PCI_

AD13

SVSSZCMP

IDE_PIORDY

IDE_PDCS1#

SZVREF

PCI_TRDY#

SVDDZCMP

PCI_INTC#

ZAD

14

IDE_SDIOW#

ZAD

3

ZAD

10

ZSTB1#

PCI_

AD30

IDE_PDA0

PCI_

AD8

ZAD

0

PCI_GNT0#

SVSSZCMPSZVREF

PCI_

AD12

IDEAVSS

PCI_

AD9

IDE_SDIOR#

PCI_

AD16

SZ1XAVDD

PCI_

AD28

PCI_PAR

PCI_INTB#

SZCMP_P

IDEAVSS

ZSTB0

IDE_SDA2

PCI_IRDY#

PCI_REQ4#

PCI_

AD11

IDE_IRQ14

SZ1XAVDD

ZAD

12

PCI_

AD4

SZ1XAVSS

PCI_

AD20

IDE_PDA2

PCI_GNT1#

PCI_REQ3#IDEAVDD

-PCIRST

PCI_

AD24

PCI_

AD27

ZAD

15

SZ4XAVDD

IDE_PDDREQ

PCI_FRAME#

PCI_GNT2#

SZ4XAVSS

PCI_

AD19

ZAD

9

ZAD

2

ZSTB0#

IDE_PDD0IDE_PDD1IDE_PDD2IDE_PDD3IDE_PDD4IDE_PDD5IDE_PDD6IDE_PDD7IDE_PDD8IDE_PDD9IDE_PDD10IDE_PDD11IDE_PDD12IDE_PDD13IDE_PDD14IDE_PDD15

IDE_SDD0IDE_SDD1IDE_SDD2IDE_SDD3IDE_SDD4IDE_SDD5IDE_SDD6IDE_SDD7IDE_SDD8IDE_SDD9IDE_SDD10IDE_SDD11IDE_SDD12IDE_SDD13IDE_SDD14IDE_SDD15

ZCLK1

CLK_SBPCI

ZSTB0#

ZSTB0

ZSTB1#

ZSTB1

SZVSSREF

IDE_PDD[0..15]

IDE_SDD[0..15]

SZVSSREF

+1.8VS

+1.8VS

GND

GND

+1.8VS

GND

+1.8VS

GND GND

+3VS

GND

+3VS

R605 56 06031%

1 2

R676 56 06031%

1 2

L517

120Z/100M2012

1 2

U14A

SIS961BGA335_36

F1F2E1H5F3

H3G1G2G3H4

K3M4P1R4

E3F4E2G4

M3M1M2N4

M5N3N1N2

Y2C3

V20

N19N20

K20K19

N16N17

R19N18

R18P18

U20U19

T20T19

R20P20

J5 J4 H2

H1

J3 K4 J2 J1 K5 K2 L3 K1 L1 L4 L5 L2 N5

P2 P3 P4 R2

R3

R1

T1 P5 T2 U1

U2

T3 R5

U3

V1

Y3Y4

W10V10Y11U12

V11Y9Y10

T11U11W11

T12V12

W17Y17T16U17

T14W16V16

Y18T15

V17U16W18

U10V9W8T9Y7V7Y6Y5W6U8W7V8U9Y8T10W9

Y16V15U14W14V13T13Y13Y12W12W13U13Y14V14W15Y15U15

M18

M19

M17

M16

M20

L16

L20

L18

K18

J20

K17

K16

H20

J18

H19

H18

PREQ4#PREQ3#PREQ2#PREQ1#PREQ0#

PGNT4#PGNT3#PGNT2#PGNT1#PGNT0#

C/BE3#C/BE2#C/BE1#C/BE0#

INTA#INTB#INTC#INTD#

FRAME#IRDY#TRDY#STOP#

SERR#PARDEVSEL#PLOCK#

PCICLKPCIRST#

ZCLK

ZSTB0ZSTB0#

ZSTB1ZSTB1#

ZUREQZDREQ

VDDZCMPZCMP_N

ZCMP_PVSSZCMP

Z1XAVDDZ1XAVSS

Z4XAVDDZ4XAVSS

ZVREFZVSSREF

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

AD16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0 IDEAVDD

IDEAVSS

ICHRDYAIDREQA

IIRQACBLIDA

IIORA#IIOWA#

IDACKA#

IDSAA2IDSAA1IDSAA0

IDECSA1#IDECSA0#

ICHRDYBIDREQB

IIRQBCBLIDB

IIORB#IIOWB#

IDACKB#

IDSAB2IDSAB1

IDSAB0IDECSB1#IDECSB0#

IDA0IDA1IDA2IDA3IDA4IDA5IDA6IDA7IDA8IDA9

IDA10IDA11IDA12IDA13IDA14IDA15

IDB0IDB1IDB2IDB3IDB4IDB5IDB6IDB7IDB8IDB9

IDB10IDB11IDB12IDB13IDB14IDB15ZA

D0

ZAD

1ZA

D2

ZAD

3ZA

D4

ZAD

5ZA

D6

ZAD

7ZA

D8

ZAD

9ZA

D10

ZAD

11ZA

D12

ZAD

13ZA

D14

ZAD

15

C70010U

10V1206

12

JL521

JP_NET20

1 2

R1091500603D

12

C6420.1U

50V0603

12

C2120.01U0603

12

TP5171

R1161500603D

12

JL531

JP_NET20

1 2

JL519

JP_NET20

1 2

L524

120Z/100M2012

1 2

C31210U

10V1206

12

JL514

JP_NET20

1 2

RP516

4.7K*4/NA1206

1234

8765

L38

120Z/100M2012

1 2

TP5161

C2020.1U

50V0603D

12

C2130.01U0603

12

C2660.1U

50V0603

12

C2060.1U

50V0603

12

C5920.01U0603

12

C2070.1U

50V0603

12

C25710U

10V1206

12

C2080.1U

50V0603D

12

L26

120Z/100M2012

1 2

JL520

JP_NET20

1 2

C2650.01U0603

12

IDE_IRQ15 17

PCI_SERR#17,18,28,29

PCI_GNT1#17,29

IDE_SDIOR# 17

IDE_PDDACK# 17

IDE_PIORDY 17

PCI_AD[0..31]18,28,29

IDE_SIORDY 17PCI_INTD#17,28

IDE_PDD[0..15] 17

PCI_PAR17,18,28,29

IDE_PDA2 17

IDE_SDIOW# 17

PCI_REQ2#17,28PCI_REQ1#17,29

PCI_INTA#7,9,17

IDE_SDCS1# 17

ZSTB1#7

PCI_FRAME#17,18,28,29

PCI_DEVSEL#17,18,28,29

PCI_STOP#17,18,28,29

PCI_REQ0#17,18

IDE_SDA1 17

IDE_PDDREQ 17

PCI_GNT0#17,18

IDE_PDCS1# 17

ZSTB0#7ZSTB07

IDE_PDA0 17

PCI_REQ3#17

PCI_C/BE#[0..3]18,28,29

PCI_INTB#17,18

IDE_SDD[0..15] 17

IDE_PDA1 17

PCI_GNT3#17

IDE_SDDREQ 17

IDE_SDA2 17

IDE_SDCS3# 17

ZSTB17

IDE_SDA0 17

IDE_PDIOR# 17

PCI_TRDY#17,18,28,29PCI_IRDY#17,18,28,29

IDE_PDIOW# 17

ZUREQ7ZDREQ7

IDE_IRQ14 17

PCI_GNT2#17,28

IDE_PDCS3# 17

IDE_SDDACK# 17

PCI_INTC#17,28,29

ZAD[0..15]7

PCI_REQ4#17

PCI_GNT4#17

ZCLK111

CLK_SBPCI11-PCIRST7,9,17,18,21,28,29

PCI_LOCK#17

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

A A

B B

C C

D D

Need very close to 961SIS961(2/3)

Need no close to 961 chip

Need no close to 961 chip

PLACE CLOSE TO 961

Need very close to 961

Close to 961 chip

close to 961

BD 311671700001 & TU 411671700011 01

8575A SIS961 (2/3)

C

15 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

MIIAVSS

LAN_MTXC

H_INIT#

AUXOK

LAN_COL

H_STPCLK#SLP#

H_FERR#

H_A20M#

LAN_MRXD3

RTC_X1

-PME

H_NMI

LAN_MRXER

GPIO11

AC97_SDIN

LAN_MRXD2

OSC25MHI

MDC_SDIN

H_INTR

BATOK

AC97_RST#

LAN_MRXD1

LAN_MTXE

LAN_MRXDV

PWROK

H_SMI#

REFCLK3

RTC_X2

LAN_CRS

LPC_DRQ#

LAN_MRXC

LCD_ID3

LPC_FRAME#

AC97_SDOUTMIIAVDD

H_IGNNE#

LAN_MRXD0

AC97_BITCLK

SERIRQ

MIIAVDD

GPIO11

RTC_X2

RTC_X1

LPC_AD1

LPC_DRQ#

LPC_AD2LPC_AD3

LPC_AD0LPC_AD1

SIS_PWRBTN#

PSON#

SMBDATASMBCLK

REFCLK1

LPC_AD2

LPC_AD3

SERIRQLPC_AD0

-PME

MIIAVSS

SB_SPKRENTEST

LAN_MTXD0

LAN_MTXD2

LAN_MTXD1

LAN_MTXD3

LAN_DATAIO

LAN_DCLK

AC97_SDIN

MDC_SDIN

AUXOK

BATOK

-SUSC

CD_RST

PSON#

S3AUXSW#

AC97_SYNC

OSC25MHI

MB_ID0

MB_ID1

LCD_ID3

H8_SUSC

-SUSC

PSON

PSON#

MB_ID0 MB_ID1

-EXTSMI-SB_THRM

S3AUXSW#-SCI-WAKE_UP

MPCIACT#VR_GATE

OSC25MHO

CPU_STP#

VR_HI/LO#

CPU_STP#

AC97_BITCLK

VR_HI/LO# GND

+VCC_RTC

GNDGND

GND

GND

+3V

+3V

+3V

GND

+3VS

GND

GND

GND

+3V

GND GND

GND GND GND

GNDGND GND GND

+3VA

+VCC_RTC

+3V

GND

GND

GND

+5VA

GND

+3VA

GND

+3V

GND

GND

+5V

GND

GNDGND

+3VS

GND

+5V+5V

GND

+3VS

GND

+3VS

+3VS

+3V

+3VS

GND

R86210K/NA0603

12

R255 0 06031 2

R1Q513DTC144TKA

2

13

C2820.01U0603

12

R851 10K 06031 2

C25522U

10V1210

12

R853 10K/NA1 2

C2561U0603

12

R188 0/NA0603

1 2

JL545

JP_NET10

1 2

C2791U0603

12

JL546

JP_NET10

1 2

C78222U

10V1210

12

JL547

JP_NET10

1 2

R258 0 06031 2

R71610K0603

12

R28210K0603

12

R705

1K 0603

1 2

R1 Q522DTC144TKA

2

13D514

BAW56

2

13

R259 0 06031 2

R70810K0603

12

R70710K0603

12

C24047P/NA0603

12

R279 0 06031 2

R251 10K 06031 2

R153

22/NA0603D

1 2

R620 00603D_DFS

1 2

C2340.01U/NA0603D

12

R244

10M/NA0603

1 2

R715 4.7K 0603D1 2

R746 22 06031 2

R702100K 0603D

12

C81110P/NA060310%

12

R181100K 0603D

12

R18910M0603D

12

R6194.7K0603D

12

X532.768KHZCM200

14

R265 10K/NA 06031 2

R729 4.7K 0603D1 2

U14B

SIS961BGA335_36

T18P16R17R16Y20U18T17

W20V19

Y19V18

W19

V5T7U6W5

C2

D2

A8

A6

B6

E8

D7

C6

B4

A7

C7

C8

D8

A5

B5

A4

B7

E9

C5

E7

B9B8

D3D1

C1

E4

B2A1

A2D5

W2T5

D6Y1

W3G5V3

A14B14D14

A3A15

B1

E5

E13

A16

D13

B15

V2

T8

T4

T6

W1

U5

U4

C4

C14

E6

B3

F5

D4

W4U7V6

INIT#A20M#SMI#INTRNMIIGNNE#FERR#STPCLK#CPUSLP#

APICCKAPICD0APTCD1

LAD0LAD1LAD2LAD3

OSC32KHI

OSC32KHO

MIICLK25M

MIITXCLK

MIITXEN

MIITXD0

MIITXD1

MIITXD2

MIITXD3

MIIRXCLK

MIIRXDV

MIIRXER

MIIRXD0

MIIRXD1

MIIRXD2

MIIRXD3

MIICOL

MIICRS

MIIMDC

MIIMDIO

MIIAVDDMIIAVSS

BATOKPWROK

RTCVDD

RTCVSS

GPIO20GPIO19

AC_SDIN0AC_SDIN1

AC_SDOUTAC_SYNC

AC_RESET#AC_BIT_CLK

OSCIENTESTSPK

PWRBTN#PME#PSON#

AUXOKACPILED

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

LFRAME#LDRQ#SIRQ

C30610P/NA060310%

12

R70100603D

1 2

C3050060310%

12

X4

25MHZ

1324

RP36

4.7K*41206

1234

8765

C75410U

10V1206

12

R850 10K/NA 06031 2

C2300.1U

50V0603

12

C2320.01U0603

12

C291

10P0603

1 2

R25310K/NA0603

12

C7800.1U

16V0603

12

J508

DF13-2P-1.25H

12

34

12

GND1GND2

R17233 06031 2

C11910P/NA0603

12

R266 10K/NA 06031 2

R16733 06031 2

R16633 06031 2

C283

2.2U0805C

12

C290

20P 0603

1 2

U17

AME8800AEEVSOT25

1234

5 GND0VIN

VOUTNC1

NC0

OSC1

25MHZ/NAOSC_TXC30CO

4

1

3

2

VDD

E/D

OUT

GND

C2884.7U/NA0805+80-20%

12

JL522

JP_NET20

1 2C2811U0603D

12

R257 100K 06031 2

L32

130Z/100M1608

1 2

R25610K0603

12

R17733 06031 2

R252 10K 06031 2

R17133 06031 2

D17

RLS4148

AK

R17833 06031 2

R840 0 0603D_DFS1 2

D16

RLS4148

AK

D513

RLS4148

AK

C27710U

10V1206

12

R250 10K 06031 2

R18451K0603

12

R852 10K 06031 2

R175

10K 0603

1 2

R5511M/NA0603

12

R18310K0603

12

R16210K0603

12

R254 0 06031 2

R68610K0603

12

R706100K0603

12

R1 Q13DTC114TKA

2

13

C7860.1U

50V0603

12

Q15MMBT3904L

B

EC

R71710K0603

12

R693 1K 06031 2

R18000603

12

R86310K0603

12

R68510K/NA0603

12Q14

MMBT3906L

B

E C

R62710K0603

12

R1Q524DTC144TKA

2

13

LAN_MRXDV 19

H_NMI4

SERIRQ18,21

LAN_MRXD0 19

LAN_MRXD3 19

LPC_FRAME#21

SB_SPKR16,20

H_961_FERR#4

LPC_DRQ#21LAN_MRXER 19

LAN_MRXD1 19

-EXTSMI 22

LAN_MTXE 19

CRT_IN# 10

LAN_COL 19

H_A20M#4

AC97_SDOUT16,19,20

H_INTR4

H_INIT#4

-SCI 22

H_SMI#4

LAN_MRXC 19

PWROK7

H_IGNNE#4

AC97_RST#19,20

H_STPCLK#4

-WAKE_UP 22

AC97_SDIN20

LAN_MTXC 19

LAN_MRXD2 19

MDC_SDIN19

LAN_CRS 19

H_SLP#4

LPC_AD121LPC_AD021

LPC_AD321LPC_AD221

SIS_PWRBTN#22

SMBDATA11,12SMBCLK11,12

REFCLK111

CPU_STP# 11

-SB_THRM 22

SPK_OFF 20

REFCLK311 LAN_MTXD1 19

LAN_MTXD2 19

LAN_MTXD0 19

LAN_MTXD3 19

LAN_DATAIO 19

LAN_DCLK 19

AC97_BITCLK19,20

AUXOK 7

-SUSC 22,24

-PME

ACPILED10

CD_RST 17

S3AUXSW#7,22

SPDIFOUT 20AC97_SYNC19,20

H8_SUSC22PSON10,24,27

DPRSLPVR26

MPCIACT#28

G_LO/HI#4

VR_GATE26

1394_PME#29

CARD_PME#18

MPCI_PME#28

OSC25MHO16

MPCI_PD10,28

CPU_DPSLP# 4

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

A A

B B

C C

D D

CLOSE TO 961

enable

1

USB_OC5# (Trap mode)

0

AC97_SDOUT (PCICLK PLL)

disable

ROM

disable

disable

PCI AD

enable

0SB_SPKR (LPC addr mapping)

USB_OC2# (SB debug mode)

1

enable

1

Default

0

SIS961(3/3)CLOSE TO 961

PLACE UNDER 961 SOLDER SIDE

SHOULD BE 433 1%

CLOSE TO 961

CLOSE TO 961

BD 311671700001 & TU 411671700011 01

8575A SIS961 (3/3)

C

16 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

USB_OC5#

USBP0_N

USBP3_P

USBP4_P

USBP1_P

USBP3_N

USBP1_N

USBP5_N

USBP2_NUSBP2_P

USBP4_NUSBP5_P

USB_OC5#

USB_OC2#

USB_OC2#

USBP0_P

USBCLK_SB

+3V

AC97_SDOUT

SB_SPKR

USB_OC0_1#

USB_OC5#USB_OC4#USB_OC3_5#

USBP0_P

USBP0_N

USBP2_PUSBP2_N

USBVSS

USBVDD

USBVSS

USBVDD

USBP3_P

USBP3_N

D0CTL1

D1D2D5D3

SCLK_1394D4D6D7

CTL0

LINKON

LREQ

LPSGPIO21_EESKGPIO22_EEDI

GPIO23_EEDOGPIO24_EECS

OSC12MHI

OSC12MHO

USBREF

USBPVDDUSBPVSS

IVDD_AUX

IVDD_AUX

USBREFAVDD

USBVDD

USBVDD

USBVSS

USBVSS

OSC25MHO

GPIO24_EECSGPIO21_EESKGPIO22_EEDIGPIO23_EEDO

USBREFAVDD

IVDD_AUX

USBPVSS

USBPVDD

USBREF

USBP1_P

USBP1_N

USBP4_N

USBP4_P

D0D1D2D3

D4D5D6D7

LREQLPS

CTL0CTL1SCLK_1394LINKON

OSC12MHO

OSC12MHI

USB_OC2#

USBP5_PUSBP5_N

+1.8VS

+3V

+3VS

+1.8V

+3V

+VCC_CORE

+1.8VS

+1.8VS

+3VS

+3VS +1.8VS

GND

+3V

+1.8V

+VCC_CORE

+3V

+1.8VS

+3VS

+3V

+3V

+3V

+1.8V+3V

GND

GND

GND

GND

GND

GNDGND

GND

GND

GNDGND GND

GND

GND

+3V

+3V

+3V

GND

GND

+1.8V +3V

GND

GND

USBVSS

USBVSS

GND GND

GND GND

GND

GND

GNDGND

U13

NM93C46/NASO8

1234 5

678CS

SKDIDO GND

NC0NC1VCC

C774 0.1U0603D

1 2

C1291U/NA0603

12

C773 0.1U0603D

1 2

C763 0.1U0603D

1 2

C12147P0603

12

C776 0.1U0603D

1 2

R142

22 0603D

1 2

R143

22 0603D

1 2

C7564.7U0805+80-20%

12

C747 0.1U0603D

1 2

C746 0.1U0603D

1 2

L539

120Z/100M/NA2012

1 2

C7440.1U

50V0603

12

JL544

JP_NET20

1 2

C8747P0603

12

C7610.01U0603

12

C31310U/NA

10V1206

12

R269 15K1 2

U512

AME8801MEEVSOT25

123 4

5VINGNDEN BYP

OUT

R757

432/NA06031%

1 2

R270 15K1 2

L523

120Z/100M2012

1 2

C7791U

06031 2

C7691U060310V

12

C12247P0603

12

C768 0.1U0603D

1 2

C758 0.1U0603D

1 2

C762 0.1U0603D

1 2

X2

12MHZ/NA

1324

C7451U0603

12

C7481U

06031 2

L538

00603

1 2

R160

10M/NA0603

1 2

C12420P/NA06035%

12

C12320P/NA06035%

12

R114 15K1 2

R1694.7K/NA0603

12

C12547P0603

12

R107 15K1 2

C1270.01U/NA0603

12

C772 0.1U0603D

1 2

C8647P0603

12

R75

22 0603D

1 2

C751 0.1U0603D

1 2

R158

22 0603D

1 2

C749 0.1U0603D

1 2C757 0.1U1 2

RP518

10K*4 1206

1234

8765

C1280.1U/NA

50V0603

12

C767 0.1U1 2

JL542

JP_NET20

1 2

R182 10K/NA1 2

C82410U/NA

10V1206

12

C12647P0603

12

R179 10K/NA1 2

C8160.1U/NA 50V

06031 2

C787 10U1 2

R164

0/NA0603

1 2

C775 0.1U0603D

1 2

C8447P0603

12

RP522

4.7K*8/NA 1206

12345 6

78910

C750 0.1U0603D

1 2

RP521

4.7K*8/NA 1206

12345 6

78910

R161

22 0603D

1 2

R163

22 0603D

1 2

R608 10K/NA1 2

C7661U

06031 2R148

22 0603D

1 2

R147

22 0603D

1 2

C8280.1U/NA

50V0603

12

C74310U

10V1206

12

C8290.01U/NA0603

12

C8347P0603

12

C753 0.1U1 2

R764

0/NA0603

1 2

U14C

SIS961BGA335_36

V4

B18C18E14D15E16E15D18D19E18F18G18G19

G20J16H17G17H16G16

D16F17

B17E19

G6H15L6M15R10R14R6

F12F9

H6K6M6P6R11R13R7R9

F10F11F14F15F7

J6N6R12R8

F13F8

K15

G15J15J17L15L17N15P17

P15R15

H10H11H12H13

H8H9

J10J11J12

J8J9

K10K11

K8K9

L10L11

L8L9

M10M11

M8M9

N10N11N12N13

N8N9

J13J19K12K13L12L13L19M12M13P19

C11A12B12C12A13D12E11E12B13C13

A19C16E17C19D20F20A20C17D17C20E20F19F16B16C15A18A17B20B19B11D11A11E10D9B10A10A9C9C10D10

USBCLK48M

UV0+UV0-UV1+UV1-UV2+UV2-UV3+UV3-UV4+UV4-UV5+UV5-

OC0#OC1#OC2#OC3#OC4#OC5#

USBVDD0USBVDD1

USBVSS0USBVSS1

IVDD0IVDD1IVDD2IVDD3IVDD4IVDD5IVDD6

IVDD_AUX0IVDD_AUX1

OVDD0OVDD1OVDD2OVDD3OVDD4OVDD5OVDD6OVDD7

OVDD_AUX0OVDD_AUX1OVDD_AUX2OVDD_AUX3OVDD_AUX4

PVDD0PVDD1PVDD2PVDD3

PVDD_AUX0PVDD_AUX1

PVDDZ

VDDZ0VDDZ1VDDZ2VDDZ3VDDZ4VDDZ5VDDZ6

VTT0VTT1

VSS0VSS1VSS2VSS3VSS4VSS5VSS6VSS7VSS8VSS9VSS10VSS11VSS12VSS13VSS14VSS15VSS16VSS17VSS18VSS19VSS20VSS21VSS22VSS23VSS24VSS25VSS26VSS27VSS28

VSSZ0VSSZ1VSSZ2VSSZ3VSSZ4VSSZ5VSSZ6VSSZ7VSSZ8VSSZ9

NC0NC1NC2NC3NC4NC5NC6NC7NC8NC9

NC10NC11NC12NC13NC14NC15NC16NC17NC18NC19NC20NC21NC22NC23NC24NC25NC26NC27NC28NC29NC30NC31NC32NC33NC34NC35NC36NC37NC38NC39

C8260.1U/NA

50V0603

12

R555 10K/NA1 2

C8250.01U/NA0603

12

C752 0.1U0603D

1 2

C82710U/NA

10V1206

12

C778 0.1U0603D

1 2

JL543

JP_NET20

1 2

C764 0.1U1 2

C8171U/NA

06031 2

C760 0.1U1 2

USBP0-27

USBP0+27

USBP3+27

USBP3-27

USB_OC0_1#27

USB_OC3_5#27

AC97_SDOUT 15,19,20

SB_SPKR 15,20

USBCLK_SB11

USBP1-27

USBP1+27

USBP5-27

USBP5+27

OSC25MHO 15

A

A

B

B

2 2

1 1

IDE INTERFACE

Prim

ary

EIDE

Conn

ecto

r

To Audio Codec

Close to IDE Connector

W/S=16/12/12/16 mils

Seco

ndar

y EI

DE

Con

nect

or

PCI BUS

ISA BUS

Close to IDE Connector

PLACE CLOSE TO CDROM CONNECTOR

terminating resistors should be place close to South Bridge

BD 311671700001 & TU 411671700011 01

8575A IDE INTERFACE & PULL-UPs

17 30Monday, June 17, 2002

C

Title

Size DocumentNumber

Rev

Date: Sheet of

PDD14

PDD10

PDD8

PDD15

PDD9

PDD11PDD12PDD13

PIORDY

PDDREQPDIOW#

PDDACK#

PDA0PDA1IRQ14

PDIOR#

PDA2

PDCS1#PDCS3#

SDCS1#

CABLE_SEL

SIORDY

CDROM_LEFT

SDA1

SDIOR#SDIOW#

SDA2

SDA0

-HDDACTP

SDD6

SDD4

SDD0

SDD12

SDD9

SDD3

SDD5

SDD2SDD13

SDD1SDD14

SDD10

SDD15

SDCS3#

SDD8

SDDACK#

SDD11

SDD7

IRQ15

CDROM_RIGHT

PCI_LOCK#

PCI_STOP#

PCI_GNT0#PCI_GNT1#PCI_GNT2#PCI_GNT3#

PCI_REQ3#

SA0SA1SA2SA3

SA12SA13SA14SA15

-P_INIT

-P_STB

SA16SA17SA18SA19

IRQ1IRQ12

-IOR

SD5

SD7

SD4

SD6

-MCCS

SD[0..7]

-IOW-MEMR

+5VS_CD

IDE_RST#

IDE_RST#

CDROM_COMM

PCI_INTA#PCI_INTC#

PCI_INTB#PCI_REQ2#

CLKRUN#

PCI_REQ0#PCI_INTD#

PCI_REQ1#PCI_GNT4#

PCI_SERR#PCI_DEVSEL#

PCI_TRDY#PCI_FRAME#

PCI_IRDY#

PCI_REQ4#

-CDACTP

PCI_PERR#

SDDREQ

PDD0PDD1PDD2PDD3PDD4PDD5PDD6PDD7

IDE_PDD0IDE_PDD1IDE_PDD2IDE_PDD3IDE_PDD4IDE_PDD5

PDDACK#IDE_PDDACK#IDE_PDIOR#

IDE_PDA0IDE_PDA1IDE_PDA2

PDA0PDA1PDA2

IDE_PDCS3#

IDE_PDCS1#

PDCS3#

PDCS1#

IDE_PDIOW#PDIOR#PDIOW#PDD8

PDD9PDD10PDD11PDD12PDD13PDD14PDD15

IDE_PDD8IDE_PDD9IDE_PDD10IDE_PDD11IDE_PDD12IDE_PDD13IDE_PDD14IDE_PDD15

SDD4IDE_SDD5

SDD6

IDE_SDD3SDD2

IDE_SDD6

IDE_SDD0 SDD0

IDE_SDD7

IDE_SDD4

IDE_SDD2

SDD5

IDE_SDD1

SDD3

SDD1

SDD7

IDE_SDD14

SDD9

SDD14

SDD12SDD11

IDE_SDD10

IDE_SDD13

IDE_SDD8IDE_SDD9

IDE_SDD15

SDD13

SDD15

SDD10IDE_SDD11IDE_SDD12

SDD8

SDA0

IDE_SDIOR#

IDE_SDCS3#

SDDACK#IDE_SDDACK#

SDIOW#

IDE_SDA0

IDE_SDA2

SDIOR#

SDCS3#

IDE_SDIOW#

SDA2IDE_SDA1

SDCS1#IDE_SDCS1#

SDA1

PDD0

PDD5PDD4

PDD1

IDE_PDD6

PDD3

PDD6

IDE_PDD7

PDD7

PDD2

IDE_PDD[0..15]

IDE_SDD[0..15]

PDDREQ

IDE_IRQ14

IRQ15

SDDREQ

IDE_IRQ15

IDE_SDDREQ

IDE_PDDREQ

IRQ14

PIORDYIDE_PIORDY

IDE_SIORDY SIORDY

IDE_RST#

PCI_PAR

SD1

SD3

SD0

SD2

SA4SA5SA6SA7

SA8SA9SA10SA11

+3VS +3VS

+3VS

GND

+5VS

+5VS_CD

GND

+3VS

+5VS

+5VS

+5VS_HDD

+5VS

+5VS

+5VS

+5VS

GND

GND

GND

+5VS

GND

GND

C2734.7U

16V1206

12

MTG23

ID2.2/OD3.8

1

D19 PG1102W

A K

RP38

8.2K*8 1206

12345 6

78910

J19

MA/22PX2/STC16822-X44XX

13579

1113151719212325272931333537394143

2468101214161820222426283032343638404244

135791113151719212325272931333537394143

2468

101214161820222426283032343638404244

RP37

8.2K*8 1206

12345 6

78910

C6484.7U

16V1206

12

R743

4700603

1 2

R1405.6K0603

12

C6430.1U

50V0603

12

RP39

8.2K*8 1206

12345 6

78910

D18 PG1102W

A K

R734.7K0603

12

C2580.1U

50V0603

12

R205 821 2

R137

4700603

1 2

R207 821 2

R200

4700603

12

R20610K/NA0603

12

R1444.7K0603

12

R210 821 2

RP519

4.7K*8 1206

12345 6

78910

RP4333*4RPSOA_8C1

234

8765

RP514

4.7K*8 1206

12345 6

78910

RP530 4.7K*41206

1234

8765

R777 821 2

RP531 4.7K*41206

1234

8765

RP42

10*8RPX8

12345678 9

10111213141516

RP45

10*8 RPX8

12345678 9

10111213141516

R190

8.2K0603

1 2

JS4 SHORT-SMT31 2

C740.1U

50V0603

12

JS5

SHORT-SMT3

1 2

R44470/NA0603

12

RP44

10*8RPX8

12345678 9

10111213141516

RP532 4.7K*41206

1234

8765

R1315.6K0603

12

RP41

10*8RPX8

12345678 9

10111213141516

RP46 4.7K*41206

1234

8765

R711100K/NA0603

12

R730 10K/NA 0603

1 2

R202 10 06031 2

R6810K0603

12

R214

10K0603

1 2

R21510K0603

12

Q508DTC144WK/NA

1

2

3

R1 Q18DTC144TKA

2

13

RP52833*4RPSOA_8C1

234

8765

R1410

06031 2

R1 Q19DTC144TKA

2

13

R211 22 06031 2

R170 22 06031 2

R213 22 06031 2

R781 33 06031 2

R176 10 06031 2

R212 10 06031 2

R203 22 06031 2

R208 33 06031 2

R204 10 06031 2

R20910K0603

12

J12

FM/25PX2-R/AC12441-X50XX

13579

1113151719212325272931333537394143454749

2468101214161820222426283032343638404244464850

GND1GND2

135791113151719212325272931333537394143454749

2468

101214161820222426283032343638404244464850

GND1GND2

JS7

SHORT-SMT3

1 2

RP47 4.7K*41206

1234

8765

JS6 SHORT-SMT31 2

RP534 4.7K*41206

1234

8765

C2610.1U

50V0603

12

D13

EC10QS04/NA

AK

D512

EC10QS04/NA

AK

R15110K0603

12

-MCCS 21,22-IOR 21,22-IOW 21,22

CD_RST15

CDROM_COMM 20

PCI_LOCK#14

PCI_STOP#14,18,28,29

PCI_REQ1#14,29PCI_GNT4#14


PCI_FRAME#14,18,28,29

SA1521

SA1621

SA1421

SA1921

SA1321

SA1721

SA221,22

SA1221

SA321

SA121SA021

SA1821

-MEMR21

IRQ121,22IRQ1221,22

PCI_REQ3# 14

CLKRUN# 18,21,28,29

PCI_REQ0# 14,18PCI_INTD# 14,28PCI_REQ4# 14

-CDACTP22

-HDDACTP22

CDROM_LEFT 20CDROM_RIGHT 20

PCI_GNT1# 14,29

PCI_GNT3# 14PCI_GNT2# 14,28

PCI_GNT0# 14,18

PCI_TRDY# 14,18,28,29

PCI_SERR# 14,18,28,29PCI_IRDY# 14,18,28,29

-P_INIT 21,27

-P_STB 21,27

PCI_INTA#7,9,14PCI_INTC#14,28,29

PCI_INTB#14,18PCI_REQ2#14,28

PCI_PERR# 18,28,29

IDE_PDD[0..15]14

IDE_SDD[0..15]14

IDE_PIORDY14

IDE_IRQ1414

IDE_PDDREQ14

IDE_PDA014

IDE_PDIOR#14IDE_PDIOW#14

IDE_PDA114

IDE_PDDACK#14

IDE_PDA214IDE_PDCS3#14

IDE_PDCS1#14

IDE_IRQ1514

IDE_SIORDY14

IDE_SDA114

IDE_SDCS1#14

IDE_SDA014

IDE_SDIOW#14

IDE_SDCS3#14

IDE_SDIOR#14IDE_SDDACK#14

IDE_SDA214

IDE_SDDREQ14

-PCIRST7,9,14,18,21,28,29

PCI_PAR14,18,28,29

SD[0..7]21,22

SA621SA721

SA521SA421

SA1121SA1021SA921SA821

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Card Bus Socket

Close to TPS2211

Close to TPS2211

PC CARD PULL UPSIGNAL VOLT

CCD#1CCD#2CBLOCK#

+3V

CSTOP#CDEVSEL#CTRDY#CVS1CVS2CRST#CSERR#CPERR#CINT#CIRDY#CREQ#CSTSCHG#CAUDIO

+3V+3V

+3VCARD_VCCCARD_VCCCARD_VCCCARD_VCC

CARD_VCCCARD_VCCCARD_VCCCARD_VCCCARD_VCCCARD_VCCCARD_VCCCARD_VCC

PCI1410 HAVE INTEGRATED ALL PULL UP RES ABOVE

PCMCIA CONTROLLER & CARDBUS SCOKET

FOR TI 1410

AD20

PCI1410

REQ0#/GNT0#

PCI_INTB#

BD 311671700001 & TU 411671700011 01

8575A PCI1410 & 1394 PHY

18 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

-CGNT

CSTSCHG

-CREQ

CAD30

-CCBE3

-CRST

CAD28

CAD25

CAD3

CAD7

CAD2

CAD11

CAD6

-CIRDYCCLK

R2_A18-CBLOCK

CAD4

CAD15

CAD8

CAD18-CCBE2

CAD20

CAD31

CAD19

CPAR

-CSERR

CAD17

CAD14

R2_D2

CAD5

CAD0

CAUDIO

-CSTOP

CAD21

-CCBE1

CAD29CAD27

-CINT

CAD13

-CFRAME

CVS1

CAD22

R2_D14

CAD23

CAD16

CAD24

CAD26

CAD10

-CTRDY

CVS2

-CCBE0

-CDEVSEL

-CPERR

CAD1-CCD1

-CCD2

VPPEN1-VCCEN1 VPPEN0-VCCEN0

PCI_AD[0..31]

-CSTOP

CAD24

-CCBE1

PCI_AD0PCI_AD1

CAD21

CAD0

PCI_AD5

PCI_AD3

PCI_AD20

PCI_AD13

-CRST

PCI_TRDY#

-CBLOCK

-CFRAME

-CCD2

PCI_AD4

PCI_AD31

PCI_AD14

CAD12

R2_D2

CAD26

PCI_DEVSEL#

-CARDSPK

PCI_AD8

VPPEN1

CAD17

CSTSCHG

-CCD1

CAD29

CAD4

PCI_AD2

CAD13

CAD20

R2_A18

PCI_AD27

VPPEN0

-CGNT

CAD18

CAD16

PCI_AD6

-VCCEN0

PCI_AD16

PCI_AD24PCI_AD25

PCI_AD21

CVS1

CAD14

CLK_CARDPCI-CDEVSEL

CAD3

-CIRDY

-CPERR

PCI_AD10PCI_AD9

PCI_AD15

PCI_AD28

CVS2

CAD2

PCI_IRDY#

CAD30

CAD28

-PCIRST

CAD31

CAD5

CAD23

CAD6

PCI_C/BE#1

CAUDIO

PCI_AD19

PCI_AD26CAD27

CAD15

-CTRDY

PCI_SERR#PCI_PERR#

CCLK

PCI_AD22

PCI_AD29

CLKRUN#

PCI_C/BE#3

CPAR

PCI_AD17

-VCCEN1

PCI_STOP#

PCI_FRAME#

-CINT

CAD1

-CREQ

PCI_C/BE#2

PCI_PAR

PCI_REQ0#

CAD25

PCI_AD12PCI_AD11

R2_D14

CAD11

CARD_PME#

CAD8PCI_AD7

PCI_AD30

PCI_C/BE#0

-CCBE2

-CSERR

CAD22

PCI_AD18

PCI_AD23

CAD19

CAD7

-CCLKRUN

-CCBE0

CAD9

PCI_GNT0#

SERIRQ

CAD10

PCI_AD20

-CCBE3

CAD9

CAD12

-CCLKRUN

VCCA

+12VS

+5VS

+3VS+3VS

VPPA

VCCA

VPPA

VPPA

VCCA

+3VS

GND

+3VS

GND

+3VS

+3V

+3VS

VCCA

VCCA

GND

GND

+3VS

Q20DTC144WK

1

2

3

R216 0

0603

1 2

R217 0/NA

0603

1 2

C2030.1U

50V0603

12

C217

0.1U50V0603

1 2

R789 100 06031 2

R7840/NA0603

12

R78500603

12

R24910K 0603

1 2

R218

01 2

C20410P/NA060310%

12

R793 0

0603

1 2

R22110K0603

12

C6760.1U

50V0603

12

C6750.1U

50V0603

12

C6794.7U/NA

16V1206

12

C6500.1U

50V0603

12

C67810P/NA060310%

12

C6944.7U/NA

16V1206

12

C6870.1U

50V0603

12

C6610.1U

50V0603

12

C6620.1U

50V0603

12

R13447K0603

12

U505

TPS2211 SSOP16

12345678

161514131211109

VCCD0VCCD13.3VA3.3VB5VA5VBGNDOC

SHDNVDDP0VDDP1AVCCAAVCCBAVCCC

AVPP12V

C81270P060310%

12

C38270P060310%

12

J11

0.635/H5/68PCL640HIROSE

123456789

10111213141516171819202122232425262728293031323334

35363738394041424344454647484950515253545556575859606162636465666768

GND1GND2

GND3GND4

C6960.1U

50V0603

12

C6830.1U

50V0603

12

C6840.1U

50V0603

12

C6950.1U

50V0603

12

R222 0

0603

1 2

C21510P/NA060310%

12

R219 0

0603

1 2

C20510P/NA060310%

12

C8360.1U

50V0603

12

C8320.1U

50V0603

12

C1490.1U

50V0603

12

C8330.1U

50V0603

12

R220 0

0603

1 2

C21110P/NA060310%

12

R22310K0603

12

C8380.1U

50V0603

12

U6

PCI1410GGUBGA144_0.8MM

G1

K2 N4

L6 F3 M10

H11

D12

C8

B4 L9 N13

M13

N12

M12

G13A7

B2C3B3A3C4A6D7C7A8D8A9C9A10B10D10E12F10E13F13F11G10G11G12H12H10J11J12K13J10K10K12L13

B12B11A12A13B13C12D13C13A5B8C11D6D11D5B9A2J13E10C6D9L12A4B5C5

B7A11E11H13

C2C1D4D2D1E4E3E2F2F1G2G3H3H4J1J2N2M3N3K4M4K5L5

M5K6M6N6M7N7L7K7N8

E1J3N1N5

F4H1L1J4K1K3L2

M2L3

M1A1B1G4

L8L11M9

M11N11L10N10

K9N9K8

D3

H2

L4 M8

K11

F12

C10

B6

PCI_

VCC

0PC

I_VC

C1

PCI_

VCC

2PC

I_VC

C3

CO

RE_

VCC

0C

OR

E_VC

C1

CO

RE_

VCC

2C

OR

E_VC

C3

CO

RE_

VCC

4C

OR

E_VC

C5

AUX_

VCC

VCC

D0#

/VC

C5#

/SD

ATVC

CD

1#/V

CC

3#/S

CLK

VPPD

0/VP

P_PG

M/S

LAT

VPPD

1/VP

P_VC

C

SKT_VCC0SKT_VCC1

CAD31CAD30CAD29CAD28CAD27CAD26CAD25CAD24CAD23CAD22CAD21CAD20CAD19CAD18CAD17CAD16CAD15CAD14CAD13CAD12CAD11CAD10CAD9CAD8CAD7CAD6CAD5CAD4CAD3CAD2CAD1CAD0

CCLKCFRAME#

CIRDY#CTRDY#

CDEVSEL#CSTOP#

CPARCPERR#CSERR#

CREQ#CGNT#CINT#

CBLOCK#CCLKRUN#

CRST#R2_D2

R2_D14R2_A18

CVS1CVS2

CCD1#CCD2#

CAUDIOCSTSCHG

CC/BE3#CC/BE2#CC/BE1#CC/BE0#

AD31AD30AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20AD19AD18AD17AD16AD15AD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0

C/BE3#C/BE2#C/BE1#C/BE0#

IDSELPCI_CLKDEVSEL#FRAME#IRDY#TRDY#STOP#PARPERR#SERR#REQ#GNT#RST#

RI_OUT#/PME#SUSPEND#SPKR_OUT#

MF6MF5MF4MF3MF2MF1MF0

GN

D0

GN

D1

GN

D2

GN

D3

GN

D4

GN

D5

GN

D6

GN

D7

C8390.1U

50V0603

12

C1310.1U

50V0603

12

C8370.1U

50V0603

12


PCI_C/BE#314,28,29

-CARD_RI22

CARD_PME#15

PCI_C/BE#114,28,29PCI_C/BE#214,28,29

PCI_INTB#14,17

PCI_PAR14,17,28,29

-CARDSPK20

PCI_STOP#14,17,28,29

PCI_AD[0..31]14,28,29

SERIRQ15,21

PCI_SERR#14,17,28,29

PCI_FRAME#14,17,28,29

CLK_CARDPCI11

CLKRUN#17,21,28,29

PCI_REQ0#14,17

PCI_TRDY#14,17,28,29

PCI_C/BE#014,28,29

PCI_GNT0#14,17

PCI_IRDY#14,17,28,29

-PCIRST7,9,14,17,21,28,29

-PCIRST7,9,14,17,21,28,29

PCI_PERR#17,28,29

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RJ11

PIN 16

HIGH LOW

MDC SCREW HOLE

AUDIO CODEC ON DAUGHTER BOARDAUDIO CODEC ON MOTHER BD

MDC HARDWARE STRAP

CLOSE TO MDC

Mod

em D

ougt

her

Boar

dLayout Note:

㆓組㆗間須絕緣, EX: GND SHIELDINGS/W/W/S=12/6/6/12 mils

㆓組各自平行走線等長

as short as possible

GND_45

GND_45

RJ45

CLOSE TO MDCSHOULD BE 4.7PF

CLOSE TOICS1839

GND_45

PHY Address = 00001

LAN LED FOR DEBUG CONVENIENCE

1.51K

GND_45

BD 311671700001 & TU 411671700011 01

8575A LAN PHY (ICS1893) & MDC

19 30Monday, June 17, 2002

Custom

Title

Size DocumentNumber

Rev

Date: Sheet of

AC97_RST#

MODEM_SPK

MDC_GND1

MDC_GND2

MONO_OUT

AC97_SDOUTAC97_SYNC

AC97_BITCLK

MDC_SDIN

LAN_CT

RXIN+RXIN-

TXD-TXD+

RXIN-

TXD-TXD+

LAN_CT

RXIN+

PJ7

PJ4

PJRX+

PJ7PJRX+

PJRX+

PJRX-

PJTX-

PJTX+

PJ7

PJTX+

PJTX-

PJTX-

PJRX-

PJRX-

PJ4

PJ4

PJTX+

+5V

+3V

+3V

LAN_GND

+3V_LAN

GND_HOLE

+3V

LAN_GND

LAN_GND

LAN_GNDGND

LAN_GNDGND

LAN_GNDGND

LAN_GNDGND

LAN_GND

LAN_GND

GND_HOLE

LAN_GND

LAN_GND

LAN_GND

+3V_LAN

LAN_GND

LAN_GND

LAN_GND

LAN_GND

LAN_GND

+3V_LAN

GND

LAN_GND

+3V

GND

LAN_GND

LAN_GND

+3V_LAN

LAN_GND

+3V_LAN

+3V_LAN

R263

00603

1 2

C470.1U/NA

50V0603D

12

R561K0603D

12

C480.1U

50V0603D

12

C2101U0603

12

R72 22 0603D1 2

C7301U0603

12

D507

CL-190G/NA

AK

R5772K0603D

12

R70 1K 0603D1 2

R49

22K 0603

1 2

R581K0603D

12

C571U0603

12

JO6

12

R261

00603

1 2

S501Protector/NA

1808A

12

R5791.5K1%0603D

12

JO1

12

J5

ST/MA-2HIROSE

DF13-2P-1.25V

12

R57812.1k1%0603D

12

R120 4.7K

06031 2

C460.1U/NA

50V0603D

12

R2761.906031%

12

R3061.906031%

12

R67 22 0603D1 2

R40/NA 0805

1 2

C4110P060310%

12

JO509

SHORT-SMT3

1 2

JO508

SHORT-SMT3

1 2

F501

MINISMDC110

1 2

R260/NA

06031 2R28 0/NA 06031 2

L6

PLP3216SCHOKE_PLP3216S_1

14

23

R118 22 06031 2

R390/NA

06031 2

L4


14

23

R8411K0603D

12

JS502

SHORT-SMT4

1 2

R38 0/NA 06031 2

J9

8PX1/1.016MMCONN_PJS-AST_8

12345678

GND1GND2GND3GND4

12345678

GND1GND2GND3GND4

L1

50UH

CHOKE_WLT04020201

21

35

R119 22 06031 2

R465606031%

12

MTG24ID2.8/OD5.0

1

R415606031%

12

C5771000P

3KV1808

10%

12

J1

1.016MM/H8.6OCTEKCONNPJS-OXSXT

12

GND1GND2

12

GND1GND2

C540.1U

50V0603

12

U3

LF-H80PSOX16

768

10119

132

161415

45

1213

TD+TDCTD-

TX+TXCTX-

RD+RDCRD-

RX+RXCRX-

NC0NC1

NC2NC3

J18

FM/0.8MM/H2.4AMP C-179373

13579

11131517192123252729

24681012141618202224262830

R260

00603

1 2

MTG25ID2.8/OD5.0

1

R117 22 06031 2

C450.1U

50V0603D

12

R35750603

12

C440.1U

50V0603D

12

C37100P060310%

12

R537750603

12

C20910P/NA0603

12

R31750603

12

R538750603

12

R262

00603

1 2

L5

130Z/100M1608

1 2

C590.1U

50V0603D

12

C5011000P

3KV1808B

10%

12

JO55 12

R609 0 0603D1 2

C5021000P

3KV1808B

10%

12

L8

120Z/100M2012

1 2

JO5612

R66 0 0603D1 2

X1

25MHZTXC7X5274012500401

1324

C6527P

5%0603D

12

C6827P

5%0603D

12

RP410K*4RPSOA_8C

1234

8765

R651M/NA0603D

12

C3100.1U

50V0603

12

R595

10K0603D

12

C3110.1U

50V0603

12

R6110K0603D

12

R32 0 06031 2

JO2

12

R71 1K 0603D1 2

JO5

12

R431K0603D

12

JO4

12

C620.1U

50V0603D

12

JO3

12

R69 22 0603D1 2

R30/NA 0805

1 2

C640.1U

50V0603D

12

U20

PACDN006/NA SSOP8

1

2

3

4

8

7

6

5

RP5 22*4 1206

1234

8765

R1210_NA

06031 2

U5

ISC1893Y-10PQFP64_0.5MM

284501893001

333435

36

37

3839

40

41

4243

44

45464748

32

3130

2928

2726

25

24

23

22

21

2019

18

17

4950

51

5253

54

55

56 57 58

5960

61

62

63

64

1615

1413

1211

109

87

65

4

3

2

1

RXD2RXD1RXD0

RXDV

VDD

_IO

0

RXCLKRXER

VSS7

RXTRI

TXERTXCLK

TXEN

TXD0TXD1TXD2TXD3

RXD3

MDCMDIO

VSS6

VSS5

LOCKANSEL

VDD

4

DPXSEL

HW/SW

VSS4

LSTA

NCMII/SI

RESETN

VSS3

COLCRS

VDD

_IO

1

REF_OUTREF_IN

VDD

5 P0AC

VSS8

VSS9

VSS1

0

P1CLP2LI

VSS1

1

P3TD

VDD

6

P4RD

VDD

3VD

D2

TP_RXNTP_RXP

VSS2

VSS1

100TCSR10TCSR

VDD

1VD

D0

TP_TXNTP_TXP

VSS0

TP_CT

10/100SEL

NOD/REP

RP6 22*4 12061234

8765

R641.5K0603D

12

MODEM_SPK 20

AC97_RST#15,20

MONO_OUT20

AC97_BITCLK 15,20

MDC_SDIN 15AC97_SDOUT15,16,20AC97_SYNC 15,20

LAN_MTXD215

LAN_MRXD015

LAN_COL15LAN_DATAIO15

LAN_MTXD015

LAN_MRXD215

LAN_MRXER15

LAN_MTXD115

LAN_MRXD115

LAN_MRXDV15

LAN_MRXC15

LAN_MTXC15

LAN_DCLK15

LAN_MTXD315

LAN_MRXD315

LAN_CRS15

LAN_MTXE15

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AGND

AGND

AGND

Cap pin33: 1U X

Very Close to Codec

AGND

AGND

CHIP ALC200 CS4299

Cap pin32: 0.1U 0.01U

20mil

AGND

AGND

AGND

INTERNAL MICROPHONE

Close to ADP3301

CLOSE TO CODEC

Cap pin31: 0.1U X

AGND

Close to CodecClose to Codec

AGND

MIC

AGND

CAGND

AGND

AGND

AGND

AGND

AUDIO CODE & AMPLIFIER

External Micro Phone Jack

AGND

AGND

AGND

Cap p33/34 X 1000P

HI LOW

L

AGND

SPK_OFF

Very Close to TPA0202 Pin 18/7

R

AGND

Signal

AGND

AGND

AGNDCAGND

Internal Speaker Connector

Normal

Amplifier

Shut Down

AGND

AOUT_R/L Cap x2 - SIZE0805

AGND

AGND

AGND

AGND

Line Out Phone Jack

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

0Ohms?

AGND

AGND

AGND

AGND

AGND

01

8575A AUDIO CODEC & AUDIO AMP

20 30Monday, June 17, 2002

BD 311671700001 & TU 411671700011Custom

Title

Size DocumentNumber

Rev

Date: Sheet of

CDROM_LEFT

AC97_RST#

CDROM_COMM

MIC1

MIC2

MONO_OUT

AOUT_L

AOUT_R

AC97_SDIN

CDROM_RIGHT

AC97_SYNC

MODEM_SPK

AC97_BITCLK

AC97_SDOUT

AMP_MUTE

SPKLOUT--DECT_HP/OPT

-DEVICE_DECT

AC97_BITCLK

SPDIFOUT

SB_SPKR

MIC_VREF

MIC_VREF

-CARDSPK

LINE_OUT_2

LINE_OUT_5

VR1_2

SPDIFOUT

VR1_5

MIC_2MIC_3

MIC

SPKROUT+SPKROUT-

SPKLOUT+

AOUT_R

AOUT_L

-DEVICE_DECT

AMP_MUTE

-DECT_HP/OPT

-DEVICE_DECT

AVDDAD

+3VS

AVDDAD

5V_AMP

5V_AMP

AVDDAD

+5V

+12VS

AVDDAD

+5VS

+3VS_SPD

AVDDAD

AVDDAD

AVDDAD

+3VS+3VS_SPD5V_AMP

R727

2.2K0603

1 2

L530


14

23

R7264.7K

06031 2

R27100603

12

J25

ST/MA-2HIROSE

DF13-2P-1.25V

12

R185 6.8K 5%1 2

U513

AHCT1G86DBVSOT25

42

35

1

L35

36Z/100M2012

1 2

R13600603

12

R193100K0603

12

R719

20K 06031 2

C244

0.1U_NA 50V 06031 2

C269 1U 060310V1 2

R721

20K 06031 2

R191100K0603

12

R69810K0603

12

R703

10K 0603

1 2

C2540.1U

50V0603

12

C271 1U 060310V1 2

R192100K0603

12

R70010K0603

12

R731

10K0603

1 2

C219 0.1U 50V 06031 2

C2490.1U

50V0603

12

C224 0.1U 50V 06031 2

L28600Z/100M16081 2

R732

10K0603

1 2

C2361000P_NA

0603 50V 1 2

L526

600Z/100M/NA1608

1 2

U514

ADP3301AR-5/NASO8

1234 5

678OUT0

OUT1NRGND SD

ERRIN1IN0

R733

10K0603

1 2

R150

1M/NA0603

1 2

R155

0/NA 0603

1 2

C264 0.1U 50V 06031 2

R734

10K0603

1 2

C2381U0603 10V 1 2

L45600Z/100M1608 1 2

C286

4.7U0805 +80-20%12

C260 0.1U 50V 06031 2

L43600Z/100M1608 1 2

C880.1U

50V0603

12

C24610P/NA0603

12

C2010.1U

50V0603

12

C2874.7U0805 +80-20%

12

L39600Z/100M1608 1 2

R72010K 06031 2

C789100P0603

12

C7971U/NA0603

12

Q529DTA144WK

1

2

3

C22710P/NA0603

12

C796

0.01U/NA0603

1 2

+

C289 100U 6.3V EW6.31 2

R1Q528DTC144TKA

2

13

VR110K

1

2

3

4

5

67

C777

0.1U

50V0603

1 2

+

C280 100U 6.3V EW6.31 2

R738330K/NA 0603

1 2

+C245100U

16VEW6.3

12

C2840.1U

50V0603

12

R7392.7K0603

12

L44600Z/100M1608 1 2

L554120Z/100M2012

12

R15947K0603

12

C2470.1U

50V0603

12

JS505SHORT-SMT4

12

R74510K/NA0603

12

R1Q523

DTC144TKA

2

13

L535

600Z/100M1608

1 2

J21

ST/MA-2HIROSE

DF13-2P-1.25V

12C250 1000P 060350V1 2

C8011U0603

12

U15

ALC201PQFP48_0.5MM

192

3

12

24

23

20

18

17

16

15

14

13

37

39

41

34

1 9 25 38

4 7 26 42

21

22

35

36

31

32

33

1158

106

27

28

29

30

40434445464748

CD/GNDXTL/IN

XTL/OUT

PC_BEEP

LINE/IN/R

LINE/IN/L

CD/R

CD/L

VIDEO/R

VIDEO/L

AUX/R

AUX/L

PHONE

MONO_OUT

ALT_LINE_OUT_L

ALT_LINE_OUT_R

FLTO

DVD

D1

DVD

D2

AVD

D1

AVD

D2

DVS

S1D

VSS2

AVSS

1AV

SS2

MIC1

MIC2

LINE/OUT/L

LINE/OUT/R

BPCFG

FLT3D

FLTI

RESET#SDATA/OUTSDATA/INSYNCBIT/CLK

REFFLT

VREFOUT

AFLT1

AFLT2

NC1NC2NC3ID0#ID1#EAPDS/PDIF_OUT

R72210K 06031 2

C251 1000P 060350V1 2

C7900.1U_NA

50V0603

12

C262 1U 060310V1 2L.CH

R.CHJ28

RA/D3.6/5PHCHIDJ-B27-F6T

12345

C272 1U 060310V1 2

R728

2.7K0603

1 2

C225 1U 060310V1 2

C76510P/NA0603

12

C2421U0603 10V 1 2

L40

36Z/100M2012

1 2

L34

36Z/100M2012

1 2

R194

1K

0603

12

C771

0.1U50V0603

1 2

L534600Z/100M16081 2

L532600Z/100M

16080603D

12

X3

24.576MHZ/NA

1 2

L525

600Z/100M/NA16081 2

C278 0.1U/NA 50V 06031 2

L537600Z/100M16081 2

R139

00603

1 2

C11847P0603

12

C1200.1U

50V0603

12

D25BAV99/NA

1 23

C267 0.1U/NA 50V 06031 2

C803

2.2U0805+80-20%

1 2

C7882.2U0805+80-20%

12

R168

100K0603

1 2

C1170.1U

50V0603

12

C268 0.1U/NA 50V 06031 2

C804

2.2U0805+80-20%

1 2

JO32

12

U16

TPA0202_GND TSSOP24_TPA0102

2215

310

187

1121324

21723

2120

19

45

6

1416119

8

2526272829

3031323334

R OUT+R OUT-

L OUT+L OUT-

RVDDLVDD

GND0GND1GND2GND3

NC0NC1NC2

RLINE INRHP IN

R BYPASS

LLINE INLHP IN

L BYPASS

SE/BTL#HP/LINE#MUTE INMUTE OUT

SHUTDOWN

G1G2G3G4G5

G6G7G8G9G10

C1160.1U

50V0603

12

C263 0.1U/NA 50V 06031 2

R7091K0603

12

JO33

12

C25310U

10V1206

12

L527

600Z/100M/NA16081 2

C2851U0603

12

C806

2.2U0805+80-20%

1 2

C792

470P/NA 0603

10%1 2

JP501

JP

1 2

C791100P

0603

12

C2481U0603

12

C805

2.2U0805+80-20%

1 2

D521BAV99/NA

1 23

L529


14

23

D522

BAV99/NA

1 23

L531 600Z/100M 16080603D

1 2

L536

600Z/100M1608

12

C798220P060310%

12

JS3

SHORT-SMT4

1 2

C274 0.1U 50V 06031 2

R697

33K 0603

1 2

C2201000P/NA0603

12

R15422

06031 2

R704

10K/NA 0603

1 2

L533

600Z/100M/NA16081 2

R17300603

12

R69922

06031 2

LEDDriveIC

J24

2F1138-TJ1FOXCONN

54231

789

611

C270 1U 060310V1 2

L546

36Z/100M2012

1 2

R16500603

12

L27120Z/100M2012

12

R71310K0603

12

L553130Z/100M1608

12

C75910U_NA

10V1206

12

L545

36Z/100M2012

1 2

C2431U0603 10V 1 2

C793

470P/NA 0603

10%1 2

L547

36Z/100M2012

1 2

R714 22 06031 2

R174

1K

0603

12

R186 6.8K 5%1 2

R1Q10

DTC144TKA

2

13

C794

470P/NA 0603

10%1 2

C237

0.1U_NA 50V 06031 2

R964.7K0603

12

J23

ST/MA-2HIROSE

DF13-2P-1.25V

12

JO57

SPARKGAP_6

12

R187 6.8K 5%1 2

C795

470P/NA 0603

10%1 2

L552130Z/100M1608

12

R710 22 06031 2

C78410U

10V1206

12

MODEM_SPK 19

AC97_SDOUT15,16,19

CDROM_COMM 17

AC97_BITCLK15,19

CDROM_LEFT 17

AC97_SYNC15,19

AC97_SDIN15

MONO_OUT 19

AC97_RST#15,19

CDROM_RIGHT 17

14.318MHZ_AUDIO11

-CARDSPK18

SB_SPKR15,16

SPDIFOUT 15

SPK_OFF15

A

A

B

B

2 2

1 1

Flas

hR

OM

Close to EEPROM

TOUCH_PAD

Flash ROMSCRLUP

SCRLDOWN

RIGHT

LEFT

XCNF0

XCNF1

FUNCTIONALITY

1

1

LATCH MODE , XA12-19, XRDY DISABLE

BASE ADDRESS SELECT

X

XCNF0

10

4EH

1

NO BIOS

0

1

LATCH MODE , GPIO 10-17 ,XRDY DISABLE

XCNF1

0

1

LATCH MODE , GPIO 10-17 , XRDY ENABLE

OPEN

0

2FH

STRAP OPTION

XCNF2

0

INDEX REGISTER

1

0

1

NORMAL MODE , XRDY DISABLE

MOUNTED

1

4FH

X

R303

2EH

DATA REGISTER

0

LATCH MODE ,XA12-19, XRDY ENABLE

8575 T/P BRD

BD 311671700001 & TU 411671700011 01

8575A SUPER I/O, T/P & BUTTON

21 30Monday, June 17, 2002

Title

Size Document Number Rev

Date: Sheet of

SA14

SD0[0..7]

-ROMCS

-IOR

SA12

COM1RXD

SA13

SA0

SA3

FIRSEL

LPC_FRAME#

-COM1RTS

IRQ12

-MCCS

-COM1DTR

CLK_LPC33

-IOW

PIO/-PNF

-COM1DCD

-COM1CTS

-PCIRST

SA16

SA2

COM1TXD

LPC_DRQ#

SA1

-MEMR

SERIRQ

SA18

IRRX

CLK_SIO

-XSTB

IRTX

-MEMW

-COM1RI

SA15

-COM1DSR

SA5

SA9

SA7SA8

SA4

-XSTB

SA10

SA6

SA11

SA19

SD1SD0

LPC_AD3

SD6

LPC_AD0

SD7

SD4SD3

LPC_AD2

P_LPD[0..7]

SD5

SD0

P_LPD1

SD4

SD2SD1SD1

SD3

LPC_AD1

SD6

P_LPD3

SD2SD2SD2

P_LPD2

LPC_AD[0..3]

SD5

SD7

CLKRUN#

SA1

SD3

SA[0..17]

SD0

SA13

SD2

SA0

SD5

-ROMCSSA17

T_DATA

SD6

SA10

T_CLK

SA6

SA16

SD[0..7]

SA2

-MEMW

SA5

SA14

SD7

SA12

SD1

SA8

-MEMR

SA3

SA9

SA11

SA4SD4

SA15

SA7

TP_VCC

SCRL_DOWN

CLKDATA

SCRL_UP

LEFT

-MEMW

COM1TXD

IRQ1XCNF2

-P_INIT

-P_STB-P_AFD

-P_ACK-P_SLIN

-P_ERR

P_PEP_BUSY

P_SLCT

P_LPD6

P_LPD4

P_LPD0

P_LPD7

P_LPD5

KBD_US/JP#

-LPCPD

SA17

-COM1RI

COM1TXD

-COM1DSR

-COM1RTS

-COM1DCD

COM1RXD

-COM1DTR-COM1CTS

RIGHT

+3VS

+3VS

+3VS+3VS

+3VS +3VS+3VS

+5VS

TP_GND

TP_GND

TP_GND

TP_GND

+5V

+5VS

+3VS

GND

GND

+3VS

+3VS

TP_GNDTP_GND

TP_GND TP_GND

U511

PC87393

PQFP100_0.5MM

284587393002

15161718

89

121176

1019

20

2122232425262728293031323334

9594939291908786858483828180797877767574

5250484645444342

35363740414749515354

5556575859606162

7069686766

32110099989796

45737172

13 38 64 89

14 39 63 88

LAD0LAD1LAD2LAD3

LCLKLRESET#LFRAME#LDRQ#LPCPD#CLKRUN#/GPIO36SERIRQSMI#/GPIO35

CLKIN

DSKCHG#HDSEL#RDATA#WP#TRK0#WGATE#WDATA#SETP#DIR#DR0#MTR0#INDEX#DENSELDRATE0/IRSL2

XA0/GPIO20XA1/GPIO21XA2/GPIO22XA3/GPIO23XA4/GPIO24/XSTB0#XA5/XSTB1#/XCNF2XA6/GPIO26/PRIQA/XSTB2#XA7/GPIO27/PIRQBXA8/GPIO30/PIRQCXA9/GPIO31/MTR1#/PIRQDXA10/GPIO32/XIORD#/MDRXXA11/GPIO33/XIOWR#/MDTXXA12/GPIO10/JOYABTN1/RI2#XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2XA14/GPIO12/JOYAY/CTS2#XA15/GPIO13/JOYBY/SOUT2XA16/GPIO14/JOYBX/RTS2#XA17/GPIO15/JOYAX/SIN2XA18/GPIO16/JOYBBTN0/DSR2#XA19/DCD2#/JOYABTN0/GPIO17

PD0/INDEX#PD1/TRK0#

PD2/WP#PD3/RDATA#

PD4/DSKCHG#PD5/MSEN0

PD6/DRATE0PD7/MSEN1

PNF/XRDYSLCT/WGATE#

PE/WDATA#BUSY_WAIT#/MTR1#

ACK#/DR1#SLIN#_ASTRB#/STEP#

INIT#/DIR#ERR#/HDSEL#

AFD#_DSTRB#/DENSELSTB#_WRITE#

DCD1#DSR1#

SIN1RTS1#/TEST

SOUT1/XCNF0CTS1#

DTR1#_BOUT1/BADDRRI1#

IRTXIRRX1

IRRX2_IRSL0IRSL1

IRSL3/PWUREQ#

XD0/GPIO00/JOYABTN1XD1/GPIO01/JOYBBTN1

XD2/GPIO02/JOYAYXD3/GPIO03/JOYBYXD4/GPIO04/JOYBXXD5/GPIO05/JOYAX

XD6/GPIO06/JOYBBTN0XD7/GPIO07/JOYABTN0

XWR#/XCNF1XRD#/GPIO34/WDO#

XIOWR#/XCS1#/MTR1#/DRATE0XIORD#/GPIO37/IRSL2/DR1#XCS0#/DR1#/XDRY/GPIO25

VSS0

VSS1

VSS2

VSS3

VDD

0VD

D1

VDD

2VD

D3

C7290.1U

50V0603DA

12

MTG2ID2.2/OD5.5

1

R1280/NA 06031 2

MTG18ID2.2/OD5.5

1

D4

BAV99/NA

1

23

R1320 06031 2

MTG19ID2.2/OD5.5

1

MTG1ID2.2/OD5.5

1

TP515 1

D3

BAV99/NA

1

23

J20

MA/8P/STHIROSE

DF13B-8P-1.25V

12345678

L33 130Z/100M 16081 2J501

HDR/MA-8/NAACES

88206-0800

GND2GND1

12345678

J502

ST/MA-4/NAHIROSE

DF13-4P-1.25V

1234

R67710K0603

12

R9210K0603

12

C2210.1U

50V0603

12

SW2

12V/50MA/NASTS-042-A

12

34

5

SW3


12

34

5

D6

BAV99/NA

1

23

D1

BAV99/NA

1

23

L31 130Z/100M 16081 2

R15210K/NA0603

12

C2180.1U

50V0603

12

SW1


12

34

5

R74410K0603

12

F1

1.1A

1 2

J507

FPC/FFC-12P/1MM/NA

123456789

101112

123456789101112

SW503

HDS402SW_HDS402

12

43

U10

28F020-PLCC

12111098765272623254282932

2224

1

31

1314151718192021

32

16

30

A0A1A2A3A4A5A6A7A8A9

A10A11A12A13A14A15A16

CE#OE#

VPP

WE#

O0O1O2O3O4O5O6O7

VCC

VSS

A17

U8

74AHC373_V

TSSOP20

282574373004

3478

13141718

111

256912151619

2010

D0D1D2D3D4D5D6D7

OCG

Q0Q1Q2Q3Q4Q5Q6Q7

VCCGND

L29 130Z/100M 16081 2

C7260.1U

50V0603DA

12

C2160.1U

50V0603

12

C7350.1U

50V0603DA

12

R68110K0603

12

C22247P0603

12

C1150.1U

50V0603DA

12

SW4


12

34

5

R737100K0603

12

C22847P0603

12

R67510K0603

12

C7410.1U

50V0603DA

12

R245 4.7K0603

1 2

R14910K0603

12

LPC_AD[0..3]15

IRQ1217,22

-MEMR 17-MCCS 17,22

SD[0..7] 17,22

SA1217SA1317SA1417SA1517SA1617SA1717SA1817SA1917

SA4 17SA5 17

SA7 17SA8 17SA9 17SA10 17SA11 17

SA6 17

-ROMCS 22

P_LPD[0..7] 27

P_SLCT 27

P_BUSY 27-P_ACK 27-P_SLIN 27-P_INIT 17,27-P_ERR 27-P_AFD 27-P_STB 17,27

IRRX 27IRTX 27

FIRSEL 27SA017SA117SA217,22SA317

P_PE 27

SA[0..17] 17,22

SA18

SD[0..7]17,22

-ROMCS 22-MEMR 17

T_DATA22T_CLK22

-PCIRST7,9,14,17,18,28,29CLK_LPC3311

LPC_FRAME#15LPC_DRQ#15

SERIRQ15,18

CLK_SIO11

-IOR17,22-IOW17,22

IRQ117,22

CLKRUN#17,18,28,29

FAN_SPD0/1#22

KI0 22KI5 22

KO0 22KO1 22

A

A

B

B

2 2

1 1

Normal

FAN

HI

-LID

-FAN

Come From Battery

Close to NDS352P

Controller

Close to H8-3437F

Signal

GND_H8

HI

Signal LOW

FAN On

External Pull Up/Down

GND_H8

FAN Off

Micro

Suspend

CPU Fan Control

GND_H8

LOW

Inte

rnal

Key

boar

dC

onne

ctor

MICROCONTROLLER (H8)

Close to H8-3437F

EASY START BTN

Cover SwitchAGND

LOW

FAN Off

Small Fan Control

HISignal

-DC/DC_FAN FAN On

MODE3

H8 Mode Select Table

Description

1

1

MD1

Expended mode with On-Chip ROM disableMODE1

1

MD0 MODE

Expended mode with On-Chip ROM enable1

Single-Chip mode

MODE2

0

0

Close to NDS352P

SECOND POWER SWITCH

Leve

lSh

ift

Close to 74CBTD3384DBQ ResetSwitch

Quick Switch Button: Stuff RP589, R1359LED: Stuff RP590, R1360

NA WHILE ASSEMBLY

NA WHILE ASSEMBLY

DEFAULT SHORT

FAN

BD 311671700001 & TU 411671700011 01

8575A MICROCONTROLLER (H8)

22 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

-PWRSW

H8_MODE0

SCI#/FAN_SWITCH

KI4

IRQ12

BAT_T

KI7

BAT_DATA

KI1

-IOW_H8

KI0

H8_MODE0H8_MODE1

-H8_MCCS_H8

H8_SUSB

KI3KI2 KI5

KI6

-H8_RESET

BATT_DEAD

-IOR

-BATT_DEAD

SA2BLADJ

-H8_SMI

-POWERBTNH8_MODE1

-ADEN

H8_SUSC

SCI#/FAN_SPD

-H8_THRM

BAT_CLK

-H8_WAKE_UP

-H8_KBCS

IRQ1

-SUSC

LED_CLK

T_DATA

-NUM_KI2-CAP_KI3

-HDDACTP_KO1

T_CLK

-SCROLL_KI1

-PWRSW-CDACTP_KI4

CHARGE_I_CTR

-POWERBTN

KO14

KO8

KO2

KO10

KO3

KO7

KO9

KO0

KO6

KO12

KO1

KO15

KO4

KO13

KO5

KO11

KO0

KO2

KO4

KO6

KO8

KO10

KO12

KO14

KI0

KI2

KI4

KI6

KO1

KO3

KO5

KO7

KO9

KO11

KO13

KO15

KI1

KI3

KI5

KI7H8_PWRON

LED_DATA

D/VADJ2D/VADJ1CHARGING

-ADEN-LID

SW_+5VA

LEARNING

T_CLK_H8

-FAN0

KO1KO0

-THERM_ERR

-NUM

KI2KI3

KI1

KO1

KI3

-H8_STBY

D/VADJ_2_RP

SD[0..7]

KI4

KI2

SD0

SD3

SD5

KO0

BAT_DATA

CHARGING_RP

-FAN1

-H8_RESET

KI5

KI1

D/VADJ_1_RP

-POWERBTN

KI7

BAT_CLK

SD1

SD7

KI0

SD4

SD2

KI6

BAT_VOLT

SD6

-BATT_DEAD

BAT_TEMPBAT_V

-IOW_D -H8_MCCS_D

SIS_PWRBTN

BAT_CLK

-H8_WAKE_UP

-H8_THRM

-EXTSMI

-ROMCS-SB_THRM

-MCCS

-H8_SMI

BAT_CLKBAT_DATA

-H8_MCCS

-H8_KBCS

PWR_ONH8_PWRON

SCI#/FAN_SWITCH

SCI#/FAN_SPD

H8_ENABKL

ENABKL

H8_ENABKL

-LID

-FAN1

-FAN0

FAN0_SPD

FAN1_SPD

SIS_PWRBTN

SIS_PWRBTN#

S3AUXSW#

H8_SUSB

-SUSB

KI4

-SCROLL

-CAP

FAN1_SPD FAN0_SPD

FAN_SPD

-H8_RESET

-HDDACTP

-CDACTP

-SCROLL_KI1-NUM_KI2-CAP_KI3-HDDACTP_KO1

-CDACTP_KI4

-THRMTRIP

-WAKE_UP

T_DATA

H8_PWROK

KI5KI0

T_CLK_D

H8_MODE0

PORT91

H8_MODE1-H8_RESET

PORT90

-H8_MCCS-IOW

T_CLK

-H8_MCCS_D-IOW_D

T_CLK_D

-H8_MCCS_H8-IOW_H8

T_CLK_H8

PORT90PORT91

CHARGING 25

+5VA

+5VA +5VA

+5V

+5VA

H8_AVREF1

+5VS

+5VA

+5VA

+5VA

+2.5V_DDR

+VCC_CORE

+5VS

+3V

GND

GNDGND

+5VA

+5VS

+5VS

+5VS

+5VS

+5VA

+3V

+5VS +5VA

+5VA+5VA

GND

GND GND

+5V

GND

GND

+3V

+5V

+3V

+5V

+5VS

GND

GND

+5VAS

+3V

+3VS

+5VA

+VCC_CORE

JO2012

R74710K0603

12

R63410K0603

12

R7470K0603

12

C5221U_NA0603

12

C40.1U

50V0603

12

C7120.1U50V0603

12

RP511

4.7K*41206

1234

8765

D10

RLZ5.6BMLL34B

AK

JO1712

D5

RLZ5.6BMLL34B

AK

JO3012

C7160.1U

50V0603

12

JO1812

D12

BAT54/NA

1 3

C70768P06035%

12

Q6NDS352P

G

DS

JO1512

Q1NDS352P

G

DS

R1

Q512DTC144TKA

2

1 3

D502

BAV99/NA

1

23

R16

330603D

1 2

C723 00603

1 2

RP517

47K*8 1206

12345 6

78910

U510

LM26/NASOT25

1234

5 HYSTGND

VTEMPV+

OS

C251000P0603D

12

D504

BAV99/NA

1

23

JS2

SHORT-SMT3

1 2

RP515

0*41206

1234

8765

R64710K/NA0603

12

JO31

OPEN-SMT3

1 2

R718

1K0603

1 2

R691 01 2

L522

JP_BEAD_DFS0603B_DFS

1 2

L521

120Z/100M/NA1608

1 2

R672 2.2K 06031 2

D503

BAV99/NA

1

23

R6

10K0603

1 2

R671 22 06031 2

RP510 0*4 12061234

8765

R135 01 2

U11

SN74CBTD3384QSOP24A

3478

11

1417182122

1516192023

256910

113

2412

1A11A21A31A41A5

2A12A22A32A42A5

2B12B22B32B42B5

1B11B21B31B41B5

1OE#2OE#

VCCGND

R15

10K0603

1 2

RP509 0*4/NA 12061234

8765

R6431K0603

1 2

J26

MA/.1/GOLD/NA

1 235

4

76

9810

RP513

47K*8 1206

12345 6

78910

R68010K0603

12

C7280.1U

50V0603

12

R64210K0603

12

R683470K0603

12

D505

BAV99/NA

1

23

C7090.1U

50V0603

12

R12510K0603

12

D509

BAT54

1 3

R502

330603D

1 2

R13810K0603

12

JO1612

C71068P06035%

12

C7341U/NA0603

12

X503

16MHZTXC8X4.5

1 2

D7

BAV99/NA

1

23

R65210K0603

12

U509

H8/F3437 PQFP100_0.5MM

79787776757473726766656463626160828384858687888949505152535455561413122627282932333435

383940414243444593949596979899252423221918171665

4847

9190818069685857

31302120111087123

49 1537 364659 70 71 92

100

P10/A0P11/A1P12/A2P13/A3P14/A4P15/A5P16/A6P17/A7P20/A8P21/A9P22/A10P23/A11P24/A12P25/A13P26/A14P27/A15P30/HDB0/D0P31/HDB1/D1P32/HDB2/D2P33/HDB3/D3P34/HDB4/D4P35/HDB5/D5P36/HDB6/D6P37/HDB7/D7P40/TMCI0P41/TMO0P42/TMRI0P43/TMCI1/HIRQ1P44/TMO1/HIRQ1P45/TMRI1/HIRQ1P46/PW0P47/PW1P50/TXD0P51/RXD0P52/SCK0P60/KEYIN0/FTCIP61/KEYIN1/FTOAP62/KEYIN2/FTIAP63/KEYIN3/FTIBP64/KEYIN4/FTICP65/KEYIN5/FTIDP66/KEYIN6/IRQ6P67/KEYIN7/IRQ7

P70/AN0P71/AN1P72/AN2P73/AN3P74/AN4P75/AN5

P76/AN6/DA0P77/AN7/DA1

P80/HA0P81/GA20

P82/CS1P83/IOR

P84/IRQ2/TXD1/IP85/IRQ4/RXD1/CP86/IRQ5/SCK1/S

P90/IRQ2/ESC2P91/IRQ1/EIOW

P92/IRQ0P93/RDP94/WRP95/AS

P96/0P97/WAIT/SDA

MD0MD1

PA0/KEYIN8PA1/KEYIN9

PB0/XDB0PB1/XDB1PB2/XDB2PB3/XDB3PB4/XDB4PB5/XDB5PB6/XDB6PB7/XDB7

PA2/KEYIN10PA3/KEYIN11PA4/KEYIN12PA5/KEYIN13PA6/KEYIN14PA7/KEYIN15/STBY/FVPP

/NMI/RESXTAL

EXTAL

VCC

B

VCC

1

VSS4

AVC

C

AVR

EFAV

SS

VCC

2

VSS1

VSS2

VSS3

/RESO

D8

BAV99/NA

1

23

R67920K0603

12

R1Q514

DTC144TKA

2

13

R1Q520

DTC144TKA

2

13

R682

1K0603

1 2

JO1412

R659

1K/NA0603

1 2

D9

BAV99/NA

1

23

J6

HDR/SHR/MA/5PX2

SPEEDS100-0000-101

214368

5

1079

JO1112

DS

Q42N7002

G

DS

D511

BAV70LT1

1 23

JO1212

Q5DTC144WK

1

2

3

C7330.1U

50V0603

12

JO912

RP48 0*4 12061234

8765

J8

ST/MA-3HIROSE

DF13-3P-1.25V

123

SW501

MPU-101-80/NA

12

34

C732

10P06035%

12

C7360.1U

50V0603

12

JO1012

JO1312

JO712

R146 0 06031 2

U515

IMP811SOT143

1

2

4

3

GND

RESET

VCC

MN

R1Q533DTC144TKA

2

1 3

R1

Q11 DTC144TKA

2

13

R1260/NA0603

12

JO812

C7080.1U

50V0603

12

JO2912

R72510K0603

12

R663

00603

1 2

R1Q518

DTC144TKA

2

13

R6742.2K06031 2

D510

BAT54

13

JO2712

C7990.01U0603

12

R690 0 06031 2

JO2812

R666 10K0603

1 2

RP49 0*4/NA 12061234

8765

JO2512

R129 221 2

SW5

MPU-101-80/NA

12

34

RP51222*41206

1234

8765

R130 221 2

R654

10K0603

12

JO2612

JO2312

R684

33 0603

1 2

R1Q519

DTC144TKA

2

13

R5

33 0603

1 2

Q504DTC144TKA

B

E C

C7310.1U

50V0603

12

D515

ESD0805A/NA

AK

R724100K0603

12

C7142.2U16V1206 1

2

JO2412

R17100K0603

12

R51900603

12

C2140.1U

50V0603

12

C5051000P0603D

12

JO2112

J503

DF13-3P-1.25H

123

123

R1Q515DTC144TKA

2

13

R653 10K0603

1 2

SW502

12V/50MATC010-PSs11CET-B(T)SW_STS-042A

12

34

5

R66510K0603

12

R611 0 06031 2

R655

1M 0603

1 2

JO2212

R610 0/NA 06031 2

D S

Q32N7002

G

D S

JO1912

J13

FPC/FFC/1MM/24P85203-24-02ACES

123456789101112131415161718192021222324

C7370.1U

50V0603

12

U507

IMP811/NASOT143

1

2

4

3

GND

RESET

VCC

MN

R127

00603

1 2

-IOR 17,21

BAT_T 23

BLADJ 27

IRQ117,21

BATT_DEAD 25

BAT_V 23

IRQ1217,21

SD[0..7]17,21

LED_CLK10

SA2 17,21

-CARD_RI 18

CHARGE_I_CTR 25

LED_DATA10

-ADEN 23,27

SW_+5VA 27

T_DATA 21

LEARNING 27 D/VADJ1 25D/VADJ2 25

KO1 21KO0 21

-THERM_ERR4

-SCROLL10

-CAP10-NUM10

ENABKL9,27

-H8_RESET 10

I_LIMIT 27

-SB_THRM15

-SW_+5VA27

-ROMCS21

-EXTSMI15

-MCCS17,21

SCL_THRM4SDA_THRM4 BAT_D 23

BAT_C 23

PWR_ON 24,27

-SCI 15

-LID27

FAN_SPD0/1#21

SIS_PWRBTN#15

S3AUXSW#7,15

-SUSB

H8_SUSC 15-SUSC 15,24

-HDDACTP17

-CDACTP17

-THRMTRIP4

-WAKE_UP15

H8_PWROK 7

KI5 21KI0 21

T_CLK 21

-IOW 17,21

E

E

D

D

C

C

B

B

A

A

4 4

3 3

2 2

1 1

1.25V CM8500 & BATTERYCONNECTOR

Battary connector

BD 311671700001 & TU 411671700011 01

8575A Bat con, DDR 1.25V

C

23 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

DDR_IN

DDR_IN

BATT1

+5VAS

GNDGND

BATTGND

GND

GND

GND

GND

GND

VMAIN+5VA

+1.25V

GND

+3VS

+2.5V_DDR

GND

+5VA

GND

GND

GND

GND

GND

GND

PC260.1U080525V+80-20%1 2

PF502TR/SFT-10AFUSE_2917

1 2

G

D

S

PU513SI4835DYSO8

876

4

51 32

PR191K06031%

1 2

PC5780.01U50V10%0603D

12

DS

PQ5082N7002SOT23_FET

G

DS

PQ509

DTC144WKSOT23AN_1

1

2

3

PR55233K0603

12

PC5791000P

0603

12

PL506

120Z/100M2012

1 2

PR548100K/NA0603

12

G

D

S

PU512SI4835DYSO8

876

4

51 32

PC300.01U50V10%0603D

12

PR553100K0603

12

PR551226K0603B1%

1 2

PC220.1U080525V+80-20%

1 2

PC250.1U080525V+80-20%

1 2

R5391K0603

12

PC281000P060310%

1 2

PC5901000P060310%

12

+PC20220U72434V

12

PC5841000P0603

12

PC5820.1U0603D

12

PC2710U

10V1206

12

PC190.1U0603D

12

PD5

BAV99

1

23

PR564301K

1%0603D

12

J14

R/A-7P/2.5MMSUYIN250005MR07G100ZU

1234567

PD8

BAV99

1

23

PL8

3.3UH

1 2

PU10

CM8500TSSOP16_GND

9101112131415161

2345678

17AGND3VCCQ

VFBAGND4PGND2

VL2PVDD2

VCC2VCC1PVDD1VL1PGND1AGND1SDVIN/2AGND2

GND

PR563100K

1%0603D

12

PC5830.01U0805

12

PR1220K

1%0603D

12

PR114.99K

1%0603D

12

PC2410U

10V1206

12

PC5851000P060310%

12

PL504BEAD_120Z/100M_6A

0805D1 2

PC361000P060310%

12

PL505BEAD_120Z/100M_6A0805D

1 2

PC5871000P060310%

12

PR18200K06031%1 2

PC291000P060310%

12

PC230.1U080525V+80-20%

1 2

PD9RLZ3.6B/NAMLL34B

AK

PR175.10603

1 2PC210.1U

50V0603

12

PC5880.01U/NA50V10%0603D

12

BAT_V22

BAT_D22

BAT_T22

BAT_C22

BATT25

BATT25

ADINP25,27

-ADEN 22,27

E

E

D

D

C

C

B

B

A

A

4 4

3 3

2 2

1 1

BD 311671700001 & TU 411671700011 01

8575A +1.8V,+2.5V_DDR

C

24 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

BG1.8

SENSE4-

SENSE3-

INTVCC1

BST1.8

D/VMAIN_P1

BG2.5

FB2.5V

SENSE4+

1.8V_2

SENSE3+

FB1.8V

SENSE3-

TG1.8

SENSE3+

SW1.8

TG2.5

SW2.5

FB1.8V

2.5V_2

FCB

INTVCC1

INTVCC1

FCB

+1.8V_P

GND

GND

GND

GND

GND

+2.5V_P

GND

GND

VMAIN+2.5V_P +2.5V_DDR

+1.8V_P +1.8VS

GND

+5VA

+5V

+5V

+3VS

GND

GND

JS503

SHORT-SMT1

1 2

G

D

S

PU8SI4810DYSO8

876

4

52 31

PC5211000P0603

12

PR5700/NA0603

1 2

JO45

SHORT-SMT4

1 2

R1Q538DTC144TKA

2

13

PC5640.1U

50V0603

12

+ PC1210U25V

12

PC5500.1U

50V0603

12

PR523

0/NA0603

1 2

R878

0/NA0603

1 2

PC100.1U

50V0603

12

PC5491000P

25V0603

10%

12

PC558470P/NA50V0603

12

PR537

1K0603

1 2

+PC552150U73436.3V

12

PR539

1M0603

1 2

PR532 15K 0603 1%1 2

+PC547150U73436.3V

12

PC5450.1U

50V0603

12

PD510

BAS32L

AK

+PC524150U73436.3V

12

PC5551000P/NA0603

12

+PC531150U73436.3V

12

PC5620.022U

25V0603

10%

12

PR529

00603

1 2

PC5281000P

25V0603

10%

12

PC5611000P25V060310%

1 2

PC371000P

25V0603

10%

12

PD506BAS32L

AK

PC559 33P_NA0603

50V 1 2

+PC560150U73436.3V

12

PD1EC10QS04/NA

AKPC548

0.022U25V060310%

1 2

JO46

SHORT-SMT4

1 2

PC54610U

25V1210

20%

12

PR528 15K 0603 1%1 2

PR53011K0603 1%1 2

PC5570.1U

50V0603

12 PR525

.0125121%

1 2

PC5530.1U

50V0603

12

G

D

S

PU7SI4810DYSO8

876

4

52 31

PR52710K06031%

12

PL3

10UHD124C

1 2

PR52621.5K06031%

12

PR5150.01525121%

1 2

JO504

SHORT-SMT4

1 2

PL7

120Z/100M2012

1 2

PC5441000P25V060310%

12

PC565 33P_NA0603

50V1 2

PC54310U

16V1206

12

PC563 470P 50V 0603

1 2

PC55410U

16V1206

12

PC556470P50V0603

1 2

PC5221000P/NA0603

12

PR52400603

12

JO503

SHORT-SMT4

1 2

G

D

S

PU507SI4416DYSO8

876

4

52 31

PD2

EC10QS04

AK

DS


G

DS

G

D

S

PU509SI4416DYSO8

876

4

52 31

PL4

10UH

1 2

PR531

2.7K 0603

1 2

PR50812.7K06031%

12PC35

0.1U

50V0603

12

PD507

BAS32L

AK

+ PC1110U25V

12

PR538100K0603

12

PR50710K0603

1%

12

PC551 0.01U 0603

1 2

R877

10K0603

1 2

DS


G

DS

PU510

LTC3707QSOP28

123456789

1011121314

2827262524232221201918171615

RUN/SS1SENSE1+SENSE1-VOSENSE1FREQSETSTBYMDFCBITH1SGND3.3VOUTITH2VOSENSE2SENSE2-SENSE2+

PGOODTG1SW1

BOOST1VIN

BG1EXTVCCINTVCC

PGNDBG2

BOOST2SW2TG2

RUN/SS2

PWR_ON22,27PSON 10,15,27

-SUSC 15,22

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VADJ_1_P

01

0

1

0

NIMH_CELL

12.30V

0

0

0

0

12.60V

0

0

0

1

VADJ_2_P

0

1

0

12.50V

12.40V

BAT_TYPE

LI 9.68V

BD 311671700001 & TU 411671700011 01

8575A Charger

C

25 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

L6

REF

2IN+

L1 L4 L5

D/VADJ_2

D/VADJ_1

1.25V

LI_OVP

L2

2IN+

L3

LI_OVP

1.25V

GND

GND

GND

+5VAS

+5VAS GND

VMAIN

GND

GND

GND

GND

GND

GND

BATTGND

GND

GND

GND GND

+ PC15100U25V

12

PQ506DTA144WKSOT23AN_1

1

2

3

PR5451M0603

12

+ PC1410U25V

12

PR5614.7K0603

12

PR44.7K0603

12

PC130.01U

50V0603

10%1

2

+

- PU514B

LMV393MSSOP8

5

67

84

PC5661U

16V0805

12

PQ2ANDC7002N

2

3

4

PR130.0225121%

1 2

PC5720.1U25V060320%

1 2

PR556576K0603

12

PU9BSI4925DYSO8

3

4

65

+ PC18100U25V

12

PR54010K0603B1%

12

PD4EC31QS04DC2010

AK

G

DS

PQ1 SI4835DYSO8

876

4

51

32

PC5760.1U

50V0603

12

PR55813.7K06030.1%

12

PR546

2.49K06031%

12

+PC17100U25V

12

PC5690.1U

50V0603B

12

PC573150P0603

12

PQ2BNDC7002N

5

1

6

PU511

TL594CSO16

123456789

10111213141516 1IN+

1IN-FEEDBACK

DTCCTRT

GNDC1E1

E2C2VCCOUTPUTCTRLREF2IN-2IN+

PR144.7K0603

12

DS


G

DS

PC57710U

25V1210

12

C8980.1U

50V0603

12

PR720K06030.1%

12

PQ3MMBT2222A

B

EC

+

-

PU514ALMV393MSSOP8

3

21

84

PR560130K0603.1%

12

PR51M0603

12

PR557100K06031%

12

PR3100K0603D

12

PD3

EC31QS04DC2010

A K

PR547249K06031%

12

PR9487K06031%

12

PR5436.19K06031%

1 2

PR54210K0603B1%

12

PC5681000P0603B10%,X7R

12

PR562

100K0603

1 2

PQ510SCK431LCSK-.5

SOT23N

32

1

PC381000P060310%

12

JO506

OPEN-SMT2

12

PC5801U

25V0805

12

PC391000P060310%

12

PC5810.1U

50V0603

12

PL5

BEAD_120Z/100M0805D

1 2

PL6

33UHIND_CDR127_1

1 2

PR61M0603

12

PD511

RLZ20CMLL34B

AKPC567

0.01U

50V0603

10%

12

PC5710.01U_NA

50V0603

10%

1 2

DS

PQ42N7002

SOT23_FETG

DS

PR8976K06031%

12

PU9ASI4925DYSO8

1

2

78

PR1013.7K06030.1%

12

JS1

SHORT-SMT3

12

PC5750.01U50V

0603

10%1 2

PC570

0.1U50V0603B

1 2

PR54447K0603

12

PD7

BAS32LMLL34B

AK

PR1633K0603

12

PR5498.66K06031%

12

PC5740.1U_NA

50V0603B

12

PR559100K0603

12

PR15

100K0603B

12

JO507

OPEN-SMT2

12

PF501

FUSE_12061A-1206

1 2

PR541100K0603B

12

PC160.1U_NA

50V0603

12

PR5501M06031%

12

BATT 23

BATT_DEAD 22

CHARGE_I_CTR 22

ADINP3,27

CHARGING22

D/VADJ1 22

D/VADJ2 22

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU CORE

ForMobile

Northwood

Willamette

Mobile

DT/MOBO#MOBO/DT# W/N#

ON

OFF

OFF

OFFOFF ON

ON ON

OFF

BD 311671700001 & TU 411671700011 01

8575A CPU CORE

C

26 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

INTVCC_3

RUN/SS

VID0

FB-

MOBO/DT#

FB-

VID4

VID2

S2+

VID4

SGND1

DH1_CORE_1

+3V

INTVCC_3

MOBO/DT#

INTVCC_3

DH1_CORE_2

RUN/SS

FB-

VID2VID3

S2-

INTVCC_3 S1-

VID0_P

FB+

DL1_CORE

DH2_CORE_1

CORE_1

CORE_2

S1+

VID1

DH2_CORE_2

CORE_PG

RUN/SS

DL2_CORE

core_in

DT/MOBO#

DT/MOBO#

DT/MOBO#W/N#

VID3

VID0_P

VID1

W/N#DT/MOBO#

MOBO/DT#

+3V

GND

+5VA

GND

GND

GND

GND

GND

+5VA

GND

+VCC_CORE

GND

GND

GND

GND

+5V

GND

GND

GND

GND

+VCC_CORE

GND

GND

GND

GND

GND

GND

VMAIN

GND

GND

GND

+5VA

+5VS

PR32

00603

1 2

PR262M0603

12

PQ511MMBT3904L

B

EC

PC5300.1U

50V0603

12

PC53310U

10V1206

12

+ PC3410U/NA25V

12

PR352M0603

12

PC5120.1U

50V0603

12

PC5420.1U0603

12

+ PC3820U4V

12

+ PC3347U25V

12

DS

PQ52N7002/NA

G

DS

PR5820/NA0603

12

+PC592220U73432.5V

12

PR24

0_NA0603

1 2

PD505EC10QS04

AK

PR23750K06031%

12

PR6021M0603

12

PR342M0603

12

+ PC3247U25V

12

PC50410U

10V1206

12

PR310_NA 0603

1 2

PR521

100603

1 2

PC5321U

10V0805

12

PR58120K0603

1%1 2

PU1FDD6676SOT252B_FET

G

DS

PR2100603

12

DS

PQ72N7002

G

DS

DS

PQ5182N7002G

DS

DS

PQ5122N7002

G

DS

PC5050.1U

50V0603

12

PR585100K0603

12

PR5800_NA0603

1 2

+ PC5820U4V

12

PR330_NA 0603

1 2

PR20187K06031%

12

PL502120Z/100M2012

1 2

PC541

470P060310%

12

PC5260.1U

50V0603

12

PC5361000P

25V060310%1 2

DS

PQ62N7002

G

DS


G

DS

PC5160.1U0603

12

PC527

1000P25V060310%

1 2

JS501

SHORT-SMT1

1 2

PR57410K0603

12

+ PC3147U25V

12


G

DS

PR514

5.1 0603

1 2

PR5790_NA0603

12

PR57600603

12

+ PC7820U4V

12

PR300_NA 0603

1 2

PD502EC31QS04-TE12L

AK

PL1

1.25UH0.8X330%

1 2

R909 0_NA 06031 2

PR5770_NA0603

1 2

DS

PQ82N7002

G

DS

JO36

SHORT-SMT2

12

DS

PQ5132N7002

G

DS

PU516FDD6672ASOT252B_FET

G

DS

PR6011M0603

12

PC537

1000P25V060310%

1 2

PD515EC31QS04-TE12L

AK

PR52222K0603

1 2

PD504EC10QS04

AK

+PC6220U73432.5V

12

PR1100603

12

PC5290.1U

50V0603

12

PR571

0 0603

1 2

PC5071000P0603

12

PR51918.2K06031%

1 2

JO511SHORT-SMT2

12

PR21

20K0603

1%1 2

PD6BAS32LMLL34B

AK

DS


G

DS


G

DS

PL2

1.25UH0.8X330%

1 2

PD501EC31QS04-TE12L

AK

SW6

FHDS-04

1234

8765

PC596680P060310%

12

DS


G

DS

DS

PQ5192N7002

G

DS

PC50310U

10V1206

12

PC5060.1U

50V0603

12

PR22412K06031%

12

PD10BAS32L/NAMLL34B

AK

PC534 1000P0603 10%1 2

+ PC9820U4V

12

PU508

LTC3716SSOP36A

1

23

4

56

7

8

9

10

1112

1314

1516

1718

36

35

3433

32

31

30 29

28

27

2625

24

23

22

212019

RUN/SS

SENSE1+SENSE1-

EAIN

PLLFLTRPLLIN

FCB

ITH

SGN

D

VDIFFIUT

VOS-VOS+

SENSE2-SENSE2+

ATTENOUTATTENIN

VID0VID1

PGOOD

TG1

SW1BOOST1VI

N

BG1EXTV

CC

INTV

CC

PGN

D

BG2

BOOST2SW2

TG2

AMPMD

VBIAS

VID4VID3VID2 PU3

FDD6672ASOT252B_FET

G

DS

+PC8220U73432.5V

12

PR2926.7K06031%

12

PD516EC31QS04-TE12L

AK

PR59310K/NA0603

12

JO35SHORT-SMT2

12

PL501120Z/100M2012

1 2

PR250_NA 0603

1 2


G

DS

PC595

0.01U0603

1 2


G

DS

PC5170.1U

50V0603

12

PR504

.00525121%

1 2

DS

PQ92N7002

G

DS

PR5030.00325121%

1 2


G

DS

PR572

00603

1 2

PR513 10K

0603 1%

1 2

PR502

.00525121%

1 2

PR590

00603

1 2

PC5380.1U

50V0603

12

PD517

BAS32LMLL34B

AK PR511

2.2K0603

1%1 2

DS

PQ5142N7002

G

DS

DS

PQ5202N7002

G

DS

PR27100K 0603

1 2


G

DS

+PC591220U73432.5V

12

PC5250.022U25V

060310%

1 2

PR5732K0603

12

PR28100K0603

12

PR5010.00325121%

1 2

DS

PQ102N7002

G

DS

PC5130.1U

50V0603

12

JO34

SHORT-SMT2

12

PR575130K06031%

12

PR51843.2K06031%

12

VR_GATE15

CPU_CORE_EN5

DPRSLPVR15

VID0 4

VID24VID34

VID14

VID44

VSS_SENSE 4

VCC_SENSE4

H_PWRGD

VID0_P4

DT/MOBO#

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

+5VA +5VAS

BD 311671700001 & TU 411671700011 01

8575A TO D/D Connector & H8 power

C

27 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

P_BUSY

P_LPD5

DP_LPD7

P_LPD0

DP_LPD5

-P_ERR

-P_SLIN

P_LPD4

P_SLCT

-P_INIT

-P_AFD

P_LPD6

-P_STB

P_PE

P_LPD2

-P_ACK

P_LPD7

DP_BUSYDP_PE

DP_LPD1P_LPD1

P_LPD3

DVMAIN1

USBP_3+

DP_LPD4

-DP_SLIN

-DP_AFD

-DP_INIT-DP_ERR

DP_LPD6

-DP_ACK

-DP_STB

DP_LPD2

USBP_3-

USBP_5+

DP_LPD0

USBP_5-

DP_LPD3

DP_SLCT

USBP_0-

-BATT_LEDUSBP_3+

DP_LPD2

DP_LPD7USBP_0+

-DP_ERR

DP_LPD5-DP_ACK

DP_SLCT

BLADJ

-AC_POWER

DP_PEDP_LPD0

-BATT_RENPBLT

DP_LPD3

-DP_AFD

USBP_1-

FIRSELDP_BUSY

PWR_ONPSON

-DP_STB

IRRX

-DP_INIT

DP_LPD4

DP_LPD6

USBP_5-

DP_LPD1

USBP_1+

-DP_SLINUSBP_3-

USBP_5+

IRTX

LEARNING

-BATT_G

USBP_0+ USBP_1+

USBP_1-USBP_0-

+5VAS

+3V

+5VA+5VA

GND

+5V

GND

ALWAYS

GND

GND

H8_AVREF1

GND

GND

GND GND

+3V

+5VS

GND

VMAIN

+5V

GND GND GND

ALWAYS

+3VS

GND

GND

GND

GND

GND

+5VAS

+12VS

+5VA

D11

RLS4148

A K

D SG

Q509

SI2301DSG

D S

RP5040*41206

1234

8765

Q9DTC144WK

1

2

3

D508

RLZ5.6BMLL34B

AK

R621100K0603

12

D516

UDZ5.6BSOD323

AK

C50422P06035%

12

MTG27ID2.8/OD7.6

456

7 9

10

1238

1112

CP50522P*41206

1234

8765

CP50322P*41206

1234

8765

MTG26ID2.8/OD7.6

456

7 9

10

1238

1112

L555

PLP3216S/NACHOKE_PLP3216S_1

14

23

RP5010*41206

1234

8765

R88800603

12

DSG

Q511

SI2301DSG

DS

CP50622P*41206

1234

8765

R886 00603

12

J4

HDR/10PX2/H8.4

CENPH/PS-D-RA-44-X-X

13579

1113151719

2468101214161820

L558


14

23

CP50422P*41206

1234

8765

PC5020.1U

0603

12

R891 0 060312

RP5030*41206

1234

8765

PC210U

16V1210

12

PC110U

16V1210

12

R893 0 060312

PC40.1U

0603

12

PC5010.01U0805

12

L557


14

23

C6994.7U

16V1206

12

R890 0 060312R892 0 060312

F504

3216FF-1

1 2

J7

FM/22PX2/1.27B06P-0110-441

SPEED

135791113151719212325272931333537394143

2468

101214161820222426283032343638404244

454647484950

13579

1113151719212325272931333537394143

2468101214161820222426283032343638404244

454647484950

R61810K0603

12

U506

LP2951-02BMSO8

8273

6154

INSENSEF/BSHUTDN

5VTAPOUT

ERR-GND

C69810U

16V1206

12

DSG

Q8

SI2301DSG

DS

RP5050*41206

1234

8765

L556


14

23

R887 0 060312

R889 0 060312

R80100K0603

12

R501 00603 1 2

Q510DTC144WK

1

2

3

-ADEN 22,23

-SW_+5VA 22

SW_+5VA22

-P_ACK21

P_LPD421

P_LPD021

P_PE21P_BUSY21

-P_STB17,21

-P_ERR21

P_LPD521

-P_SLIN21

-P_AFD21

P_SLCT21

P_LPD121

P_LPD321

-P_INIT17,21

P_LPD621

P_LPD221

P_LPD721

ADINP23,25

USBP5- 16

USBP5+ 16

USBP3- 16

USBP3+ 16

BLADJ22

-BATT_LED 10

IRTX21

-LID 22

PSON10,15,24

ENABKL 9,22

TV_CRMA9TV_LUMA9

-AC_POWER 10

-BATT_G 10-BATT_R 10

FIRSEL21

IRRX21

USB_OC0_1#16

LEARNING 22USB_OC3_5#16 I_LIMIT 22

PWR_ON 22,24

USBP0+ 16

USBP0- 16

USBP1+16

USBP1-16

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AD21PCI_INTD#

MINI-PCI

REQ2#/GNT2#

PIN24, 124 ARE AUX_POWER

MINI-PCI

BD 311671700001 & TU 411671700011 01

8575A Mini PCI

C

28 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

MPCI_PD1

PCI_C/BE#1

AD21

AD18

AD26

MPCI_PME#

AD10

MPCI_PD1

PCI_STOP#

PCI_C/BE#0

PCI_FRAME#

AD9

PCI_SERR#

AD23

MPCIACT#

PCI_IRDY#

PCI_TRDY#

AD20

AD[0..31]

AD12

AD5

PCI_PAR

PCI_DEVSEL#

AD13

MINIPCI_INTC#

AD0

AD25

AD22

PCI_C/BE#3

AD14

MINIPCI_INTD#

AD11

AD27

AD4

AD7

PCI_C/BE#2

AD1

AD28

CLKRUN#

AD15

AD17

AD24

AD29

AD3

PCI_AD21

AD2

AD8

PCI_PERR#

AD19

AD16

AD30

AD6

AD31

GNDGND

+3V

+3VS

+3VS

+3VS

GND

+3VS

+5VS

+5VS

GND+3VS

+3VS

GND

R8740

06031 2

R885

00603

1 2

C8550.1U

50V0603

12

C8560.1U

50V0603

12

C8530.1U

50V0603

12

R802

1000603

1 2

C8460.1U

50V0603

12

R1

Q536DTC144TKA/NA

2

1 3

R87310K/NA0603

12

R8010/NA

06031 2R800

006031 2

C8520.1U

50V0603

12

R80310K0603

12 DS

Q534

SI2302DS

G

DS

C8510.1U

50V0603

12

JS511

SHORT-SMT4

1 2

J509

124P/0.8MM/H6SPEEDB27-101-0038

13579

111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799

101103105107109111113115117119121123

2468101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124

GND1GND2

TIPRX+RX-PJ7PJ8LED1_GRNPLED1_GRNNCHSGNDINTB#3.3V[0]RESERVED0GROUND0CLKGROUND1REQ#3.3V[1]AD[31]AD[29]GROUND2AD[27]AD[25]RESERVED1C/BE[3]#AD[23]GROUND3AD[21]AD[19]GROUND4AD[17]C/BE[2]#IRDY#3.3V[2]CLKRUN#SERR#GROUND5PERR#C/BE[1]#AD[14]GROUND6AD[12]AD[10]GROUND7AD[8]AD[7]3.3V[3]AD[5]RESERVED2AD[3]5V[0]AD[1]GROUND8AC_SYNCAC_SDATA_INAC_BIT_CLKAC_CODEC_ID1#MOD_AUDIO_MONAUDIO_GND0SYS_AUDIO_OUTSYS_AUDIO_OUT_GNDAUDIO_GND1RESERVED3VCC5VA

RINGTX+TX-PJ4PJ5

LED2_YELPLED2_YELN

RESERVED45V[1]

INTA#RESERVED5

3.3VAUX[0]RST#

3.3V[4]GNT#

GROUND9PME#

RESERVED6AD[30]3.3V[5]AD[28]AD[26]AD[24]IDSEL

GROUND10AD[22]AD[20]

PARAD[18]AD[16]

GROUND11FRAME#

TRDY#STOP#3.3V[6]

DEVSEL#GROUND12

AD[15]AD[13]AD[11]

GROUND13AD[9]

C/BE[0]#3.3V[7]

AD[6]AD[4]AD[2]AD[0]

RESERVED_WIP4[0]RESERVED_WIP4[1]

GROUND14M66EN

AC_SDATA_OUTAC_CODEC_ID0#

AC_RESET#RESERVED7GROUND15

SYS_AUDIO_INSYS_AUDIO_IN_GND

AUDIO_GND2MPCIACT#3.3VAUX[1]

GND1GND2

C8500.1U

50V0603

12

C84910U

10V1206

12

C8540.1U

50V0603

12

PCI_INTC#14,17,29

PCI_C/BE#214,18,29

PCI_C/BE#314,18,29

PCI_FRAME# 14,17,18,29

PCI_C/BE#0 14,18,29

MPCIACT# 15

PCI_GNT2# 14,17

-PCIRST 7,9,14,17,18,21,29

PCI_DEVSEL# 14,17,18,29

PCI_STOP# 14,17,18,29

PCI_REQ2#14,17

PCI_TRDY# 14,17,18,29

CLK_MINIPCI11

PCI_C/BE#114,18,29PCI_PERR#17,18,29

PCI_SERR#14,17,18,29CLKRUN#17,18,21,29

PCI_IRDY#14,17,18,29

MPCI_PD10,15

PCI_PAR 14,17,18,29

MPCI_PME# 15

PCI_AD[0..31]14,18,29

PCI_INTD# 14,17

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NEC UPD72872

REQ1#/GNT1#INTC#AD22

NOTE

P/N:274012457405

RI0 & RI1 connect an external resistorof 9.1K 0.5% to limit the LSI's current.

IEEE1394-uPD72872

uPD72872 uPD72873/74R227

NA

NA

0

NA

0

R811

NA

NA 0

0

R229

R811

R813

R230

R882

R883

R884

NA

NA

NA

0

0

0

BD 311671700001 & TU 411671700011 01

8575A IEEE 1394

C

29 30Monday, June 17, 2002

Title

Size DocumentNumber

Rev

Date: Sheet of

SCLK

SDATA

PORTDISPC1

CARDONPC0

PC2

PCI_AD24

PCI_AD19

PCI_AD17

PCI_AD15

PCI_AD8

PCI_AD6

TPA-

PCI_AD31

PCI_AD26

PORTDIS

PC1

TPB-

TPBIAS1

TPB-

PCI_AD21

PCI_AD5

CPS

PCI_AD30

TPB+

PCI_AD23

PCI_AD10

PCI_C/BE#2PCI_C/BE#1

PCI_AD28PCI_AD27

PCI_AD4

SDATA

PCI_AD16

PCI_AD12

PCI_AD7

1394_PME#

XI

XO

TPA-

PCI_AD29

CLKRUN#

XO

PCI_C/BE#3

TPA+

PCI_AD22

PCI_AD20

PCI_AD3

PCI_AD1PCI_AD0

PC2

TPA+

PCI_AD25

CPS

PCI_AD[0..31]

TPB+

PCI_AD18

PCI_AD11

XI

PC0

PCI_AD14

PCI_AD9

PCI_C/BE#0

SCLK

PCI_AD2

PCI_AD13

CARDON

TPA+

TPB+

TPBIAS1 TPA-

TPB-

+5VS

GND

+3VS

GND

GNDGND

GND

+3V

+PHYVDD

+3V

+PHYAVDD

GND

ALWAYS

GND

+3VS

+PHYVDD

GND

GND

GND

GND

+PHYVDD

+3VS

+PHYAVDD

GND

+PHYVDD

+PHYAVDD

+3VS+3VS

GND

1394_GND

R234 10K0603

1 2

R1980 0603

1 2

C8574.7U0805+80-20%

12

R1960 0603

1 2

C2930.1U50V

0603D

12

C2410.1U

50V0603D

12

R1950 0603

1 2

C2940.1U50V

0603D

12

JO510

12 JS506

SHORT-SMT4

1 2

C2590.1U50V

0603D

12

JO502

12

R225

1M 0603D

1 2

L41


14

23

JO501

12

C8614.7U0805+80-20%

12

L42


14

23

C2330.1U

50V0603D

12

L544

130Z/100M0603D

1 2

R1970 0603

1 2

C2390.1U

50V0603D

12

R272 00603 1 2

R862.7K0603

12

R232 10K 0603D1 2

JO505

12

C2520.1U

50V0603D

12

R872.7K0603

12

C3041U

0603D1 2

C2350.1U50V0603D

12

U18

UPD72872PQFP120_0.4MM

910121315161718232426272829323347484950525355565859626365666768

2348

3536373940414244

87

88

9192

567

22788193

85115114

7776

119118

7574

21344557

727170

9899100101

9697

102103104105

116117

1142531435164

1960

7379112

82869095110111

112030384654616980113120

83848994106107108109

AD31AD30AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20AD19AD18AD17AD16AD15AD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0

CLKRUNPMEINTAREQFRAMEIRDYTRDYDEVSELSTOPPERRSERRPAR

XI

XO

RI0RI1

PRSTPCLKGNTIDSELPORTDISP_RESETBCPS

ICNICL4ICL3ICL2ICL1

CARD_ONGROM_EN

ICH2ICH1

CBE3CBE2CBE1CBE0

PC2PC1PC0

TPB1NTPB1PTPA1NTPA1P

TPBIAS1TPBIAS0

TPB0NTPB0PTPA0NTPA0P

GROM_SDAGROM_SCL

LVDD0LVDD1LVDD2LVDD3LVDD4LVDD5LVDD6

PCI_VDD0PCI_VDD1

P_DVDD2P_DVDD3P_DVDD4

P_AVDD5P_AVDD6P_AVDD7P_AVDD8P_AVDD9

P_AVDD10

DGND0DGND1DGND2DGND3DGND4DGND5DGND6DGND7DGND8DGND9

DGND10

AGND0AGND1AGND2AGND3AGND4AGND5AGND6AGND7

R24356

0603D1 2

R24056

0603D1 2

R23856

0603D1 2

RP529

10K*4RPSOA_8C

1234

8765

D24ESD41A/NARPSOA_8_1

12

34

56

78

R2395.1K

1% 0603D1 2

C2920.1U50V

0603D

12

C2960.1U50V

0603D

12

C2950.1U50V

0603D1

2

C30022P0603D

12

C8630.1U

50V0603D

12

C302270P 060310%1 2

C8590.1U

50V0603D

12

C3030.01U

0603D1 2

C2750.1U50V

0603D

12

C2760.1U50V

0603D

12

C29922P0603D

12

C2310.1U

50V0603D

12

L543

130Z/100M0603D

1 2

R241 56 0603D1 2

R2372.7K/NA0603

12

R24200603

12

R80400603

12

C876 1U/NA 06031 2

C297 1U/NA 06031 2

R227 0 06031 2

R273 00603 1 2

C298 1U/NA 06031 2

R813 0 06031 2

C875 1U/NA 06031 2

R811 0/NA 06031 2

R231 1000603

1 2

R229 0/NA 06031 2

R2740 06031 2

U7

NM24C02NSO8

1

2

3

4

5

6

7

8

A0

A1

A2

GND

SDA

SCLK

WC-

VCC

R2240

0603

1 2

R226390K/NA0603

12

J27

IEEE1394/4PLINKTEKAVR20-4XXX0X

1234

GND1GND2

1234

GND1GND2

R230

100K0603

1 2

C930.1U

50V0603

12

R228 9.09K

0603

1%1 2

X6

24.576MHZ

1324

C3010.1U

50V0603

12

R23600603

12

TP5191

R2350/NA0603

12

R233 10K0603

1 2

TPB-TPB+TPA-TPA+

CLKRUN#17,18,21,28

PCI_INTC#14,17,28PCI_REQ1#14,17

PCI_FRAME#14,17,18,28PCI_IRDY#14,17,18,28PCI_TRDY#14,17,18,28

PCI_DEVSEL#14,17,18,28PCI_STOP#14,17,18,28PCI_PERR#17,18,28PCI_SERR#14,17,18,28

PCI_PAR14,17,18,28

-PCIRST7,9,14,17,18,21,28CLK_1394PCI11

PCI_GNT1#14,17PCI_AD2214,18,28

PCI_C/BE#[0..3]14,18,28

PCI_AD[0..31]14,18,28

1394_PME#15

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

8575 A MB R01

Page-15 R280,R281,D26 --->DELR0APVT

First GenerationR00

Page-22 R909 to +5VA/NA Reserve for Pull-upPage-15 R257 (VR HI/LO#)/100K--->Pull-down

R01MP

01

8575A M/B Revision

30 30Monday, June 17, 2002

C BD 311671700001 & TU 411671700011

Title

Size DocumentNumber

Rev

Date: Sheet of

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Reference Material

� Intel Pentium 4 Processor mPGA478 Socket

� SiS650 IGUI Host / Memory Controller

� SiS691 MuTIOL Media I/O Controller

� SiS301LV / Chrontel CH7019 TV/LVDS Encoder

� PCI1410GGU PCMCIA Controller

� uPD72872 IEEE1394 Controller

� 8575A Hardware Engineering Specification

Intel, INC

SiS, INC

SiS, INC

SiS, INC

TI, INC

NEC, INC

Technology Corp./MiTAC

SERVICE MANUAL FOR 8575ASERVICE MANUAL FOR SERVICE MANUAL FOR 8575A

Sponsoring Editor : Jesse Jan

Author : Sissel Diao

Assistant Editor : Janne Liu

Publisher : MiTAC International Corp.

Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C.

Tel : 886-3-5779250 Fax : 886-3-5781245

First Edition : Aug. 2002

E-mail : Willy.Chen @ mic.com.tw

Web : http: //www.mitac.com http: //www.mitacservice.com

mitac 8575a service manual

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