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Graduate Institute of Electronics Engineering, NTU

MIPS CPU Lab 3MIPS CPU Lab 3memory,register file & control unitmemory,register file & control unit

TA:王奕權

2004/5/7

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A simplified processorA simplified processor

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MemoryMemory

64 words length of each word:16 bit

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Memory:writeMemory:writeWriteEnable =1DataIn can be written into the memory synchronously with clk(posedge)The written location is specified by input address DataOut could be arbitrary number during write operation

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Memory:readMemory:readWriteEnable =0The memory behaves as a combinational logic block. read the data in the memory asynchronouslyThe location to be read is specified by input address.

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Memory:I/O pinMemory:I/O pin

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synchronous memorysynchronous memoryModify the above memory to make the read operation synchronously with clksynchronous memory for both read and write operationAlso, compare the simulation waveforms of (1) and (2).

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Register fileRegister file

length of each word : 16 bit32 registers in the register file. one 16 bit input bus: busW. Two 16 bit output buses: busA and busB.

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Register file:writeRegister file:writeWriteEnable =1The data on busW will be written into a register synchronously with clk(posedge). RW selects the register(one of 32 registers) to be written. BusA and busB could be arbitrary number during write operation.

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Register file:readRegister file:readWriteEnable =0The register file behaves as a combinational logic block. read the data in the register file asynchronouslyRA selects one of 32 registers. The content of that register will be output on busA. At the same time, RB selects one of 32 registers. The content of that register will be output on busB.

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Register file:I/O pinRegister file:I/O pin

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synchronous register filesynchronous register fileModify the above register file to make the read operation synchronously with clk as you have done in problem 1. Also, compare the simulation waveforms of (1) and (2).

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Single cycle architectureSingle cycle architecture

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MultiMulti--cycle architecturecycle architecture

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Control unitControl unitsingle-cycle:the control unit can be realized with combinational logic. multi-cycle: need a state machine to be our control unit. write a FSM control unit based on the text: Computer Organization & design, The hardware/Software interface, Chapter 5.

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MultiMulti--cycle architecture control cycle architecture control unitunit

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State transition diagramState transition diagram

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Notes(1/2)Notes(1/2)5 different operations in the diagram:

LW, SW, R-type, BEQ, J(jump). You can choose the binary numbers to represent the 5 opcodes by yourself. use “parameter” in Verilog to change binary numbers to ‘LW’, ‘SW’, ‘Rtype’, ‘BEQ’, ‘J’ in your verilog code.

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Notes(2/2)Notes(2/2)Follow the above graph to use binary number(0000~1001) to represent 10 states. use “parameter” to avoid using a binary number to represent a state in your verilogcode. write verilog code for the control unit and do simulations on each path on the state transition diagram (all 5 operations).

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State abbreviation tableState abbreviation table

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I/O pinI/O pin

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Submission list(due on 5/21)Submission list(due on 5/21)Hardcopy submission only: print out and submit to TA before deadlineTwo memory modules (read synchronous/asynchronous)verilog code and simulation waveforms to verify the two modules. Comment on differences of the two waveforms.Two register file modules (read synchronous/asynchronous)verilog code and simulation waveforms to verify the two modules. Comment on differences of the 2 waveforms.Control unit verilog code and simulation waveforms.

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ReferenceReferenceComputer Organization & design, the hardware/Software interface,Chapter 5course slides of prof. 郭斯彥