mipi ip modules for soc prototyping
DESCRIPTION
Arasan Chip Systems develops and marketing interface IP that meets MIPI standards. Digital IP can typically be emulated in FPGA, but mixed signal IP for physical interface cannot. Arasan provides MIPI D-PHY and MIPI M-PHY is module form for application processor / system on a chip developers to use with their emulation boards.TRANSCRIPT
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MIPI® PHY Modules for SoC Development, Validation and Compliance Testing
Surender SharmaSam W. Beal
Arasan Chip Systems
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Surender SharmaArasan Chip Systems
(408) [email protected]
Sam W. BealArasan Chip Systems
(408) [email protected]
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MIPI PHY Modules for SoC Development, Validation and
Compliance Testing
MIPI Interfaces are used in a wide range of mobile devices, from smartphones to tablets with new applications emerging beyond mobile. SoC designers typically use FPGA-based prototyping boards for design, debug, validation and compliance.
Low-power high-speed SLVS I/Os for camera, display and storage (CSI, DSI, UFS) are typically not supported by FPGA vendors. Arasan has developed PHY modules to support this need.
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Outline
D-PHY and M-PHY Overview
Hardware PrototypingUse CasesArasan UFS HVP System
Arasan PHY ModulesD-PHY Module, System ExampleM-PHY Module, System Example
Summary
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What is D-PHY?
D-PHY OverviewMIPI defined I/O for display (DSI) and camera (CSI)
High-speed (HS) Low Power (LP) ModesHS SLVS 200mV differential up to 1.5GbpsLP LVCMOS 1.2V single-ended low speedSeparate clock and data lanes (up to 4 data lanes)
Not supported in standard FPGAs
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D-PHY Functional Diagram
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What is M-PHY?
M-PHY Overview• MIPI defined I/O for high speed and very low power• Adopted by JEDEC for next generation mobile storage (UFS)• Adopted by PCI-SIG for mobile PCIe• Adopted by USB for USB 3 chip to chip (SSIC)
High-speed / Low Power / Low pin count• 1 or 2 lanes SerDes• HS 1.2Gbps – 5.9Gbps (Gear 1, 2, 3)• LS 10Kbps – 576Mbps (Gear 0-7)
Not supported in standard FPGAs
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M-PHY Module InterfaceReference MPHY Module Interface (RMMI)
Physical Media Interface
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Hardware Prototyping – Use Cases
HostBoard
PHYTarget
PHY
Early Software Development
SoC Validation
SoC Demonstration
Compliance Testing
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Arasan UFS HVP Example
Memory CPU FPGA
Host Platform
ConnectivityIP BoardMotherboard
UFS Device or Host
Software Stack and Drivers for Linux
UFS & UniPro
Host RTL IP
M-PHYDigital & Analog IP
Device Platform
FPGA
Connectivity IP Board
MemoryCPU
Motherboard
UFS Device or Host
Software Stack and Drivers for Linux
UFS & UniPro DeviceRTL IP
M-PHYDigital & Analog IP
Hardware Platform Enables Early Software Development & Device Testing
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D-PHY Module
D-PHYTest Chip
FMC Connector SMA Connectors
PHY Protocol Interface PPI Physical Media Interface
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D-PHY Module Example
DSI Configuration
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D-PHY Development – loopback test
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M-PHY Module
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M-PHY Module
The board consists of ACS MIPI M-PHY test chipPower supply regulatorMultiple test points and mode switchesHigh speed SMA for differential signalingSamtec FMC for board to board connection
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