minimizing response time implication dvs scheduling low ...€¦ ·...

Minimizing Response Time Implication in DVS Scheduling for LowPower Embedded Systems

Nasro Min-Allah1'2'3, Asad-Raza Kazmi2, Ishtiaq Al3, Xing Jian-Sheng', Wang Yong-Ji'

1Institute of Software, Chinese Academy of Sciences, Beijing 100080, Chinanasar.pathan@ gmail.com

2 Graduate University, Chinese Academy of Sciences, Beijing 100039, China3 COMSATS Institute of Information Technology, Islamabad 44000, Pakistan

Abstract

Recently, a lot of work has been done on minimiz-ing energy consumption of real time embedded systemsby exploiting hardware characteristics of latest processors.However; these techniques are effective to energy reductionat the expense of delayed responsiveness; a feature highlydiscouraged in real time embedded systems. As opposedto the previous works, we value response time of higherimportance than energy reduction after reliability, when atradeoff is involved. In this paper; we present a novel tech-niquefor scheduling mixed tasks on single dynamic voltagescaling enabled processor The proposed algorithm, pre-serves all timings constraints for hard periodic tasks underworst case execution time scenario, improves responsive-ness to periodic tasks and, saves as much energy as possi-ble for hybrid workload.

1. Introduction

Due to the efforts of scientists, engineers and mathe-maticians, the law of Gordon Moore- the number of tran-sistors on a microprocessor would double periodically [1]-is maintained for microprocessors . Unfortunately, on theother front, advances in battery technologies are not in pacewith microprocessor improvement, as battery capacity isonly tripled since 1990 [2, 3]. This gap is now addressedby applying energy efficient techniques at architecture, op-erating system, protocol and application levels, since en-ergy reduction has become a major design consideration forcomputing environments, ranging from wearable devices togird computing and server farms.

In [4], authors formulated a relation between powerconsumption, operating frequency and operating voltagefor CMOS circuitry, which provided a foundation for Dy-namic Voltage Scaling (DVS) in latest processors. It shows

that neglecting the leakage and short circuit power, powerconsumption becomes a linear function of frequency (f)and a quadratic function of the operating voltage (v) i.e.Pcmos v2f. This voltage/speed adjustment on the fly iscalled DVS; an effective means for power savings in cur-rent systems. Unlike typical processors running at maxi-mum speed throughout, latest processors support discretespeed levels (Table 1).

Today, many real-time embedded systems are capableof equally responding to randomly arriving events calledaperiodic tasks, along with periodic task. In such systemsa delayed response may result in performance degrada-tion ranging from degraded QoS to user's frustration andeven critical system failure. Although the focus of previ-ous studies [5, 6, 7, 8, 9, 10] is minimizing system energy,however energy saving is left behind by system responsive-ness on hand held devices running embedded applicationsin general and interactive application in particular. Apply-ing DVS to mixed tasks require a compromise between twoconflicting terms, namely, responsiveness and energy re-duction. In this paper, we propose a novel algorithm forhybrid task scheduling which is applicable to power effi-cient hand held devices running performance intensive ap-plications, where responsiveness is of higher importancethan energy reduction after reliability.

The rest of the paper is organized as follows. In Section2, we discuss related work and formulate our problem inSection 3. A novel technique for scheduling mixed work-load from DVS perspective is presented in Section 4. Ex-perimental results are given in Section 5. We conclude ourpaper in Section 6.

2. Related work

In their pioneer work, Weiser et al. [6] and a year laterChan et al. [7] proposed DVS algorithms for reducing en-ergy consumption of processor by dividing time slots into

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Table 1. DVS-enabled processors

Processor Speed (MHz) Voltage (V)StrongARM SA[16] 150 -600 0.75 -1.30PXA250[15] 100 -400 0.85 -1.3Cursoe(TM5400) [18, 21] 200 -700 1.10 -1.65ARM7D[19] 20 -33 3.3 -5.0PowerPC860[17] 25 -50 2.4 -3.3Itsy[21] 59 -206 1.0 -1.5Intel XScale [24] 150 -1000 0.75 -1.80

fixed-length intervals. Based on the CPU utilization in pre-vious intervals, their algorithms predict the CPU utilizationduring next interval in advance and adjust the system speedaccordingly. Unlike interval based strategies, more promis-ing task based strategies were proposed recently. Pillai andShin's work [5] provides real-time guarantees for real-timetasks. Yifan and Frank in [8] recently proposed a feedbackEDF scheduling for hard real time systems exploiting dy-namic workload characteristics, where actual and WCETexhibits a significant variation. Their greedy scheme splitshighest priority job into two subtasks. Only highest prior-ity job is scaled exploiting available slack while assumingall other task execute at full speed. Each task is dividedinto two subtasks i.e. the first subtask exploits availableslack and executes at lowest speed to reduce energy con-sumption while enough time is reserved for second subtaskto met deadline. As tasks do not fully utilize WCET, tasksare ideally expected to complete during first subtask. Thiscombination of feedback scheme and task splitting guaran-tees in deadline requirement of real time tasks while reduc-ing system energy consumption.

Majority of available literature [5, 12, 14] focusesmainly on reducing energy consumption and preserves tim-ing constraints for hard periodic tasks. However, unlike en-ergy efficient hard periodic tasks scheduling, applying DVSto hybrid/mixed task scheduling is very recently addressedin [11, 12], where focus is primarily on energy reduction.In contrast, we propose a novel algorithm for hybrid taskscheduling, applicable to power efficient hand held devicesrunning performance intensive applications, where respon-siveness is of higher importance than energy reduction afterreliability, whenever a tradeoff is involved between theseconflicting factors.

overheads. We schedule hybrid/mixed tasks (both peri-odic and aperiodic) according to EDF scheduling policy,where the task which has the earliest deadline among allready tasks has highest priority. Our target processor of-fers discrete speed levels in voltage-frequency (v,f) pairsand is controlled by operating system instructions, whereVI < v2 < ... < v, and fi < f2 < ... < fmax. Furthermorethe overhead of scheduling algorithm and voltage transi-tion is negligible when compared to the WCET of tasks.The power consumption of a processor under the speed fis given by g(f) and energy consumption during the inter-val [to,t1] is ft4' g(f(t))dt [12].

Hybrid schedule consists of

3.0.1. Periodic Tasks.

* A task set T ={T1, T2, ..., Tn } represents hard periodictasks simultaneously ready at t = 0, where every Ti ischaracterized by a pair of parameters (pi, ci), where piis time period and ci is WCET of the task.

* All tasks are independent and preemptable.

* The relative deadline Di of a task Ti is equal to pi.

* The periodically released instance Rij of Ti is calledj-th job of periodic task Ti. The release time of Rijinstance is pi x (j -1).

* The WCET of Ti is known in advance.

3.0.2. Aperiodic Tasks. Aperiodic jobs {Uk lk = 1,2,...}are modeled by a pair (r, e) of parameters, where r is re-lease time of job and not known in advance, e is aver-age WCET of ak, and is known only when job arrives att = rk. Considering r and e as mean inter-arrival and exe-cution times respectively, aperiodic load is represented byc = e/r. To evaluate our algorithm, we vary this load inour experiments up to the maximum limit.We deploy a dedicated server to handle aperiodic load

called Total Bandwidth Server (TBS) [22]. TBS is repre-sented in terms of capacity us = cs/ps, where cs is calledexecution budget and ps is period of the server. In this al-gorithm, the k -th aperiodic job ak, with execution time ekarrives at t = rk, is assigned deadline

dk = max(rk, dk-1) +3. System Model (1)

Throughout the paper, we assume a DVS-enabledprocessor running RTOS having negligible task switching

where ek is WCET of aperiodic task ak. The higher is u,the earlier is dk. Initial deadline do is always 0.

348

ek

us


4. Scheduling Mixed workload

4.1. TBS at Full Speed (No-DVS)

According to EDF scheduling test, a task set can be fea-sibly scheduled iff

n

Utot = cI-< 1 (2)i=l Pi

Where ut,t is called total system utilization. As we haveto accommodate aperiodic jobs along with period tasks, to-tal CPU utilization is portioned between up and us suchthat, the timing constraints of periodic tasks remain intactin presence of TBS iff

uP+US < 1

times are scaled by a factor of /Iai. Lowering frequencymeans lowering voltage and it is clear from Pcmo, = v2f thatlowering speed offers gain in power reduction at the ex-pense of performance (response time) degradation. Sinceenergy acquired by an application during time t is E = P.t.Consequently, energy consumption becomes E -c v2.

Since execution times of jobs are scaled when runningat lower frequency ai. The deadline assignment policy ofTBS becomes [12]

dk(aci) = max(rk,dk_ ) +ek

Hence, the deadline for TBS is delayed as

dk (ai) -dk = max(rk, dk-1) + a,us. 1

(3)

subject to 0 < up,u < 1 and 0 < up + us < 1, at fre-quency f = fm (f 1 in this case), where up is worst caseutilization of periodic tasks. We represent this approach byNo-DVS in rest of the paper.

4.2. Static Speed

Equation 3 gives the lowest possible system utilizationrunning at maximum speed. Assuming all task instancesrun for their WCET, the processor utilization is often farlower than 1.0 and results in idle intervals. Such inter-vals can be exploited to reduce energy consumption bystatically slowing down the processor and operating at alower voltage. System utilization can be increased and en-ergy consumption is reduced by lowering operating fre-quency. However, lowering frequency also means perfor-mance degradation of the system as the execution time of atask always takes longer at lowered speed than running atmaximum speed. Based on [5], the frequency componentcan be added to Equation 3 as

up+ us <fifm

where fi is the suitable speed for task set, so that no taskmisses the deadline and fi gives the maximum speed (0 <fiJfm < 1 ). This arrangement is done statically and wedenote this initial speed fi by f[atic, which is the minimumspeed to successfully execute hybrid task set. For the sakeof brevity, we denote fi/fm by ai , hereafter throughout inthis paper.

4.3. Deadline-based Frequency Scaling Algorithm(DFSA)

(5)

max(rk, dk- ) +ek

=ek( -1) (6)uS aci

As deadline is prolonged, aperiodic task's response timealso increases. In a large number of real-time applications,aperiodic jobs contribute very little to total workload suchas Java based videophone, which needs to run garbage col-lector(aperiodic job) almost every 600ms for 3.732ms [12].For systems, where aperiodic jobs rarely arrive as com-pared to periodic tasks and need quick responsiveness, onepossible solution to Equation 6 is running aperiodic jobsat maximum available speed, however this scheme is im-practical as energy-voltage curve is convex in nature [25],a small increase in voltage brings quadratic increment inpower consumption.

Equation 6 clearly means lowering scheduling priorityand delayed response time for response sensitive aperiodicjobs. Like periodic tasks, initially, we assume, as long asresponse time of aperiodic task is less than p, (worst case),frequency scaling is unnecessary. In order to avoid perfor-mance degradation of aperiodic jobs, we restrict this dead-line delay. As mentioned earlier, it is safely assumed thatTBS has to execute aperiodic jobs for ci intervals duringany interval of length p. Similarly, when applying DVSto our model, we provide a constraint that this delay mustbe less than or equal to p, i.e. dk(ai) -dk < ps. As wehave a range of speed levels (fi < f2 < ... < fi), suitablefrequency fk for aperiodic job akcan be obtained by

(7)

In case dk(ai) -dk < ps, our algorithm runs aperiodic loadwith ai = static.

5. Experimental Results and Analysis

Although, Equation 4 provides the lowest possible fre-quency to successfully schedule mixed tasks, execution

For our experiments we use the power energy model ofTransemmta's Cursoe processor as given in Table 2 [24].

349

ai = (I +Ps. us ) -Iek


Table 2. Characteristics of Cursoe processor

0.10.1

To apply Crusoe processor to our task model, we extrap-olate the last three rows of Table 3. To study energy con-

sumption and response times of aperiodic jobs are shownin the following. We varied aperiodic load from 0.1 to 0.8(maximum possible load).

5.1. Energy Savings

Figure 1 gives the energy consumption of aperiodictasks, when we apply No-DVS, Static-Speed and DFSA.The highest energy consumption is attributed to No-DVSbecause all tasks are executed at maximum speed. BothStatic-Speed and DFSA are normalized to No-DVS. Thestatic adjustment is directly linked to system utilization, thehigher is utilization the more is energy consumption. Thereason for this behavior is that it executes all tasks withsame frequency that is decided statically f[atic < fi, Both,No-DVS and Static-Speed consume a fixed amount of en-

ergy, which remains constant throughout the application,as their speed is not influenced by variation in aperiodicload. However, for DFSA, aperiodic load plays a crucialrole here; influences energy consumption greatly. Whenaperiodic utilization is increased, larger deadlines are as-

signed by TBS. This is the point where tradeoff has to bemade: either execute aperiodic job at lower speed with min-imum energy consumption and accept maximum response

time or, execute aperiodic job at maximum speed with max-imum energy consumption so that no performance lost are

observed. In such situation, we opt for system responsive-ness, while keeping energy consumption lowered, wherepossible. It can be seen that when aperiodic load is in-creased, the slope of DFSA becomes steeper because ape-

riodic tasks are executed with higher speed.

5.2. Performance Degradation

Figure 2 provides a comparison among average response

times of aperiodic jobs, running at maximum (f,), Static

0.2 0.3 0.4 0.5 0.6 0.7Aperiodic load

0.8

Figure 1. Energy consumption as a function of aperi-odic load for DFSA

(fstatic) and restricted speed (ai). Maximum speed (fm)gives shortest response time, while Static speed (fstatic) re-

sults in highest values; tasks are running at lowest possiblespeed such that timing constraints are preserved. DFSAhas restricted the response time delay (dk(ai) -dk < ps).We varied aperiodic load from to 0.1 to 0.8. Initially, re-

sponse times are the same for all techniques, as aperiodicutilization is low and the difference becomes clear whenhigher aperiodic load is applied. DFSA never exceeds sta-tic graph, whatever is the utilization. At higher aperiodicload, the response time of jobs with static technique ex-

perience quick raise; can not comply with higher aperi-odic demands. In contrast DFSA closely follow No-DVSapproach since dk(ai)- dk < ps. When aperiodic load ishigh, higher speed is assigned to aperiodic jobs by DFSAand thus its average response times become similar to No-DVS, since a1i = fm . Although No-DVS has better results,the energy consumption is very high, as shown in Figure 1.The performance loss with associated DVS schemes suchas static scheme is effectively overcome by DFSA, whichis the main contribution of this paper.

6. Conclusions and Future Work

Dynamic Voltage Scaling has been projected as a

promising technique for minimizing power consumption oflow powered devices. An inherit drawback associated withDVS is performance degradation.We have proposed a novel technique that minimizes

power consumption of latest real-time systems by avoidingperformance lost. The performance lost is bounded by re-

stricting aperiodic tasks deadlines. The scheme is evaluated

350

Frequency Voltage Power300 1.20 1.30400 1.23 1.80500 1.35 2.73600 1.53 4.21700 1.75 6.43800 2.00 9.60900 2.35 14.911000 2.80 23.52

0.9

(D 0.8N

E 0.70z: 0.60

E 0.5

o 0.4

a) 0.3

0.2

No-DVSStaticDFSA


0.9

0.8

No-DVSStaticDFSA

0.2 0.3 0.4 0.5Aperiodic load

0.6 0.7 0.8

Figure 2. Effectiveness of DFSA over Static approach

in light of maintaining pre-defined performance criteria, as-suming task's WCET and, varying aperiodic load. As a fu-ture work, we are indented to further reduce performancepenalty through slack stealing mechanism by consideringthe early completion of jobs.

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