minimizing energy in sub-threshold digital circuits · • s. gubbi and b. amrutur, “all digital...
TRANSCRIPT
Minimizing Energy Consumption in Sub-threshold Digital Circuits
Sagar G V
Indian Institute Of Science
Available Online: http://chips.ece.iisc.ernet.in/images/2/28/Emin.pdf
Overview
• Motivation
• Background
• Measuring Energy Consumption
• Time Based Digital Energy Sensing
• Error Estimation
• Results
• References
• Conclusion
Motivation
• “Agile duty cycled” systems have relaxed performance requirements, but stringent energy targets
• Ex: Body temperature logger
Motivation
• Computation duration is flexible
• Doesn’t matter if the circuit takes 1ms or 10ms or 100ms to complete before going back to sleep
Background
• E = Vdd * Idd * Ton
• High Vdd => Ton is small, but Idd is large
• At low Vdd => Ton is large, but Idd is small
• Optimize E = Vdd * Idd * Ton by adjusting Vdd
Background
• Minimum Energy Point (MEP) depends on the activity factor, process parameters, temperature etc.
• Can’t select optimal Vdd at design time
• Do it while the chip is running!
Background
• Hunt for the Minimum Energy Point
• Need to measure Eop at a given Vdd
Vdd Eop
1.0 volt 100 pJ
Background
• Hunt for the Minimum Energy Point
• Need to measure Eop at a given Vdd
Vdd Eop
1.0 volt 100 pJ
0.8 volt 50 pJ
Background
• Hunt for the Minimum Energy Point
• Need to measure Eop at a given Vdd
Vdd Eop
1.0 volt 100 pJ
0.8 volt 50 pJ
0.6 volt 25 pJ
Background
• Hunt for the Minimum Energy Point
• Need to measure Eop at a given Vdd
Vdd Eop
1.0 volt 100 pJ
0.8 volt 50 pJ
0.6 volt 25 pJ
0.4 volt 20 pJ
Background
• Hunt for the Minimum Energy Point
• Need to measure Eop at a given Vdd
Vdd Eop
1.0 volt 100 pJ
0.8 volt 50 pJ
0.6 volt 25 pJ
0.4 volt 20 pJ
0.2 volt 30 pJ
Background
• Hunt for the Minimum Energy Point
• Need to measure Eop at a given Vdd
Vdd Eop
1.0 volt 100 pJ
0.8 volt 50 pJ
0.6 volt 25 pJ
0.4 volt 20 pJ
0.2 volt 30 pJ
Measuring Energy Consumption
• Naïve method – Use lots of analog hardware
• Idd maybe in nA !
• Measurement hardware consumes more power than the digital circuit
Measuring Energy Consumption
• Shut off power to the circuit!
Proposed by Ramadass et.al “Minimum energy tracking loop with embedded DC–DC converter enabling ultra-low-voltage operation down to 250 mV in 65 nm CMOS,” JSSC 2008.
Measuring Energy Consumption
• Shut off power and wait for Nop operations to complete
• Measure Vdroop and compute Eop
Proposed by Ramadass et.al “Minimum energy tracking loop with embedded DC–DC converter enabling ultra-low-voltage operation down to 250 mV in 65 nm CMOS,” JSSC 2008.
Measuring Energy Consumption
• Issues:
– If Idd is low, Vdroop may be small => large error in digitizing it
– If Idd is large, Vdroop may cause functional failure
– Still need to digitize Vdroop
Proposed by Ramadass et.al “Minimum energy tracking loop with embedded DC–DC converter enabling ultra-low-voltage operation down to 250 mV in 65 nm CMOS,” JSSC 2008.
Time Based Digital Energy Sensing
• Don’t fix Nop. Instead, keep Vdroop fixed
• Count Nop, the number of cycles needed to reach the pre-set Vdroop
• No need to digitize the droop! Only need to know when the voltage droop just crossed Vdroop
Proposed by S. Gubbi and B. Amrutur, “All Digital Energy Sensing for Minimum Energy Tracking,” TVLSI 2014.
Time Based Digital Energy Sensing
Time Based Digital Energy Sensing
Time Based Digital Energy Sensing
• Limitations
– Only works in the sub-threshold region
– When Idd is small, Nop will be large => long time to measure Eop
Time Based Digital Energy Sensing
• Impact of Process Variations
Error Estimation
• Error due to approximation
– Less than 1% of Eop
• Error due to droop variation over Vdd
– Less than 5% of Eop
Results
• Test circuit
Results
References
• M. Alioto, “Ultra-low power VLSI circuit design demystified and explained: A tutorial,” TCAS-1, 2012
• B. H. Calhoun, A. Wang, and A. Chandrakasan, “Modeling and sizing for minimum energy operation in subthreshold circuits,” JSSC 2005
• Ramadass et.al “Minimum energy tracking loop with embedded DC–DC converter enabling ultra-low-voltage operation down to 250 mV in 65 nm CMOS,” JSSC 2008
• S. Gubbi and B. Amrutur, “All Digital Energy Sensing for Minimum Energy Tracking”, TVLSI 2014
• Ramezani et. Al ““Voltage sensing using an asynchronous charge-to-digital converter for energy-autonomous environments,” IEEE Transactions on Emerging Topics on Circuits and Systems, 2013
Conclusion
• Lowering the supply voltage does not always reduce energy consumption
• There is a sweet spot (Minimum Energy Point) for the supply voltage
• One can tune the supply voltage to lower energy
• Circuit Energy consumption can be measured using entirely digital circuitry