mini project- rom based sine wave generator

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The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes. The objectives of this module are to demonstrate, within an embedded development environment: • Processor – to – processor communication • Multiple processors to perform one computation task using parallel processing This project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team.

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  • 1. Mini Project ROM-Based Sine Wave GeneratorAuthor: University of Hertfordshire Date created: Date revised: 2009Abstract The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes.The objectives of this module are to demonstrate, within an embedded development environment: Processor to processor communication Multiple processors to perform one computation task using parallel processingThis project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using C, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team. Contents Mini Project ROM-Based Sine Wave Generator...............................................................................................1 Section 2. Project Day 1.......................................................................................................................................4 Section 3. Project Day 2.......................................................................................................................................5 Section 4. Preparation Session- Introduction to Altium Designer 6 ....................................................................8 Credits.................................................................................................................................................................19In addition to the resources found below there are supporting documents which should be used in combination with this resource. Please see: Mini Projects - Introductory presentation. Mini Projects - E-Log. Mini Projects - Staff & Student Guide. Mini Projects - Standard Grading Criteria. Mini Projects - Reflection.You will also need the Mini Project- ROM-Based Sine Wave Generator presentation. University of Hertfordshire 2009 This work is licensed under a Creative Commons Attribution 2.0 License.

2. Mini Projetc ROM-Based Sine Wave Generator Section 1. Project Specification 1. Learning Outcomes assessed (as taken from the DMD) All Learning Outcomes specified in the Definitive Module Documentation are assessed as part of this miniproject, the specific Learning Outcomes are: Knowledge and Understanding Successful students will typically: Identify and enhance knowledge gained from other studies in areas relevant to the project topic selected.Skills and Attributes Successful students will typically: Use relevant measurement instruments to analyse a defined electronic engineering problem relevant to digital systems or embedded computer systems. Synthesise a solution to a defined electronic engineering problem relevant to digital systems or embedded computer systems. Take, and analyse appropriately, test results from that solution. Carry out a simple critical evaluation of the results taken. 2. Project Title: ROM-Based Sine Wave Generator 3. Project Objectives: (technical, specific to this project) Demonstrate within the Altium Designer environment: An understanding of the principles of digital waveform generators the use of a hardware description language to implement a digital circuit the use of a test pattern to simulate a digital circuit4. Project Summary: (50 words max) Each student will be required to design and implement a ROM-based sine wave generator using a hybrid VHDL and schematic on Field Programmable Gate Array (FPGA). The design process will include the production of a test pattern to simulate the design before hardware implementation.5. Introductory Lecture (2hrs) Content: i.VHDL Design Stylesii.Basic principles of sequential circuit design using VHDL - Memories iii.Writing VHDL Testbenches iv. Development tools to be used6. Preparation Session (3hrs): i. Familiarisation with the Altium Designer environmentii. Writing a VHDL code for a sequential circuit iii. Writing a VHDL testbench for a sequential circuit7. Day 1 Expected Outcomes for the day: Students working individually must carry out a series of tasks to implement the sine wave generator. The tasks include the implementation and simulation of the generators basic component which is the ROM using a suitable VHDL design style. A briefing pack which contains instructions and sine wave samples will be provided at the start of the day.Assessment criteria; successful implementation using VHDL of a ROM that contains sine wave samples and justification of the VHDL design style used. Use of a test pattern to successfully simulate the designed ROM.Key Tasks: Implementation of a ROM that contains sine wave samples using VHDL Writing a VHDL test bench to simulate the ROM FB Version 1.0Page 2 of 19 3. Mini Projetc ROM-Based Sine Wave Generator8. Day 2Expected Outcomes for the day: Students are expected to use the ROM designed in day 1 to implement the sine wave generator on FPGA using a schematic document. The students are also expected to monitor and analyse the generators output using a Logic Analyzer soft device.Assessment criteria; successful implementation of a sine wave generator using schematic on FPGA and use of a Logic Analyzer soft device to monitor and analyse the output.Key Tasks: Creation of a sheet symbol from the VHDL file written in day 1 and use it in a new schematic document toimplement the sine wave generator Implementation of the generator on FPGA Use a Logic Analyzer soft device available from Altium Designers instruments library to monitor and analysethe generators output9. Facilitator guidance (key ideas to draw out from students): Day 1: Suitable VHDL design style to design sequential circuits Day 2: FPGA design flow and use of a Logic Analyzer soft device 10. Required Resources: Laboratory Facilities and Teaching Support.Laboratory Resources: LD4031. PC Workstations with Altium Designer 6 (AD6), DXP simulator and Xilinx ISE.2. NanoBoard-NB1 FPGA board. Teaching Resources:1. Preparatory Session; LD403: structured workshop based on an AD6 sequential design.2. Day 1: briefing pack containing instructions for the day.3. Day 2: briefing pack containing instructions for the day. FB Version 1.0Page 3 of 19 4. Mini Projetc ROM-Based Sine Wave GeneratorSection 2. Project Day 1 Tasks for the day1. Use VHDL to describe the ROM shown in Figure 1 that contains the following 128 samples of a sinewave "10000000" "11111111" "10000000""00000000" "10000110""11111111" "01111001" "00000000" "10001100""11111111" "01110011" "00000000" "10010010""11111110" "01101101" "00000001" "10011000""11111101" "01100111" "00000010" "10011111""11111100" "01100000" "00000011" "10100101""11111010" "01011010" "00000101" "10101011""11111000" "01010100" "00000111" "10110000""11110110" "01001111" "00001001" "10110110""11110011" "01001001" "00001100" "10111100""11110000" "01000011" "00001111" "11000001""11101101" "00111110" "00010010" "11000111""11101010" "00111000" "00010101" "11001100""11100110" "00110011" "00011001" "11010001""11100010" "00101110" "00011101" "11010101""11011110" "00101010" "00100001" "11011010""11011010" "00100101" "00100101" "11011110""11010101" "00100001" "00101010" "11100010""11010001" "00011101" "00101110" "11100110""11001100" "00011001" "00110011" "11101010""11000111" "00010101" "00111000" "11101101""11000001" "00010010" "00111110" "11110000""10111100" "00001111" "01000011" "11110011""10110110" "00001100" "01001001" "11110110""10110000" "00001001" "01001111" "11111000""10101011" "00000111" "01010100" "11111010""10100101" "00000101" "01011010" "11111100""10011111" "00000011" "01100000" "11111101""10011000" "00000010" "01100111" "11111110""10010010" "00000001" "01101101" "11111111""10001100" "00000000" "01110011" "11111111""10000110" "00000000" "01111001"ADDR8x128 ROMDATARE CECLK Figure 1. 8x128 ROM2. Produce a test pattern and simulate your design using the DXP simulator.3. Use VHDL to describe a counter that can be used to generate the ROMs addresses4. Produce a test pattern and simulate your counter using the DXP simulator. FB Version 1.0Page 4 of 19 5. Mini Projetc ROM-Based Sine Wave GeneratorSection 3. Project Day 2Tasks for the day 1. Finish all tasks from Day 1. 2. Using the same FPGA project from Day 1, create sheet symbols from the ROM and counter VHDL files and place them in a new schematic document. 3. Place the following components (listed below in Table 1) on the schematic sheet. Table 1. Components to be used in schematic Component nameAvailable from FPGA integrated library LAX_1K8 (Logic Analyzer)FPGA Instruments.IntLib CLOCK_BOARD FPGA NB1 Port-Plugin.IntLib CDIV4 FPGA Generic.IntLib NEXUS_JTAG_CONNECTORFPGA NB1 Port-Plugin.IntLib NEXUS_JTAG_PORT FPGA Generic.IntLib4. Wire the NEXUS_JTAG_CONNECTOR and NEXUS_JTAG_CONNECTOR as shown in Figure 1.P8JTAG_NEXUS_TDI TDIJTAG JTAGP11 JTAG_NEXUS_TDOTDOJTAG P9 JTAG_NEXUS_TCKTCKJTAGP10 JTAG_NEXUS_TMSTMS . JTAG.. JTAGVCC TRST Figure 1.5. Connect the ROM and the counter (Leave the clock and the memory data pins unconnected). Verifying the design using a logic analyzer The LAX_x family of devices provide a range of 8- or 16-channel Logic Analyzer instruments for use in an FPGA design. They provide a simple method of analyzing the logical levels of signals. In this mini-project, the Logic Analyzer device to be used is the LAX_1K8. This device has 1Kx8 storage memory built-in. All 8 input channels are to be used to monitor the corresponding outputs of the 8-bit ROM. The capture clock signal, CLK_CAP, is derived from the external system clock (CLOCK_BOARD). A divide-by-4 clock divider is to be used. This makes the CLK_CAP, the ROMs clock a

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