migrating to powerpc 440gx from 440gp: hardware...

Revision 1.01 Application Note (Proprietary) AN2006

440GX Application NoteMigrating to PowerPC 440GX from 440GP: Hardware Considerations

January 18, 2008

AbstractThe AMCC PowerPC® 440GX processor contains several new features that significantly improve its performanceover the 440GP processor:

• Increased static random access memory (SRAM)• An expanded Ethernet controller interface• A transmission control protocol and internet protocol (TCP/IP) assist hardware unit• An extended peripheral component interconnect (PCI-X) messaging unit.

This application note highlights the hardware features of the PowerPC 440GX processor. It also describes thehardware changes between the 440GX and 440GP processors. Refer to the PPC440GX Embedded ProcessorUser’s Manual, listed in Related Documents on page 19, for detailed information.

OverviewThe 440GX processor offers 440GP customers the advantage of enhanced performance in speed and communi-cation, as outlined in Table 1. No circuit-board modifications are required to accommodate the 440GX packagesize, which is the same as the 440GP package size. All the 440GX signal locations are the same as the 440GP sig-nal locations. Therefore, the 440GX processor should support existing board layouts with minor modifications.Although the 440GX processor is package-compatible with the 440GP processor, there are some additional sig-nals in the 440GX processor. These additional signals account for most of the hardware differences between the440GX and 440GP processors; thus, they are the focal point of this note. From a software perspective, porting an application from the 440GP processor to the 440GX processor involvesnew register settings for parity, machine check handling, and clock configuration strapping. Another software con-sideration is a new value for the processor version register (PVR) register. For information on softwaremodifications, see the Software Considerations When Migrating to the PowerPC 440GX Processor from the440GP Processor application note, listed in Related Documents on page 19.

Table 1: Comparison of 440GP Processor to 440GX Processor

Features 440GP Processor 440GX Processor

Technology 0.18 μm 0.13 μm

CPU Speed 400 to 500 MHz 500 to 667 MHz

Double Data Rate (DDR) Clock Speed Maximum: 133 MHz (DDR266) Maximum: 166 MHz (DDR333)

SRAM On-chip: 8 KB On-chip: 256 KB

I/O Voltage 3.3 V Ethernet/DMA/Trace2.5 V Memory

3.3 V2.5 V Memory/Ethernet/DMA/Trace

Core Voltage 1.8 V 1.5 V

Typical Power Less than 4.0 W @ 400 MHz Estimate: 4.5 W @ 500 MHz

Ethernet Two 10/100 Mbps interfaces Two 10/100/1000 Mbps interfacesTwo 10/100 Mbps interfaces

External Interrupts 13 programmable interrupts 18 programmable interrupts

Package 25 x 25 mm, 552-ball ceramic ball grid array (CBGA)

25 x 25 mm, 552-ball CBGA

2 Application Note (Proprietary) Revision 1.01

440GX Application Note

Hardware DifferencesA primary hardware difference between the 440GP and 440GX processors is the voltage levels of some I/O sig-nals. In particular, the voltage levels of the Ethernet, direct memory access (DMA), and some trace and generalpurpose input/output (GPIO) signals have changed. To support up to four Ethernet ports, there is signal multiplex-ing on the following:

• Ethernet pins• Trace and GPIO signals• Some external bus master interface (EBMI) signals• The two reserved pins on the 440GP processor

By multiplexing these signals, the designers were able to maintain the same pin count as on the 440GP processor. Another major change is the implementation of the new Ethernet controller, which increases the number of 10/100Ethernet interfaces from two to four. Two of these Ethernet channels are capable of 1 Gbps, and support jumboframes and TCP/IP assist. In addition, the on-chip SRAM increases from 8 KB in the 440GP processor to 256 KB in the 440GX processor.

TCP/IP Assist Hardware UnitThe 440GX processor has two new Ethernet interfaces that support 1 Gbps. Each has a TCP/IP assist hardware(TAH) unit that provides improved bandwidth and lower CPU utilization. For more information on the TAH, Refer tothe PPC440GX Embedded Processor User’s Manual, listed in Related Documents on page 19.

Clocking ChangesLike the 440GP processor, the 440GX processor generates its internal clocks from the system clock using an inter-nal phase locked loop. There is a new scheme for implementing the clocking configuration that differs from theimplementation in the 440GP processor. Figure 1 on page 3 illustrates this structure; Table 2 on page 3 lists thenew registers used to implement the various clocking configurations. In the 440GP processor, there is a series of individually addressable device-configuration registers (DCRs) that arecalled CPC0_xxx. The 440GX processor splits these DCRs into two groups of registers, the clocking and power-onreset registers (CPRs), and the system DCR registers (SDRs). In the 440GP processor, different bit fields residedin the same configuration register. The new scheme implemented in the 440GX processor allows more logical par-titioning (see the Software Considerations When Migrating to the PowerPC 440GX Processor from the 440GPProcessor application note for more information about register settings). The firmware that is ported from the440GP processor to the 440GX processor still needs to be changed. However, the use of these common registersand bit and field definitions provides a simpler migration path for future generations of firmware. The system clock provided to the 440GX processor has a higher maximum frequency than the 440GP processor.The maximum frequency has increased from 66.66 MHz for the 440GP processor to 83.33 MHz for the 440GX pro-cessor. Both parts have a minimum frequency of 33.33 MHz. From a system-clock hardware perspective, oneboard should be able to support either the 440GP processor or the 440GX processor. A clean clock that has relatively low jitter must be provided. For details on jitter limitations, see the PowerPC440GX Embedded Processor Datasheet, listed in Related Documents on page 19.Other configuration changes are modifications for the new software registers. The Software Considerations WhenMigrating to the PowerPC 440GX from the 440GP application note documents these changes.

Revision 1.01 Application Note (Proprietary) 3


Figure 1: 440GX Processor Clocking Structure

Table 2: 440GX Processor Register

Mnemonic NameDCR

Address (0:9)

Bit Usage

(0:15) (16:31)

CPR_CFGADDR Clock / Power-On-ResetConfiguration Address Register x‘00C’ Reserved Offset

CPR_CFGDATA Clock / Power-On-ResetConfiguration Data Register x‘00D’ Read or write data

SDR_CFGADDR System DCRConfiguration Address Register x‘00E’ Reserved Offset

SDR_CFGDATA System DCRConfiguration Data Register x‘00F’ Read or write data

CPRD_PLLDn(FWDVA)

PLL

SYSCLK VCO

feedbackdivider

CPR0_PLLDn(FBDV)

selectedfeedback

CPR0_PLLCn(SEL)

other clocks43210

external

CPR0_PLLDn(EFBOV)

PLLOUTB

PLLOUTA

1

0CPR0_PLLCn(SRC)

Divider MAL

CPR0_OPBDn(OPBDV0)

DividerOPB

Divider PER

CPRO_PERDn(PERDV0)

PLBPrimary B

CPR0_PRIMBDn(PRBDV0)

CPUPrimary A0

1

1

0

forward

forward

SYSCLK

PLLOUTA

Clock Mux

CPR0_PLLDn(ENG)

PLLOUTB

SYSCLK

forward

forwardB

divider

dividerA

feedbackclock

CPR0_PLLDn(FWDVB)

Divider 0

Divider 0A

divider

Bdivider



Default Strapping Comparison During a system reset, both the 440GP and 440GX processors are configured using the strapping (pull-up or pull-down) resistors on various I/Os. Table 3, Table 4, Table 5, and Table 6 beginning on page 4 show the default strap-ping for the 440GX processor. Refer to the PowerPC Embedded Processor User’s Manuals for detailed informationon programming other strapping options for these processors.

• Bit 0Value strapped on pin UART0_DCD_N• Bit 1Value strapped on pin UART0_DRSR_N• Bit 2Value strapped on pin GMC1TxCtl

The values in the following tables assume a system reference clock of 33 MHz. Vary the reference clock and usethe same default values to obtain different frequencies.

Table 3: Default Settings for the 440GX Processor: 8-Bit ROM Option 0x1Serial device is not enabled. Use the following defaults:Voltage controlled oscillator (VCO) = 933 MHz, central processing unit (CPU) = 466 MHz, processor local bus (PLB) = 133 MHz, on-chip peripheral bus (OPB) = 66 MHz, peripheral (PER) = 66 MHz

Strap Bits012 Register Name Bit(s) Field Name Default Value Description

Strap 0

CPR0_PLLC0

1 PLL Engage ‘1’

2 PLL FB Src ‘0 PLLOutA

5:7 PLL FB Selection ‘000’ PLL Output

22:31 PLL Tune Bits ‘1010111110’ 14 < M < 40 (Our M equals 28)

CPR0_PLLD0

3:7 PLL Divider (MULT) ‘01110’ MULT equals 14.

12:15 FWSDVA (RangeA) ‘0010’ VCO equals 933 MHz.CPU (VCO / 2) equals 466 MHz.

21:23 FWDVB (RangeB) ‘111’ VCO equals 933 MHz.PLB (VCO / 7) equals 133 MHz.

CPR0_PRIMBD0 5:7 OUTB Div ‘001’

CPR0_OPDD0 6:7 OPB Div ‘10’ OPB equals 66 MHz



Strap 1

CPR0_PLLD0 26:31 EFBDV (Ext FB Div) ‘000001’

CPR0_PERD0 6:7 PER Div ‘01’ PER equals 66 MHz.

CPR0_MALD0 6:7MAL Div

‘10’Memory access layer (MAL)/Ethernet media access controller (EMAC) interface equals 66 MHz.

SDR0_EBC 2:3 ROM Width ‘00’ 8-bit ROM

SDR0_CP4400 3 ROM Loc ‘0’ Selects 0001 external bus configu-ration (EBC) ROM for this field

SDR0_PCIX0 0 Internal Arb En ‘0’

SDR0_PCIX0

1 Host Config En ‘0’

2 Initial Seq En ‘0’

3 CPU Wait En ‘0’

4:7 PIM Sel ‘01’

8 SDR0_PCIX0 (Req64 En) ‘0’

9:10 SDR0_PCIX0 (Freq Sel) ‘01’

11 SDR0_PCIX0 (Quick PCIX cap Detect En) ‘0’ Quickboot Off

12 SDR0_PCIX0 (PCI Driver Mode Ctrl) ‘0’ 0 equals Multipoint

SDR0_PFC17:9 SDR0_PFC1 (Enet Group) ‘000’ MII and DMA and either CPU

trace or GPIO

10 SDR0_PFC1 (RMII Mode) ‘0’ 100 Mb

SDR0_PFC0 23 SDR0_PFC0 (CPU Trace En) ‘0’

SDR0_CP4400 30 SDR0_CP4400 (Nto1) ‘0’

Table 3: Default Settings for the 440GX Processor: 8-Bit ROM Option (Continued)0x1Serial device is not enabled. Use the following defaults:Voltage controlled oscillator (VCO) = 933 MHz, central processing unit (CPU) = 466 MHz, processor local bus (PLB) = 133 MHz, on-chip peripheral bus (OPB) = 66 MHz, peripheral (PER) = 66 MHz




Table 4: Default Settings for the 440GX Processor: 16-Bit ROM Option 000Serial device is not enabled. Use the following defaults:VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz


Strap 0

CPR0_PLLC0


2 PLL FB Src ‘0’ PLLOutA


22:31 PLL Tune Bits ‘1010111110’ 14 < M < 40 (Our M = 30)

CPR0_PLLD0

3:7 PLL Divider (MULT) ‘01111’ MULT equals 15




CPR0_OPDD0 6:7 OPB Div ‘10’ OPB equals 83 MHz.



Strap 1



CPR0_MALD0 6:7 MAL Div ‘10’ MAL/EMAC interface equals 83 MHz.


SDR0_CP4400 3 ROM Loc ‘0’ Selects 0001 EBC ROM for this field


SDR0_PCIX0




4:7 PIM Sel ‘0000’

8 Req64 En ‘0’

9:10 Freq Sel ‘01’

11 Quick PCIX cap Detect En ‘0’ Quickboot Off

12 PCI Driver Mode Ctrl ‘0’ 0 equals Multipoint

SDR0_PFC17:9 Enet Group ‘000’ MII and DMA and either CPU

Trace or GPIO

10 RMII Mode ‘0’ 100 Mb

SDR0_PFC0 23 CPU Trace En ‘0’

SDR0_CP4400 30 Nto1 ‘0l’

Table 4: Default Settings for the 440GX Processor: 16-Bit ROM Option (Continued)000Serial device is not enabled. Use the following defaults:VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz




Table 5: Default Settings for the 440GX Processor: 32-Bit ROM Option 010Serial device is not enabled. Use the following defaults:VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz

Strap Bits 012 Register Name Bit(s) Field Name Default Value Description

Strap 0

CPR0_PLLC0





CPR0_PLLD0

3:7 PLL Divider (MULT) ‘01111’ MULT equals 15.







Strap 1





SDR0_CP4400 3 ROM Loc ‘0’ Selects 0001 EBC ROM for this field.


SDR0_PCIX0




4:7 PIM Sel ‘0000’

8 Req64 En ‘0’

9:10 Freq Sel ‘01’




trace or GPIO



SDR0_CP4400 30 Nto1 ‘0’

Table 5: Default Settings for the 440GX Processor: 32-Bit ROM Option (Continued)010Serial device is not enabled. Use the following defaults:VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz

Strap Bits 012 Register Name Bit(s) Field Name Default Value Description



Table 6: Default Settings for the 440GX Processor: PCI Boot Option 100Serial device is not enabled. Use the following defaults:VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz


Strap 0

CPR0_PLLC0





CPR0_PLLD0

3:7 PLL Divider (MULT) ‘01110’ MULT equals 15







Strap 1




SDR0_EBC 2:3 ROM Width ‘10’ PCI Boot Option

SDR0_CP4400 3 ROM Loc ‘0’ Selects 001 EBC ROM for this field


SDR0_PCIX0




4:7 PIM Sel ‘0000’

8 Req64 En ‘0’

9:10 Freq Sel ‘01’




trace or GPIO



SDR0_CP4400 30 Nto1 ‘0’

Table 6: Default Settings for the 440GX Processor: PCI Boot Option (Continued)100Serial device is not enabled. Use the following defaults:VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz




Ethernet ChangesThe 440GX processor implements two new Ethernet interfaces with larger first in/ first out queues (FIFOs). Thesenew interfaces support Gbps operations and jumbo packets (that is, packets greater than 1518 bytes). Existingsoftware written for the 440GP processor will execute properly on the 440GX processor. However, new softwarewill be needed to take advantage of the faster and larger interface. The two new interfaces also require two newinterrupts per interface that will drive changes into the interrupt handler routine. For more information on softwarerequirements, see the Software Considerations When Migrating to the PowerPC 440GX Processor from the440GP Processor application note.There is a total of four Ethernet ports, and two support the gigabit Ethernet. These controllers have several config-uration options available to communicate with a device (see Table 7 for supported Ethernet port configurations onthe 440GX processor). On the 440GP processor, there are only two interfaces for communications to physicaldevices.New signal pins are associated with the new Ethernet controllers. These pins are multiplexed with existing signalsthat were on the 440GP processor. Seven combinations of pin multiplexing support the different Ethernet combina-tions listed in Table 7. Select the desired combination by programming the Ethernet group field in the new pinfunction control register, SDR0_PFC1. Table 7 shows that, in gigabit mode, DMA channels 2 and 3 share pins withthe ethernet media access controller pin, EMAC2. Therefore, neither of those DMA channels are available forexternal use when any of the EMAC pins are configured for any setting other than 10/100 Mbps in serial mediaindependent interface (SMII) mode. Note that DMA channels 2 and 3 are still available for use within the processorby internal DMA peripherals or for memory-to-memory transfers. Also, the GPIO[27:31] and CPU trace pins are shared with the gigabit modes for EMAC3. Therefore, they cannotbe used simultaneously unless EMAC3 is only configured for 10/100 Mbps SMII mode. To allow access to the tracefeature when using EMAC3, the trace pins have also been multiplexed onto the external bus master interface(EBMI) signals. Note that the trace and GPIO pins multiplexed with Ethernet signals operate at 2.5 V I/O, and thetrace and EBMI multiplexed signals operate at 3.3 V I/O. See Table 9 on page 15 for a list of I/O signals that aremultiplexed in the 440GX processor.

Table 7: Ethernet Interfaces

Option Number EMAC0 EMAC1 EMAC2 EMAC3 DMA2/3 Trace/GPIO

Trace on EBMI

0 MII Y Y Y

1 RMII RMII Y Y Y

2 SMII SMII SMII SMII Y Y Y

3 RMII RGMII/RTBI Y Y

*4 SMII SMII RGMII/RTBI RGMII/RTBI Y

5 SMII SMII SMII RGMII/RTBI Y Y

6 SMII SMII RGMII/RTBI Y Y

* The two reduced gigabit ethernet media-independent interface (RGMll) / reduced 10-bit interface (RTBl) ports can be combined into a single gigabit ethernet media-independent interface (GMll) / 10-bit interface (TBl) port, per the gigabit Ethernet chart in Table 10 on page 18.



SRAM ChangesThe on-chip SRAM has increased from 8 KB on the 440GP processor to 256 KB on the 440GX processor. The440GX SRAM is divided into four banks of 64 KB each; this requires four bank-configuration registers(SRAM0_SBxCR) for access use. On the 440GP processor, there are two banks of memory available. The 440GXSRAM parity protection is the same as that for the 440GP processor.

Universal Interrupt ControllerFigure 24. shows that two universal interrupt controllers (UIC) have been added for the 440GX processor. A baseUIC cascades the original two UICs from the 440GP processor with a new third UIC for the additional function. The440GP controller has 62 inputs that come from an internal chip component or external devices. There are addi-tional cores in the 440GX processor that have their own interrupts. In order to provide backward compatibility withthe 440GP processor, an additional switch allows the controller to operate in 440GP mode if desired. The switch isimplemented as a bit in the miscellaneous function register, SDR0_MFR. To use this new function in the 440GXprocessor, set the switch to 440GX mode. In this mode, a new UIC, UIC2, is present. The inputs to UIC2 are thenew components of the 440GX processor that are accessible in this mode. For details, see the Software Consider-ations When Migrating to the PowerPC 440GX from 440GP application note.

Table 8: SRAM Comparison

440GX Processor 440GP Processor

Four physical banks of 64 KB Two physical bank of 8 KB

Parity Support Parity support

Memory cycles supported:- Single-beat read and write, one to 16 bytes- 32- and 64-byte burst transfers

Memory cycles supported:- Single-beat read and write, one to 16 bytes- 32- and 64-byte burst transfers

Guarded memory accesses Guarded memory accesses

Sustainable 2.6 GBps peak bandwidth at 166 MHz Sustainable 2.1 GBps peak bandwidth at 133 MHz



Figure 2: Universal Interrupt Controllers

UIC0

UIC1

UIC2

01

23

45

6:31

440GP

Interrupt Queues

440GP

Interrupt Queues

440GX

Interrupt Queues

Critical Interrupt

Noncritical Interrupt

Base UIC

Critical InterruptNoncritical Interrupt

Critical Interrupt


Critical Interrupt


Reserved

Mode



I2O Messaging Unit The I2O messaging unit (IMU) is a new feature in the 440GX processor. This processor local bus (PLB) slave andmaster core allows messages to be transferred between two PLB masters (normally the CPU and an I/O devicesuch as the PCI-X core). Typically, inbound messages are written from the PCI-X or I/O device to the 440GX CPU.Outbound messages are written from the CPU to the PCI-X or I/O device. There are four message registers in the440GX processor, two for inbound messages and two outbound message. The IMU operates at the same fre-quency as the PLB, per the clocking configuration.The IMU core implements the following three different messaging methods:

• Message registers: Messages are transferred among PLB masters by writing and reading 32-bit message registers that are implemented inside the IMU core. Writing to the message registers may cause interrupts to be generated.

• Doorbell registers: Interrupts are generated among the PLB masters by writing to the doorbell registers.• Circular queues: The PLB masters transfer messages by using four circular queues to pass message frame

addresses (MFAs). The IMU core informs the destination device that messages have arrived by setting internal status bits and generating interrupts.

I/O Signal ChangesAlthough the pin count for the 440GP and 440GX processors is the same, the 440GX processor has additional sig-nals. These additional signals are multiplexed with other signals to maintain the pin count, thus preserving thesame package type as with the 440GP processor. The 440GX processor uses the 1.5 V CMOS Cu-11 technology.All Ethernet and DMA signals have changed from 3.3 V to 2.5 V. The trace and GPIO[27:31] signals have changedfrom 3.3 V to 2.5 V. Refer to the PowerPC 440GX Embedded Processor Datasheet for a complete pinout listing.Although the I/O signals have switched from 3.3 V to 2.5 V, the receivers are still 3.3 V tolerant. Therefore, a 3.3 Vdevice can drive the I/O signals. The drivers are 3.3 V or 2.5 V tolerant, but there is no support for 5 V interfaces. Table 9 lists the new 440GX signals that are multiplexed with existing 440GP signals. In general, signals havebeen multiplexed to incorporate the enhanced Ethernet feature of the 440GX interface.

Table 9: Multiplexed Ethernet Signals

Ball MII I/O RMII I/O SMII I/O RGMII I/O Other I/O Other I/O

L05 EMCMDIO I/O EMCMDIO I/O EMCMDIO I/O

J08 EMACMDClk O EMACMDClk O EMACMD-Clk O

G03 EMCRxD0 I EMC0RxD0 I EMCRxD I

E01 EMCRxD1 I EMC0RxD1 I EMC1RxD I

A07 EMCRxD2 I EMC1RxD0 I EMC2RxD I GMC0TxD0 O

H09 EMCRxD3 I EMC1RxD1 I EMC3RxD GMC0TxD1

K01 EMCRxDV I EMC1CRSDV GMC1TxD0 O

1. MII: Media-independent interface2. RMII: Reduced media-independent interface3. SMII: Serial media-independent interface4. RGMII:Reduced gigabit Ethernet media-independent interface. 1000 Mbps standard transceiver interface.



J02 EMCRxClk I GMC1TxD1 O

K03 EMCRxErr I EMC0RxErr I O GMC1TxD2 O

K07 EMCCRS I EMC0CRSDV I O GMC1TxD3 O

J06 EMCTxClk I EMCRefClk I EMCRef-Clk I

J07 EMCCCD I EMC1RxErr I GMC0TxClk O

C05 EMCTxErr O EMC1TxEn O GMC0RxClk I

L06 EMCTxEn O EMC0TxEn O EMCSync O

L09 EMCTxD0 O EMC0TxD0 O EMC0TxD O

K05 EMCTxD1 O EMC0TxD1 O EMC1TxD O

J04 EMCTxD2 O EMC1TxD0 O EMC2TxD O GMC0TxD2

J03 EMCTxD3 O EMC1TxD1 O EMC3TxD GMC0TxD3

P06 GMC0RxD0 I DMAAck2 O

P11 GMC0RxD1 I DMAAck3 O

P16 GMC0RxD2 I EOT2 I/O

M16 GMC0RxD3 I EOT3 I/O

N11 GMC0RxCtl I DMAReq2 I

P01 GMC0TxCtl O DMAReq3 I

P03 GMC1RxClk I TrcTS1 O GPIO27 I/O

R07 GMC1RxD0 I TrcTS2 O GPIO28 I/O

P09 GMC1RxD1 I TrcTS3 O GPIO29 I/O

R09 GMC1RxD2 I TrcTS4 O GPIO30 I/O

T06 GMC1RxD3 I TrcTS5 O GPIO31 I/O

R01 GMC1TxClk O TrcTS6 O

L01 GMCRefClk I

P04 GMC1RxCtl I

L07 GMC1TxCtl O

Table 9: Multiplexed Ethernet Signals (Continued)





AA24 TrcTS1 O BusReq O

AA22 TrcTS2 O ExtAck O

AB23 TrcTS3 O ExtReq I

Y21 TrcTS4 O HoldAck O

Y23 TrcTS5 O HclReq I

P21 TrcTS6 O PERR I/O

Table 9: Multiplexed Ethernet Signals (Continued)





Table 10: Gigabit Ethernet and TBI Mode Multiplexing

Ball RGMII I/O GMII I/O TBI I/O RTBI I/O

A07 GMC0TxD0 O GMCTxDO O TBITxD0 O RTBI0TxD0 O

H09 GMC0TxD1 O GMCTxD1 O TBITxD1 O RTBI0TxD1 O

K01 GMC1TxD1 O GMCTxD4 O TBITxD4 O RTBI1TxD0 O

J02 GMC1TxD1 O GMCTxD5 O TBITxD5 O RTBI1TxD1 O



J07 GMC1TxClk O GMCTxClk O TBITxClk O RTBI0Txclk O

C05 GMC0RxClk I GMCRxClk I TBIRxClk0 I RTBI0RxClk I

J04 GMC0TxD2 O GMCTxD2 O TBITxD2 O RTBIOTxD2 O

J03 GMC0TxD3 O GMCTxD3 O TBITxD3 O RTBIORxD3 O

P06 GMC0RxD0 I GMCRxD0 I TBIRxD0 I RTBIORxD0 I



M16 GMC0RxD3 I GMCRxD3 I TBIRxD3 I RTBIORxD3 I

N11 GMC0RxCtl I GMCRxDv I TBIRxD8 I RTBI0RxCtl I

P01 GMC0TxCtl O GMCTxEn O TBITxD8 I RTBI0TxCtl O

P03 GMC1RxClk I GMCCol I TBIRxClk1 I RTBI1RxClk I

R07 GMC1RxD0 I GMCRxD4 I RBIRxD4 I RTBI1RxD0 I

P09 GMC1RxD1 I GMCRxD5 I TBIRxD5 I RTBI1RxD1 I

R09 GMC1RxD2 I GMCRxD6 I TBIRxD6 I RTBI1RxD2 I

T06 GMC1RxD3 I GMCRxD7 I TBIRxD7 I RTBI1RxD3 I

R01 GMC1TxClk O GMCCrs I RTBI1TxClk O

L01 GMCRefClk I GMCRefClk I GMCRefClk I GMCRefClk I

P04 GMC1RxCtl I GMCRxEr I TBIRxD9 I RTBI1RxCtl I

L07 GMC1TxCtl O GMCTxEr O TBITxD9 O RTBI1TxCtl O

1. RGMII:Reduced gigabit Ethernet media-independent interface. 1000 Mbps standard transceiver interface.2. GMII: Gigabit Ethernet media-independent interface. 1000 Mbps standard transceiver interface.3. TBI: 10-bit interface.4. RTBI:Reduced 10-bit interface.



ConclusionThe PowerPC 440GX processor provides a path that can enable PowerPC 440GP customers to realize improvedsystem performance. Multiplexing additional I/O signals on the 440GX processor maintains the same packagepinout as on the 440GP processor, thus minimizing the effort required to redesign existing 440GP boards. NewPowerPC designs based on the 440GX processor can also use the new performance features of the 440GX pro-cessor by taking advantage of the new Ethernet core, TCP/IP hardware assist, upgraded I2O messaging unit, andincreased SRAM storage capacity.

Related DocumentsAdditional information about the PowerPC 440Gx and 440GP processors is available in the following sources,located at http://www.amcc.com.PPC440GX Embedded Processor User’s Manual. AMCC Corporation.Software Considerations When Migrating to the PowerPC 440GX Processor from the 440GP Processor Applica-tion Note. AMCC Corporation.PowerPC 440GX Embedded Processor Datasheet. AMCC Corporation.



Document Revision HistoryRevision Date Description

v1.01 1/18/08 Converted layout to AMCC format.



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