microcontroladores atmega8

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UNIVERISIDAD NACIONAL DEL CALLAO CURSO: MICROCONTROLADORES PROFESOR: ING. ASTOCONDOR FACULTAD: DE INGENIERIA ELECTRICA Y ELECTRONICA CICLO: 6TO RESOLUCION DEL EXAMEN PARCIAL DE MICROCONTROLADORES w7

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Page 1: Microcontroladores ATMEGA8

UNIVERISIDAD NACIONAL DEL CALLAO

CURSO:

MICROCONTROLADORES

PROFESOR:

ING. ASTOCONDOR

FACULTAD:

DE INGENIERIA ELECTRICA Y ELECTRONICA

CICLO:

6TO

DE

MICROCONTROLADORES

Page 2: Microcontroladores ATMEGA8

PRACTICA2 CALIFICADA –MICROCONTROLADORES

1. USO DE INTERRUPCION INTX.include"m8def.inc" .org 0x0000 rjmp reset .org 0x0001 rjmp ext_0 reset: ldi r16,high(ramend) out sph,r16 ldi r16,low(ramend) out spl,r16 sbi ddrc,0 sbi ddrc,1 cbi ddrd,2

sei ; poner a uno la bandera I del registro de estado ldi r16,0b00001010 out mcucr,r16 ldi r16,0b11000000 out gicr,r16 bucle: sbi portc,0 rcall delay_500ms cbi portc,0 rcall delay_500ms rjmp bucle ext_0: cbi portc,0 sbi portc,1 rcall delay_500ms cbi portc,1 rcall delay_500ms sbi portc,1 rcall delay_500ms cbi portc,1 rcall delay_500ms reti delay_500ms:

; ============================= ; delay loop generator ; 100000 cycles:

; ----------------------------- ; delaying 99990 cycles:

ldi R17, $A5 WGLOOP0: ldi R18, $C9 WGLOOP1: dec R18 brne WGLOOP1 dec R17

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brne WGLOOP0 ; ----------------------------- ; delaying 9 cycles: ldi R17, $03 WGLOOP2: dec R17 brne WGLOOP2 ; ----------------------------- ; delaying 1 cycle: nop ; ============================= ret

2. CONTADOR UP/DOWN DE 00 A 99

.include"m8def.inc"

.org 0x0000 rjmp reset .org 0x0001 rjmp ext_0 .org 0x0002 rjmp ext_1 reset: ;--------------------------- ;puntero de pila ;-------------------------------- ldi r16,0x04 out sph,r16 ldi r16,0x5f out spl,r16 ;-------------------- ;configuracion de entrada y salida ;--------------------------- ldi r16,0xff out ddrb,r16 sbi ddrc,0 sbi ddrc,1 cbi ddrd,2

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cbi ddrd,3 ;--------------------- ;configuracion de las interrupciones esternas ;--------------- sei ; hailitando las interrupciones pone auno la bandera I del registro de estadosa(sreg) ldi r16,0b00001010 out mcucr,r16 ; habilitar las interrepciones externas para que se puedan activar con flanco de bajada ldi r17,0b11000000 out gicr,r17 ;habilitar las interrupciones externas bucle1: nop ; no operacion rjmp bucle1 ext_0: sbi portc,0 cbi portc,1 out portb,r20 rcall delay_40ms inc r20 cpi r21,9 breq sal3 rjmp salto sal3: cpi r20,9 breq sal4 rjmp salto sal4:

clr r21 clr r20 rcall delay_40ms salto: out portb,r20 rcall delay_500ms final: rcall delay_40ms sbi portc,1 cbi portc,0 out portb,r21 cpi r20,9 brne final1 clr r20 inc r21 final1: out portb,r21 rcall delay_40ms sbis pind,2 rjmp ext_0 reti ext_1: sbi portc,0 cbi portc,1 out portb,r20 rcall delay_40ms cpi r20,0 breq salto4 dec r20

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rjmp salto6 salto4: ldi r20,9 salto6: out portb,r20 rcall delay_500ms final2: rcall delay_40ms sbi portc,1 cbi portc,0 cpi r20,0 brne final3 cpi r21,0 breq salto2 dec r21 rjmp final3 salto2: ldi r21,9 final3: out portb,r21 rcall delay_40ms sbis pind,3 rjmp ext_1 reti

delay_500ms: ; ============================= ; delay loop generator ; 80000 cycles: ; ----------------------------- ; delaying 79998 cycles: ldi R17, $86 WGLOOP0: ldi R18, $C6 WGLOOP1: dec R18 brne WGLOOP1 dec R17 brne WGLOOP0 ; ----------------------------- ; delaying 2 cycles: nop nop ; ============================= ret delay_40ms: ; ============================= ; delay loop generator ; 50000 cycles: ; ----------------------------- ; delaying 49995 cycles: ldi R17, $65 WGLOP0: ldi R18, $A4 WGLOP1: dec R18 brne WGLOP1 dec R17 brne WGLOP0 ; ----------------------------- ; delaying 3 cycles: ldi R17, $01

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WGLOP2: dec R17 brne WGLOP2 ; ----------------------------- ; delaying 2 cycles: nop nop ; ============================= ret delay_60ms: ; ============================= ; delay loop generator ; 600000 cycles: ; ----------------------------- ; delaying 599955 cycles: ldi R17, $05 WGOOP0: ldi R18, $C6 WGOOP1: ldi R19, $C9 WGOOP2: dec R19

brne WGOOP2 dec R18 brne WGOOP1 dec R17 brne WGOOP0 ; ----------------------------- ; delaying 45 cycles: ldi R17, $0F WGLOOP3: dec R17 brne WGLOOP3 ; ============================= Ret

EXAMEN PARCIAL –MICROCONTROLADORESProblea 1

.include "m8def.inc"

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.cseg

.org 0x000rjmpinicioinicio:ldi r20,high(ramend)out sph,r20ldi r20,low(ramend)out spl,r20cbi ddrd,pd0;...;interruptor:sbic pind,pd0;salta si pd0=0rjmpinterruptorbucle:ldi r16,0x08out PORTB,R16RCALL DELAY

ldi r16,0x0Cout PORTB,R16RCALL DELAY

ldi r16,0x04out PORTB,R16RCALL DELAY

ldi r16,0x06out PORTB,R16RCALL DELAY

ldi r16,0x02out PORTB,R16RCALL DELAY

ldi r16,0x03out PORTB,R16RCALL DELAY

ldi r16,0x01out PORTB,R16RCALL DELAY

ldi r16,0x09out PORTB,R16rcall DELAY

;_______________;

ldi r16,0x09out PORTB,R16rcall DELAY

ldi r16,0x01out PORTB,R16rcall DELAY

ldi r16,0x03

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Page 8: Microcontroladores ATMEGA8

out PORTB,R16rcall DELAY

ldi r16,0x02out PORTB,R16rcall DELAY

ldi r16,0x06out PORTB,R16rcall DELAY

ldi r16,0x04out PORTB,R16rcall DELAY

ldi r16,0x0Cout PORTB,R16rcall DELAY

ldi r16,0x08out PORTB,R16rcall DELAY

RJMPbucle;............;DELAY:ldi R17, $97WGLOOP0: ldi R18, $06WGLOOP1: ldi R19, $92WGLOOP2: dec R19brne WGLOOP2dec R18brne WGLOOP1dec R17brne WGLOOP0

ret

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Problema 2

.include"m8def.inc"

.org 0x0000 rjmp inicio.org 0x0002rjmp ext_int1 inicio: ldi r16,high(ramend) out sph,r16ldi r17,low(ramend)out spl,r16 ;____________________;ldi r21,0x00ldi r16,0xff out ddrb,r16 cbi ddrd,pd3;__________________;seildi r16,0b00001010 out mcucr,r16 ldi r16,0b10000000 out gicr,r16 bucle: ser r16 out portb,r16 rcall delay500ms clr r16 out portb,r16 rcall delay500ms rjmpbucle;------------- ;llmada de una interrupcion;------------------ ext_int1: clr r16 out portb,r16 sbi portb,pb0 rcall delay500ms cbi portb,pb0 sbi portb,pb1 rcall delay500mscbi portb,pb1 sbi portb,pb2 rcall delay500ms cbi portb,pb2 sbi portb,pb3 rcall delay500ms cbi portb,pb3 sbi portb,pb4 rcall delay500ms cbi portb,pb4 sbi portb,pb5 rcall delay500ms cbi portb,pb5 sbi portb,pb6

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rcall delay500ms cbi portb,pb6 sbi portb,pb7 rcall delay500ms inc r21 cpi r21,4 breqiniciorjmp ext_int1 retidelay500ms: ldi R17, $09 WGLOOP0: ldi R18, $37 WGLOOP1: ldi R19, $C9 WGLOOP2: dec R19brne WGLOOP2 dec R18brne WGLOOP1 dec R17brne WGLOOP0 ldi R17, $01 WGLOOP3: dec R17 brne WGLOOP3 ret

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