Microarchitecture of Superscalars (5)Dynamic Instruction Issue

Dezső Sima

Fall 2007

(Ver. 2.0) Dezső Sima, 2007

Overview

1 The principle of dynamic instruction issue•

2 Design space•

5 Case examples•

2.1 Overview•

2.2 Types of issue buffers•

2.3 Operand fetch policies•

4 Implementation of dynamic instruction issue in superscalars•

4.1 The introduction of dynamic instruction issue•

4.2 Basic implementation schemes•

3 Principle of operation of dynamic instruction issue•

3.1 Dispatch bound operand fetching•

3.2 Issue bound operand fetching•

1. Principle of dynamic instruction issue (1)

Aim: • To eliminate the issue bottleneck of early (first generation) supercalars

1. Principle of dynamic instruction issue (2)

The issue bottleneck

(b): The issue process(a): Simplified structure of the mikroarchitecture assuming unbuffered issue

Figure 1.1: The principle of dynamic instruction issue

Ci

i1i2i3

Instr. windowCycles

C i+1

i2i3

Executable instructionsDependent instructionsIssue

Ci+2

i4i5i6

Icache

I-buffer

Instr. window (3)

Decode,check,issue

Dependent instructions block instruction issue

EU

Issue

EU

I cache

I-buffer

Decode/IssueInstructions are dispatched withoutchecking for dependencies to theshelving buffers (reservation stations)

Shelved not dependent

for execution to the EUs.

EU

Instruction window

instructions are issued

Shelving buffer Shelving buffer

Issue

Dispatch

Dep. checking/issue

Dep. checking/issue

EU

1. Principle of dynamic instruction issue (3)

Figure 1.2: Principle of dynamic instruction issue

(b): The issue process(a): Simplified structure of the mikroarchitecture assuming buffered issue (shelving)

Eliminating the issue bottleneck Dynamic instruction issue

(shelving, buffered issue)

Ci

i2i3i4

Instr. windowCycles

i1

C i+1

i2i3 i1i4

Executable instructionsDependent instructionsIssue

Ci+2

i6i7i8 i5

Layout of the issue buffers

Scope of dynamic instr. issue

Instruction issue scheme

Dynamic instruction issue

Operand fetch policy

2. Design space of dynamic instruction issue

2.1 Overview

Types of issue buffers

2.2 Types of issue buffers

Reservation stations (RS)

Issue buffers in the ROB

Types of issue buffers

Individual RSs

Central RS

Group RSs

RS

FXEU

RS

FPEU

FXEU

RS

FPEU

FXEU

FPEU

Power1 (1990)PowerPC 603 (1993)PowerPC 604 (1995)

Power4 (2001)Power5 (2004)

K5 (1995)K7 (1999), K8 (2003)

RS

FXEU

FX

FXEU

RS

FXEU

FP

FXEU

ES/9000 (1992)Power2 (1993)R10000 (1996)

PM1(Sparc64)(1995)Alpha 21264 (1997)

Pentium Pro (1995)Pentium II (1997)Pentium III (1999)Pentium IV (2000)Pentium M (2003)

Core (2006)

Lightning (1991)pK6 (1997)

Layout of the issue buffers

Scope of buffered issue

Instruction issue scheme

Dynamic instruction issue

Operand fetch policy

Types of issue buffers

2.3 Operand fetch policies

Dispatch boundoperand fetch policy

Issue boundoperand fetch policy

Operand fetch policies

Decode / Issue

EU

Reg. file

IB

OC Rd Op1/Rs1 Op2/Rs2OC

I-buffer

Source reg. identifiers

Opcodes, destination reg. identifiers

Source 1 operands

Source 2 operands

EURd, result

IB

Rd Op1/Rs1 Op2/Rs2

I-buffer

Source reg. identifiers

Opcodes, destination reg. identifiers

Source 1 operands

Source 2 operands

OC Rd

IB

OC Rd

Decode / Issue

Reg. file

EU EU

Source reg. identifiers

Rs1 Rs2

IB

Rs1 Rs2

Dispatch

Issue

Dispatch

Issue

Figure 2.1: Operand fetch policies

3 Principle of operation of dynamic instruction issue

3.1 Dispatch bound operand fetching (1)

• Checking the availability of operands

Decode / Issue

EU

Reg. file

IB

OC Rd Op1/Rs1 Op2/Rs2OC

I-buffer

Source reg. identifiers

Opcodes, destination reg. identifiers

Source 1 operands

Source 2 operands

EURd, result

IB

Rd Op1/Rs1 Op2/Rs2

Dispatch

Issue

V

V V V V

3.1 Dispatch bound operand fetching (2)

• Updating the issue buffers

Decode / Issue

EU

Reg. file

IB

OC Rd Op1/Rs1 Op2/Rs2OC

I-buffer

Source reg. identifiers

Opcodes, destination reg. identifiers

Source 1 operands

Source 2 operands

EURd, result

IB

Rd Op1/Rs1 Op2/Rs2

Dispatch

Issue

V

V V V V

3.2 Issue bound operand fetching

Checking the availability of operands

I-buffer

Source reg. identifiers

Opcodes, destination reg. identifiers

Source 1 operands

Source 2 operands

OC Rd

IB

OC Rd

Decode / Issue

Reg. file

EU EU

Source reg. identifiers

Rs1 Rs2

IB

Rs1 Rs2

Dispatch

Issue

V

4. Implementation of dynamic instruction issue in superscalars

4.1 The introduction of dynamic instruction issue

Figure 4.1: The introduction of dynamic instruction issue

Gmicro/500 (2)

Alpha 21064 (2) Alpha 21064A (2) Alpha 21164 (4)

SuperSparc (3)

PA7100 (2)

Pentium (2)

MC 68060 (3)

1989 1990 1991 1992 1993 1994 1995 1996

MC 88000

Gmicro

M1

SPARC

PowerPC

PA

R

K5

80x86

Power

ES

MC 68000

Nx

Motorola

CYRIX

Sun/Hal

PowerPC

MIPS

AMD

IBM

NexGen

HP

TRON

DEC

Alliance

ES/9000 (2)

PPC 603 (3)PPC 604 (4)

PPC 620 (4)

Nx586 (1/3)1

M1 (2)

K5

UltraSparc (4)

PM1 (4) (Sparc64)

R 8000 (4) R 10000 (4)

PA8000 (4)

PentiumPro (~2)

Power1 (4)(RS/6000)

MC 88110 (2)

PPC 602 (2)

Power2 (4)

PPC 601 (3)

RSC (4)

(~2)

2

2

2

2

2

Alpha 21264 (4)

1997

PA 8200 (4)

R 12000 (4)

RISC processors

CISC processors

The Nx586 has scalar issue for CISC instructions but a 3-way superscalarsuperscalar core for converted RISC instructions.

1- Partial dynamic issue

- Full dynamic issue PowerPC is abbreviated here to PPC2

CISC processors

Motorola

IBM

Intel

PA7200 (2)

Reservation stations (RS)

Issue buffers in the ROB

Basic issue buffer schemes

Individual RSs

Central RS

Group RSs

Typ

es o

f is

sue

buff

ers

Ope

rand

fet

ch p

olic

y

Dispatchbound

Issuebound

Dispatchbound

Issuebound

Dispatchbound

Issuebound

Dispatchbound

Issuebound

PowerPC 603 (1993)PowerPC 604 (1995)

K5 (1995)

Power1 (1990)Power4 (2001)Power5 (2004)Nx586 (1994)

K7 (1999), K8 (2003)

PM1(Sparc64)(1995)

ES/9000 (1992)Power2 (1993)R10000 (1996)

Alpha 21264 (1997)

Pentium Pro (1995)Pentium II (1997)Pentium III (1999)

Pentium IV (2000)Pentium M (2003)

Core (2006)

Lightning (1991)pK6 (1997)

4.2 Basic implementation schemes

5. Case example (1)

Individual issue buffers

Figure 5.1: The microarchitecture of the Athlon

5. Case example (1)

Individual issue buffers (2)

Figure 5.2: Integer issue buffers of the K8L

Source: Malich, Y.„AMD's Next Generation Microarchitecture Preview: from K8 to K8L”, Aug. 2006.

Issue buffersDecoders EUs

5. Case example (2)

Group issue buffers

Figure 5.3: The microarchitecture of the Alpha 21264

Source: Kessler, R.E. et al. .„The Alpha 21264 Microprocessor Architecture”, h18002.www1.hp.com/alphaserver

5. Case example (3)

Central reservation station (1)

Figure 5.3: The microarchitecture of the Core processor

Source: Kanter, D., „Intel’s next Generation Microarchitecture Unveiled”, Real World Tech., 2006 March 9.