micro controler 8051

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A Course on REAL-TIME EMBEDDED SYSTEMS . . . by Krest Technologies

MICRO CONTROLLER 8051

EMBEDDED SYSTEMSWhat Is an Embedded System?

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An em edded system is a unit 'a*ing $om ination o+ so+t)are and 'ard)are along)it' me$'ani$al parts.

A general#purpose de+inition o+ em edded systems is t'at t'ey are de*i$es used to$ontrol, monitor or assist t'e operation o+ e uipment, ma$'inery or plant.

An embedded system &s des&'ned to (er)orm a ded&cated )*nct&on

Most em edded de*i$es are primarily designed +or one spe$i+i$ +un$tion. de*i$es su$' as personal data assistant -P A/0$ell p'one 'y rids, )'i$' are

em edded systems designed to e a le to do a *ariety o+ primary +un$tions.

digital 2s in$lude intera$ti*e appli$ations t'at per+orm a )ide *ariety o+ general+un$tions unrelated to t'e 3 23 +un$tion ut 4ust as important, su$' as e#mail, )e

ro)sing, and games.

Character&st&cs o) Embedded Systems:

Reliability: pro a ility o+ system )or&ing $orre$tly Maintainability: pro a ility o+ system )or&ing $orre$tly time units a+ter error o$$urred.

Availability: pro a ility o+ system )or&ing at time t

Safety: no 'arm to e $aused

Security: $on+idential and aut'enti$ $ommuni$ation

Energy e++i$ient

C !e"#i$e e++i$ient -espe$ially +or systems on a $'ip/

Run"ti%e e++i$ient

&eig't e++i$ient

C #t e++i$ient

(e!icate! to)ards a $ertain a))licati n ! 5no)ledge a out e'a*ior at design time $an e used to minimize resour$es and to ma imize ro ustness.

(e!icate! user interface -no mouse, &ey oard and s$reen/.

MICR, R,CESS,R -----------------------------------------------------------------------------------------------------------------------------------------------------------------

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A Mi$ropro$essor is +undamentally a $olle$tion o+ on0o++ s)it$'es laid out o*er sili$on in order to per+orm Computations.

C'aracteri#tic# f a Micr )r ce## r:

Hig' $ost, Hig' speed, on t'e order o+ 188 MHz 9 :Hz

Hig' Po)er $onsumption, lots o+ 'eat

;arge ar$'ite$ture,


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C'aracteri#tic# f a Micr c ntr ller:

;o) $ost ;o) speed, on t'e order o+ 18 5Hz 78 MHz

Small ar$'ite$ture, usually an ># it ar$'ite$ture

Small memory size, ut usually enoug' +or t'e type o+ appli$ation it is intended +or=n oard Flas'.

;imited I0=, ut again, enoug' +or t'e type o+ appli$ation.

;o) Po)er, e tremely lo) po)er in sleep mode.

Choos&n' a m&crocontro//er

'ere are +our ma4or ># it mi$ro$ontrollers. 'ey are! Frees$ale?s 6>11, Intel?s >8@1,ilog?s >, and PIC 16 +rom Mi$ro$'ip e$'nology. "a$' o+ t'ese mi$ro$ontrollers 'as a

uni ue instru$tion set and register set t'ere+ore, t'ey are not $ompati le )it' ea$' ot'er.Programs )ritten +or one )ill not run on t'e ot'ers. 'ere are also 16# it and


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'e +irst and +oremost $riterion in $'oosing a mi$ro$ontroller is t'at it mustmeet t'e tas& at 'and e++i$iently and $ost e++e$ti*ely. In analyzing t'e needso+ a mi$ro$ontroller# ased pro4e$t, )e must +irst see )'et'er an ># it, 16# it,or 1, Intel Corporation introdu$ed an ># it mi$ro$ontroller$alled t'e >8@1. 'is mi$ro$ontroller 'ad 17> ytes o+ GAM, 95 ytes o+ on#$'ip G=M, t)otimers, one serial port, and +our ports -ea$' ># its )ide/ all on a single $'ip. At t'e time it )as

also re+erred to as a 3system on a $'ip.3 'e >8@1 is an ># it pro$essor, meaning t'at t'e CP$an )or& on only > its o+ data at a time. ata larger t'an > its 'as to e ro&en into ># it pie$esto e pro$essed y t'e CP . 'e >8@1 'as a total o+ +our I0= ports, ea$' > its )ide. Alt'oug't'e >8@1 $an 'a*e a ma imum o+ 695 ytes o+ on#$'ip G=M, many manu+a$turers 'a*e put only95 ytes on t'e $'ip.

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,ther members o) the "3%! )am&/y ! 'ere are t)o ot'er mem ers in t'e >8@1 +amily o+mi$ro$ontrollers. 'ey are t'e >8@7 and t'e >8


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Ha*e 98 pins dedi$ated +or *arious+un$tions su$' as I0=, #G , #(G, address, data, andinterruptsCome in di++erent pa$&ages, su$' as

IP-dual in#line pa$&age/,FP- uad +lat pa$&age/, and

;;C-leadless $'ip $arrier/Some $ompanies pro*ide a 78#pin *ersion o+ t'e >8@1 )it' a redu$ed num er o+ I0=

ports +or less demanding appli$ations

'e >8@1 is t'e original mem er o+ t'e >8@1 +amily. Intel re+ers to it as MCS#@1.

2o5 to 5or6 on embedded system?

(e $an di*ide our re uirements on t)o di++erent sets.

!7 2ARDWARE:

1/ Cir$uit esigning

7/ Cpu sele$tion


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INTRO(*CTION O+ AT8,C51

A Mi$ro $ontroller $onsists o+ a po)er+ul CP tig'tly $oupled )it' memory, *arious I0=inter+a$es su$' as serial port, parallel port timer or $ounter, interrupt $ontroller, data a$ uisitioninter+a$es#Analog to igital $on*erter, igital to Analog $on*erter, integrated on to a singlesili$on $'ip.

I+ a system is de*eloped )it' a mi$ropro$essor, t'e designer 'as to go +or e ternalmemory su$' as GAM, G=M, "PG=M and perip'erals. But $ontroller is pro*ided all t'ese+a$ilities on a single $'ip. e*elopment o+ a Mi$ro $ontroller redu$es PCB size and $ost o+design.=ne o+ t'e ma4or di++eren$es et)een a Mi$ropro$essor and a Mi$ro $ontroller is t'at a $ontrollero+ten deals )it' its not ytes as in t'e real )orld appli$ation.

Intel 'as introdu$ed a +amily o+ Mi$ro $ontrollers $alled t'e MCS#@1.

The Ma9or 1eat*res:

Compati le )it' MCS#@1 produ$ts 9& Bytes o+ in#system Geprogramma le +las' memory Fully stati$ operation! 8H to 79MH 'ree le*el programma le $lo$& 17> K > it timer0$ounters Si interrupt sour$es Programma le serial $'annel ;o) po)er idle po)er#do)n modes.

Why AT " C%!

'e system re uirements and $ontrol spe$i+i$ations $learly rule out t'e use o+ 16,


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to large num er o+ internal +eatures. 'ey are also +aster and more relia le ut, ># it mi$ro$ontroller satis+a$torily ser*es t'e a o*e appli$ation. sing an ine pensi*e ># it Mi$ro$ontroller)ill doom t'e C@1 o+ all t'e ># it mi$ro$ontroller a*aila lein t'e mar&et t'e main ans)er )ould e e$ause it 'as 9 5 on $'ip +las' memory )'i$' is 4ustsu++i$ient +or our appli$ation. 'e on#$'ip Flas' G=M allo)s t'e program memory to ereprogrammed in system or y $on*entional non#*olatile memory Programmer. Moreo*erA M"; is t'e leader in +las' te$'nology in todayLs mar&et pla$e and 'en$e using A > C@1 ist'e optimal solution.

AT" C%! MICR,C,.TR,LLER ARC2ITECT8RE

'e > C@1 ar$'ite$ture $onsists o+ t'ese spe$i+i$ +eatures!

"ig't it CP )it' registers A -t'e a$$umulator/ and B Si teen# it program $ounter -PC/ and data pointer - P G/ "ig't# it sta$& pointer -PS(/ "ig't# it sta$& pointer -Sp/ Internal G=M or "PG=M ->J@1/ o+ 8->8 C@1/ Internal GAM o+ 17> ytes!

! Four register an&s, ea$' $ontaining eig't registers4 Si teen ytes, )'i$' may e addressed at t'e it le*el

"ig'ty ytes o+ general# purpose data memory 'irty t)o input0output pins arranged as +our ># it ports!p8#p< )o 16# it timer0$ounters! 8 and 1 Full duple serial data re$ei*er0transmitter! SB F Control registers! C=E, M= , SC=E, PC=E, IP, and I" )o e ternal and t'ree internal interrupts sour$es. =s$illator and $lo$& $ir$uits.

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1*nct&ona/ b/oc6 d&a'ram o) m&cro contro//er The " C%! osc&//ator and c/oc6:

'e 'eart o+ t'e > C@1 $ir$uitry t'at generates t'e $lo$& pulses y )'i$' all t'e internalall internal operations are syn$'ronized. Pins A;1 and A;7 is pro*ided +or $onne$ting aresonant net)or& to +orm an os$illator. ypi$ally a uartz $rystal and $apa$itors are employed.

'e $rystal +re uen$y is t'e asi$ internal $lo$& +re uen$y o+ t'e mi$ro$ontroller. 'emanu+a$turers ma&e > C@1 designs t'at run at spe$i+i$ minimum and ma imum +re uen$iestypi$ally 1 to 16 MHz.

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,sc&//ator and t&m&n' c&rc*&t

Ty(es o) memory:

'e > C@1 'a*e t'ree general types o+ memory. 'ey are on#$'ip memory, e ternalCode memory and e ternal Gam. =n#C'ip memory re+ers to p'ysi$ally e isting memory on t'emi$ro $ontroller itsel+. " ternal $ode memory is t'e $ode memory t'at resides o++ $'ip. 'is iso+ten in t'e +orm o+ an e ternal "PG=M. " ternal GAM is t'e Gam t'at resides o++ $'ip. 'iso+ten is in t'e +orm o+ standard stati$ GAM or +las' GAM.

a7 Code memory

Code memory is t'e memory t'at 'olds t'e a$tual > C@1 programs t'at is to e run. 'ismemory is limited to 695. Code memory may e +ound on#$'ip or o++#$'ip. It is possi le to'a*e 95 o+ $ode memory on#$'ip and 685 o++ $'ip memory simultaneously. I+ only o++#$'ipmemory is a*aila le t'en t'ere $an e 695 o+ o++ $'ip G=M. 'is is $ontrolled y pin

pro*ided as "A.b7 Interna/ RAM

'e > C@1 'a*e a an& o+ 17> o+ internal GAM. 'e internal GAM is +ound on#$'ip. Soit is t'e +astest Gam a*aila le. And also it is most +le i le in terms o+ reading and )riting.

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Internal Gam is *olatile, so )'en > C@1 is reset, t'is memory is $leared. 17> ytes o+ internalmemory are su di*ided. 'e +irst


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SRAM Stati$ Gandom#A$$ess Memory

Hig'est speed, 'ig'#po)er, lo)#densitymemory limited density dri*es up $ost

E R,M

"le$tri$ally Programma le Gead#=nlyMemory

Hig'#density memory must e e posed to

ultra*iolet lig't +or erasure

EE R,MorE 4 R,M"le$tri$ally "rasa le Programma le Gead#=nly Memory

"le$tri$ally yte#erasa le lo)er relia ility,'ig'er $ost, lo)est density

DRAM ynami$ Gandom A$$ess Memory

Hig'#density, lo)#$ost, 'ig'#speed, 'ig'# po)er

Techn&ca/ ,;er;&e5 o) 1/ash Memory

Flas' memory is a non*olatile memory using E=G te$'nology, )'i$' allo)s t'e user toele$tri$ally program and erase in+ormation. Intel Flas' memory uses memory $ells similar to an"PG=M, ut )it' a mu$' t'inner, pre$isely gro)n o ide et)een t'e +loating gate and t'e sour$e-see Figure 7/. Flas' programming o$$urs )'en ele$trons are pla$ed on t'e +loating gate. 'e$'arge is stored on t'e +loating gate, )it' t'e o ide layer allo)ing t'e $ell to e ele$tri$allyerased t'roug' t'e sour$e. Intel Flas' memory is e tremely relia le non*olatile memoryar$'ite$ture.

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&n d&a'ram o) AT" C%!

I. DESCRI TI,.

0CC: Supply *oltage.


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ort 3:Port 8 is an ># it open#drain i#dire$tional I0= port. As an output port, ea$' pin $an sin&

eig't ; inputs. ('en oneLs are )ritten to port 8 pins, t'e pins $an e used as 'ig' impedan$einputs. Port 8 may also e $on+igured to e t'e multiple ed lo) order address0data us duringa$$esses to e ternal program and data memory. In t'is mode P8 'as internal pull#ups. Port 8 alsore$ei*es t'e $ode ytes during Flas' programming, and outputs t'e $ode ytes during program*eri+i$ation. " ternal pull#ups are re uired during program *eri+i$ation.

ort !:Port 1 is an ># it i#dire$tional I0= port )it' internal pull#ups. 'e Port 1 output u++ers

$an sin&0sour$e +our ; inputs. ('en 1s are )ritten to Port 1 pins t'ey are pulled 'ig' y t'einternal pull#ups and $an e used as inputs. As inputs, Port 1 pins t'at are e ternally eing pulledlo) )ill sour$e $urrent -II;/ e$ause o+ t'e internal pull#ups. Port 1 also re$ei*es t'e lo)#orderaddress ytes during Flas' programming and *eri+i$ation.

ort 4:Port 7 is an ># it i#dire$tional I0= port )it' internal pull#ups. 'e Port 7 output u++ers

$an sin&0sour$e +our ; inputs. ('en 1s are )ritten to Port 7 pins t'ey are pulled 'ig' y t'einternal pull#ups and $an e used as inputs. As inputs, Port 7 pins t'at are e ternally eing pulledlo) )ill sour$e $urrent -II;/ e$ause o+ t'e internal pull#ups. Port 7 emits t'e 'ig'#order address

yte during +et$'es +rom e ternal program memory and during a$$esses to e ternal datamemories t'at use 16# it addresses -M=2 % P G/. In t'is appli$ation, it uses strong internal

pull#ups )'en emitting 1s. uring a$$esses to e ternal data memories t'at use ># it addresses-M=2 % GI/, Port 7 emits t'e $ontents o+ t'e P7 Spe$ial Fun$tion Gegister. Port 7 alsore$ei*es t'e 'ig'#order address its and some $ontrol signals during Flas' programming and*eri+i$ation.

ort :Port < is an ># it i#dire$tional I0= port )it' internal pull#ups. 'e Port < output u++ers

$an sin&0sour$e +our ; inputs. ('en 1s are )ritten to Port < pins t'ey are pulled 'ig' y t'einternal pull#ups and $an e used as inputs. As inputs, Port < pins t'at are e ternally eing pulledlo) )ill sour$e $urrent -II;/ e$ause o+ t'e pull#ups.Port < also ser*es t'e +un$tions o+ *arious spe$ial +eatures o+ t'e A > C@1 as listed elo)!Port < also re$ei*es some $ontrol signals +or Flas' programming and *eri+i$ation

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ALE= R,"H. (it' t'e it set,A;" is a$ti*e only during a M=2 or M=2C instru$tion. =t'er)ise, t'e pin is pulled 'ig'.Setting t'e A;"#disa le it 'as no e++e$t i+ t'e mi$ro$ontroller is in e ternal e e$ution mode.

SE.:Program Store "na le is t'e read stro e to e ternal program memory. ('en t'e

A > C@1 is e e$uting $ode +rom e ternal program memory, PS"E is a$ti*ated t)i$e ea$'ma$'ine $y$le, e $ept t'at t)o PS"E a$ti*ations are s&ipped during ea$' a$$ess to e ternal datamemory.

EA=0 : " ternal A$$ess "na le "A must e strapped to :E in order to ena le t'e de*i$e to+et$' $ode +rom e ternal program memory lo$ations starting at 8888H up to FFFFH.

Eote, 'o)e*er, t'at i+ lo$& it 1 is programmed, "A )ill e internally lat$'ed on reset."A s'ould e strapped to 2CC +or internal program e e$utions. 'is pin also re$ei*es t'e 17#*olt

programming ena le *oltage -2PP/ during Flas' programming, +or parts t'at re uire 17#*olt2PP.

>TAL!:Input to t'e in*erting os$illator ampli+ier and input to t'e internal $lo$&

operating $ir$uit.

>TAL4:It is t'e =utput +rom t'e in*erting os$illator ampli+ier.

,sc&//ator Character&st&cs:

A;1 and A;7 are t'e input and output, respe$ti*ely, o+ an in*erting ampli+ier)'i$' $an e $on+igured +or use as an on#$'ip os$illator "it'er a uartz $rystal or $erami$resonator may e used. o dri*e t'e de*i$e +rom an e ternal $lo$& sour$e, A;7 s'ould e le+tun$onne$ted )'ile A;1 is dri*en. 'ere are no re uirements on t'e duty $y$le o+ t'e e ternal

$lo$& signal, sin$e t'e input to t'e internal $lo$&ing $ir$uitry is t'roug' a di*ide# y#t)o +lip#+lop, ut minimum and ma imum *oltage 'ig' and lo) time spe$i+i$ations must e o ser*ed.

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! nder steady state -non#transient/ $onditions, I=; must e e ternally limited as

+ollo)s! Ma imum I=; per port pin! 18 mA Ma imum I=; per ># it port! Port 8! 76 mA Ports 1, 7,

not guaranteed to sin& $urrent greater t'an t'e listed test $onditions.

4. Minimum 2CC +or Po)er#do)n is 72.

E>AM LE R,


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4 Wr&te an "3%! C (ro'ram to to''/e b&t D3 o) the (ort !@ ! 37 %3 333 t&mes

Nin$lude Oreg@1.'

s it MUBI RP1V8

*oid main-*oid/

Q

unsigned int z

+or -zR8 zOR@8888 z /

Q

MUBI R8

MUBI R1

T

T

Wr&te a ro'ram to s5&tch ,11 and ,. the LED s 6ee( &t *(to % *s *s&n' by de/ay

)*nct&on?

Nin$ludeOreg@1.' 00adding >8@1 ar$'ite$ture support +ile to sour$e program

*oid elay-*oid/ 00delay +un$tion de$laration at start o+ program

*oid main -/

QP7 R8 FF 00Ma&ing P7 port to get 'ig' logi$

elay -/ 00&eeping P7 to @ us as a 'ig' logi$ y generating delay

00using y delay +un$tion

P7 R 8 88 00Ma&ing P7 port to get lo) logi$

elay -/ 00&eeping P7 to @ us as a lo) logi$ y generating delay

00 using y delay +un$tion

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T

*oid elay-*oid/

Q unsigned int i

+or -iR8 iO@ i /

T

RE8@1 t'ere is only one data type! > its. 'e> its o+ a register are s'o)n in t'e diagram +rom t'e MSB -most signi+i$ant it/ J to t'e ;SB-least signi+i$ant it/ 8. (it' an ># it data type, any data larger t'an > its must e ro&en into># it $'un&s e+ore it is pro$essed. Sin$e t'ere are a large num er o+ registers in t'e >8@1, )e)ill $on$entrate on some o+ t'e )idely used general#purpose registers and $o*er spe$ial registersin +uture $'apters.

D D# D% D$ D D4 D! D3

'e most )idely used registers o+ t'e >8@1 are A -a$$umulator/, B, G8, G1, G7, G8@1,registers A, B, PS( and P G are part o+ t'e group o+ registers $ommonly re+erred to as SFG-spe$ial +un$tion registers/. 'ere are many spe$ial +un$tion registers and t'ey are )idely used.

'e SFG $an e a$$essed y t'e names -)'i$' is mu$' easier/ or y t'eir addresses. Fore ample, register A 'as address "8', and register B 'as een ignited t'e address F8H.

'e +ollo)ing t)o points s'ould noted a out t'e SFG addresses.

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!7 'e Spe$ial +un$tion registers 'a*e addresses et)een >8H and FFH. 'ese addressesare a o*e >8H, sin$e t'e addresses 88 to JFH are addresses o+ GAM memory inside t'e>8@1.

47 Eot all t'e address spa$e o+ >8H to FFH is used y t'e SFG. 'e unused lo$ations >8Hto FFH are reser*ed and must not e used y t'e >8@1 programmer.

Gegarding dire$t addressing mode, noti$e t'e +ollo)ing t)o points!

@a7 'e address *alue is limited to one yte, 88#FFH, )'i$' means t'is addressing modeis limited to a$$essing GAM lo$ations and registers lo$ated inside t'e >8@1.

@b7 I+ you e amine t'e l st +ile +or an assem ly language program, you )ill see t'at t'eSFG registers names are repla$ed )it' t'eir addresses as listed in ta le.

Symbo/ .ame AddressACC A$$umulator 8"8HB B register 8F8HPS( Program status )ord 8 8HSP Sta$& pointer >1H

P G ata pointer 7 ytesP; ;o) yte >7HPH Hig' yte >8HP1 Port1 8HP7 Port7 8A8HP< Port< 8B8HIP Interrupt priority $ontrol 8B>H

I" Interrupt ena le $ontrol 8A>HM= imer0$ounter mode $ontrol > HC=E imer0$ounter $ontrol >>H7C=E imer0$ounter 7 $ontrol 8C>H7M= imer0$ounter mode7 $ontrol 8C HH8 imer0$ounter 8'ig' yte >CH;8 imer0$ounter 8 lo) yte >AHH1 imer0$ounter 1 'ig' yte > H;1 imer0$ounter 1 lo) yte >BHH7 imer0$ounter 7 'ig' yte 8C H;7 imer0$ounter 7 lo) yte 8CCH

GCAP7H 0C 7 $apture register 'ig' yte 8CBHGCAP7; 0C 7 $apture register lo) yte 8CAHSC=E Serial $ontrol >HSB F Serial data u++er HPC=E Po)er $ontrol >JH

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"3%! S(ec&a/ )*nct&on re'&ster Address

A @Acc*m*/ator7 Re'&ster:

'is is a general#purpose register )'i$' ser*es +or storing intermediate results during operating.A num er -an operand/ s'ould e added to t'e a$$umulator prior to e e$ute an instru$tion uponit. =n$e an arit'meti$al operation is per+ormed y t'e A; , t'e result is pla$ed into t'ea$$umulator. I+ a data s'ould e trans+erred +rom one register to anot'er, it must go t'roug'a$$umulator. For su$' uni*ersal purpose, t'is is t'e most $ommonly used register t'at nonemi$ro$ontroller $an e imagined )it'out -more t'an a 'al+ >8@1 mi$ro$ontroller?s instru$tionsused use t'e a$$umulator in some )ay/.

B Re'&ster :

B register is used during multiply and di*ide operations )'i$' $an e per+ormed only uponnum ers stored in t'e A and B registers. All ot'er instru$tions in t'e program $an use t'is registeras a spare a$$umulator -A/.

uring programming, ea$' o+ registers is $alled y name so t'at t'eir e a$t address is notso important +or t'e user. uring $ompiling into ma$'ine $ode -series o+ 'e ade$imal num ersre$ognized as instru$tions y t'e mi$ro$ontroller/, PC )ill automati$ally, instead o+ registersLname, )rite ne$essary addresses into t'e mi$ro$ontroller.

R Re'&sters @R3-R 7:

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'is is a $ommon name +or t'e total > general purpose registers -G8, G1, and G7 ...GJ/. "*ent'ey are not true SFGs, t'ey deser*e to e dis$ussed 'ere e$ause o+ t'eir purpose. 'e an& isa$ti*e )'en t'e G registers it in$ludes are in use. Similar to t'e a$$umulator, t'ey are used +ortemporary storing *aria les and intermediate results. ('i$' o+ t'e an&s )ill e a$ti*e dependson t)o its in$luded in t'e PS( Gegister. 'ese registers are stored in +our an&s in t'e s$ope o+

GAM.

'e +ollo)ing e ample est illustrates t'e use+ul purpose o+ t'ese registers. Suppose t'atmat'emati$al operations on num ers pre*iously stored in t'e G registers s'ould e per+ormed!-G1 G7/ # -G< G9/. = *iously, a register +or temporary storing results o+ addition is needed.

"*eryt'ing is uite simple and t'e program is as +ollo)s!

M,0 A R Means! mo*e num er +rom G< into a$$umulator

ADD A R$ Means! add num er +rom G9 to a$$umulator -result remains in a$$umulator/

M,0 R% A Means! temporarily mo*es t'e result +rom a$$umulator into G@

M,0 A R! Means! mo*e num er +rom G1 into a$$umulator

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24/71


ADD A R4 Means! add num er +rom G7 to a$$umulator

S8BB A R% Means! su tra$t num er +rom G@ -t'ere are G< G9/

"3%! Re'&ster Ban6s and Stac6:

RAM memory s(ace a//ocat&on &n the "3%!

'ere are 17> ytes o+ GAM in t'e >8@1. 'e 17> ytes o+ GAM inside t'e >8@1 areassigned addresses 88 toJFH. 'ese 17> ytes are di*ided into t'ree di++erent groups as +ollo)s!

! A total o+ 8 lo$ations o+ GAM are )idely used +ort'e purpose o+ storing data and parameters use >8@1 programmers.

Re'&ster ban6s &n the "3%!:

A total o+ and goes to lo$ation 8FH.'e t'ird an& o+ G8#GJ starts at memory lo$ation 18H and goes to lo$ation 1JH. Finally, GAM

lo$ations 1>H to 1FH are set aside +or t'e +ourt' an& o+ G8#GJ. Fig s'o)s 'o) t'e


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RAM A//ocat&on &n the "3%!

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SW Re'&ster @ ro'ram Stat*s Word7

'is is one o+ t'e most important SFGs. 'e Program Status (ord -PS(/ $ontains se*eral status its t'at re+le$t t'e $urrent state o+ t'e CP . 'is register $ontains! Carry it, Au iliary Carry,t)o register an& sele$t its, =*er+lo) +lag, parity it, and user#de+ina le status +lag. 'e A;automati$ally $'anges some o+ registerLs its, )'i$' is usually used in regulation o+ t'e program

per+orming.

- ar&ty b&t

I+ a num er in a$$umulator is e*en t'en t'is it )ill e automati$ally set -1/, ot'er)ise it )ill e$leared -8/. It is mainly used during data transmission and re$ei*ing *ia serial $ommuni$ation.

- B&t !: 'is it is intended +or t'e +uture *ersions o+ t'e mi$ro$ontrollers, so it is not supposed to e 'ere.

,0 ,;er)/o5 !

=$$urs )'en t'e result o+ arit'meti$al operation is greater t'an 7@@ -de$imal/, so t'at it$annot e stored in one register. In t'at $ase, t'is it )ill e set -1/. I+ t'ere is no o*er+lo), t'is

it )ill e $leared -8/.

RS3 RS! - Re'&ster ban6 se/ects b&ts

'ese t)o its are used to sele$t one o+ t'e +our register an&s in GAM. By )riting zeroes andones to t'ese its, a group o+ registers G8#GJ is stored in one o+ +our an&s in GAM.

RS! RS4 S(ace &n RAM

8 8 Ban&8 88'#8J'

8 1 Ban&1 8>'#8F'

1 8 Ban&7 18'#1J'

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27/71


1 1 Ban&< 1>'#1F'

13 - 1/a' 3 'is is a general#purpose it a*aila le to t'e user.

AC - A* &/&ary Carry 1/a' is used +or BC operations only.

CY - Carry 1/a' is t'e -nint'/ au iliary it used +or all arit'meti$al operations and s'i+tinstru$tions.

D TR Re'&ster @Data o&nter7:

'ese registers are not true ones e$ause t'ey do not p'ysi$ally e ist. 'ey $onsist o+ t)oseparate registers! PH - ata Pointer Hig'/ and - ata Pointer ;o)/. 'eir 16 its are used +ore ternal memory addressing. 'ey may e 'andled as a 16# it register or as t)o independent >#

it registers. Besides, t'e P G Gegister is usually used +or storing data and intermediate results)'i$' 'a*e not'ing to do )it' memory lo$ations.

S Re'&ster @Stac6 o&nter7:

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'e sta$& is a se$tion o+ GAM used y t'e CP to store in+ormation temporarily. 'isin+ormation $ould e data or an address. 'e CP needs t'is storage area sin$e t'ere are only alimited num er o+ registers.

2o5 stac6s are accessed &n the "3%!

I+ t'e sta$& is a se$tion o+ GAM, t'ere must e registers inside t'e CP to point to it.'e register used to a$$ess t'e sta$& is $alled t'e SP -Sta$& point/ Gegister. 'e sta$& pointer in

t'e >8@1 is only > its )ide )'i$' means t'at it $an ta&e *alues o+ 88 to FFH. ('en t'e >8@1 is po)ered up, t'e SP register $ontains *alue 8J. 'is means t'at GAM lo$ation 8> is t'e +irstlo$ation used +or t'e sta$& y t'e >8@1. 'e storing o+ a CP register in t'e sta$& is $alled aP SH, and pulling t'e $ontents o++ t'e sta$& a$& into a CP register is $alled a P=P. In ot'er)ords, a register is pus'ed onto t'e sta$& to sa*e it and popped o++ t'e sta$& to retrie*e it. 'e

4o o+ t'e SP is *ery $riti$al )'en pus' and pop a$tions are per+ormed.

*sh&n' onto the stac6

In t'e >8@1 t'e sta$& pointer -SP/ points to t'e last used lo$ation o+ t'e sta$&. As )e pus' data onto t'e sta$&, t'e sta$& pointer is in$remented y one. Eoti$e t'at t'is di++erent +rommany mi$ropro$essors, nota ly >6 pro$essors in )'i$' t'e SP is de$remented )'en data is

pus'ed onto t'e sta$&. As ea$' P SH is e e$uted, t'e $ontents o+ t'e register are sa*ed on t'esta$& and SP is in$remented y 1. Eoti$e t'at +or e*ery yte o+ data sa*ed on t'e sta$& and t'enSP is in$remented only on$e. Eoti$e also t'at to pus' t'e registers onto t'e sta$& )e must uset'eir GAM addresses. For e ample, t'e instru$tion XP SHY pus'es register G1 onto t'e sta$&.

o((&n' )rom the stac6

Popping t'e $ontents o+ t'e sta$& a$& into a gi*en register is t'e opposite pro$ess o+ pus'ing. (it' e*ery pop, t'e top yte o+ t'e sta$& is $opied to t'e register spe$i+ied y t'einstru$tion and t'e sta$& pointer is de$remented on$e.

The *((er /&m&t o) the stac6

As, mentioned earlier, lo$ations 8> to 1FH in t'e >8@1 GAM $an e used +or t'e sta$&.'is is e$ause lo$ations 78#7FH o+ GAM are reser*ed +or it#addressa le memory and must not

e used y t'e sta$&. I+ in a program )e need more t'an 79 ytes -8> to 1FHR79 ytes/ o+ sta$&,)e $an $'ange t'e SP to point to GAM lo$ations


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In $ase t'at e ternal memory and serial $ommuni$ation system are not in use t'en, 9 ports )it' in total o+ 8@1 $an a$$ess programaddresses 8888 to FFFFH, a total o+ 69& ytes o+ $ode.

Ty(es o) &nstr*ct&ons

epending on operation t'ey per+orm, all instru$tions are di*ided in se*eral groups!

Arit'meti$ Instru$tions Bran$' Instru$tions ata rans+er Instru$tions ;ogi$al Instru$tions ;ogi$al Instru$tions )it' its

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'e +irst part o+ ea$' instru$tion, $alled ME"M=EIC re+ers to t'e operation an instru$tion per+orms -$opying, addition, logi$al operation et$./. Mnemoni$s $ommonly are s'ortened +orm o+name o+ operation eing e e$uted. For e ample!

I.C R1 : In$rement G1 -in$rement register G1/LJMP LAB5 : ;ong Zump ;AB@ -long 4ump to address spe$i+ied as ;AB@/JNZ LOOP: Zump i+ Eot ero ;==P -i+ t'e num er in t'e a$$umulator is not 8, 4ump toaddress spe$i+ied as ;==P/

Anot'er part o+ instru$tion, $alled =P"GAE is separated +rom mnemoni$ at least yone empty spa$e and de+ines data eing pro$essed y instru$tions. Some instru$tions 'a*e nooperand some 'a*e one, t)o or t'ree. I+ t'ere is more t'an one operand in instru$tion, t'ey areseparated y $omma.

RET - -return +rom su #routine/

JZ TEMP - -i+ t'e Eo. in t'e a$$umulator is not 8, 4ump to address spe$i+ied as "MP/ ADD A,R3 - -add G< and a$$umulator/

CJNE A,#20,LOOP - -$ompare a$$umulator )it' 78. I+ t'ey are not e ual, 4ump to addressspe$i+ied as ;==P/Ar&thmet&c &nstr*ct&ons:

'ese instru$tions per+orm se*eral asi$ operations -addition, su tra$tion, di*ision,multipli$ation et$./ A+ter e e$ution, t'e result is stored in t'e +irst operand. ADD A, R1 - 'eresult o+ addition -A G1/ )ill e stored in t'e a$$umulator.

Ar&thmet&ca/ Instr*ct&ons

Mnemon&c Descr&(t&onByte

.*mber,sc&//ator

er&od

A A,Gn Add G Gegister to a$$umulator 1 1

A A,GAdd dire$tly addressed G Gegister to

a$$umulator 7 7

A A,%GiAdd indire$tly addressed Gegister to

a$$umulator 1 1

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31/71


A A,N Add num er to a$$umulator 7 7

A C A,Gn Add G Gegister )it' Carry it to a$$umulator 1 1

Branch Instr*ct&ons :

'ere are t)o &inds o+ t'ese instru$tions!

8ncond&t&ona/ 9*m( &nstr*ct&ons: A+ter t'eir e e$ution a 4ump to a ne) lo$ation +rom )'eret'e program $ontinues e e$ution is e e$uted.

Cond&t&ona/ 9*m( &nstr*ct&ons: I+ some $ondition is met # a 4ump is e e$uted. =t'er)ise, t'e program normally pro$eeds )it' t'e ne t instru$tion.

Branch Instr*ct&on

Mnemon&c Descr&(t&onByte

.*mber,sc&//ator

er&od

ACA;; adr11Call su routine lo$ated at address )it'in 7 5

yte Program Memory spa$e7 8@1.

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Alt'oug' *arious >8@1# ased systems 'a*e an A; +re uen$y o+ 18MHz,)e )ill$on$entrate on t'e A; +re uen$y o+ 11.8@ 7MHz.

'e reason e'ind su$' an odd num er 'as to do )it' t'e aud rate +or serial$ommuni$ation o+ t'e >8@1. A; R11.8@ 7MHz allo)s t'e >8@1 system to $ommuni$ate )it't'e PC )it' no errors.

imers $an also e used as $ounters $ounting e*ents 'appening outside t'e >8@1

('en it is used as a $ounter, it is a pulse outside o+ t'e >8@1 t'at in$rements t'e H, ;registers.

M= and H, ; registers are t'e same as +or t'e timer

'e C0 it in t'e M= registers de$ides t'e sour$e o+ t'e $lo$& +or t'e timer.

('en C0 R 1, t'e timer is used as a $ounter and gets its pulses +rom outside t'e >8@1.

'e $ounter $ounts up as pulses are +ed +rom pins 19 and 1@, t'ese pins are $alled 8-timer 8 input/ and 1 -timer 1 input/.

E>AM LE R,


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Nin$lude Oreg@1.'*oid 8 elay-*oid/*oid main -*oid/Q

)'ile -1/

QP1R8 @@

8 elay-/P1R8 AA

8 elay-/T

T*oid 8 elay- /Q

M= R8 81;8R8 88H8R8


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Nin$lude Oreg@1.'*oid 1M7 elay-*oid/s it my itRP7VJ*oid main-*oid/Q

unsigned $'ar )'ile -1/Q

my itR[my it1M7 elay-/

TT

*oid 1M7 elay-*oid/

Q M= R8 78H1R#1>9G1R1

)'ile - F1RR8/G1R8F1R8

T

E erc&ses1/ Find t'e *alue +or M= i+ )e )ant to program imer 8 in mode 7, use >8@1 A; +or

t'e $lo$& sour$e, and use instru$tions to start and stop t'e timer.

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7/ Assume t'at A; R 11.8@ 7 MHz. ('at *alue do )e need to load into t'e timer?s

registers i+ )e )ant to 'a*e a time delay o+ @ ms -millise$onds/D S'o) t'e program +or

imer 8 to $reate a pulse )idt' o+ @ ms on P7.8@1 C program to toggle all its o+ P2 $ontinuously e*ery @88 ms. se imer

1. mode 1 to $reate t'e delay.

J/ (rite an >8@1 C program to toggle only pin PI.@ $ontinuously e*ery 7@8 ms. se imer

8, mode 7 -># it auto#reload/ to $reate t'e delay.

>/ (rite an >8@1 C program to $reate a +re uen$y o+ 7@88 Hz on pin P7.J. se imer 1.

mode 7 to $reate t'e delay.

/ A s)it$' is $onne$ted to pin PI.7. (rite an >8@1 C program to monitor S( and $reate

t'e +ollo)ing +re uen$ies on pin PI.J!

S(R8! @88 Hz

S(R1! J@8 Hz se imer 8, mode 1 +or ot' o+ t'em.

18/ Assuming t'at $lo$& pulses are +ed into pin l, )rite a program +or $ounter 1 in mode 7

to $ount t'e pulses and display t'e state o+ t'e ;1 $ount on 4

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11/ Assume t'at a 1#Hz e ternal $lo$& is eing +ed into pin l -P# it auto reload/ to $ount up and display t'e state o+ t'e ;1 $ount

on PI. Start t'e $ount at =H.

17/ Assume t'at a 1#Hz e ternal $lo$& is eing +ed into pin = -P or more lines -)ire $ondu$tors/ are used to trans+er data to a de*i$e t'at is only a +e) +eeta)ay. " amples o+ parallel data trans+er are printers and 'ard dis&s ea$' uses $a les )it' many)ire strips. Alt'oug' in su$' $ases a lot o+ data $an e trans+erred in a s'ort amount o+ time yusing many )ires in parallel, t'e distan$e $annot e great. o trans+er to a de*i$e lo$ated manymeters a)ay, t'e serial met'od is used. In serial $ommuni$ation, t'e data is sent one it at a time,in $ontrast to parallel $ommuni$ation, in )'i$' t'e data is sent a yte or more at a time. Serial$ommuni$ation o+ t'e >8@1 is t'e topi$ o+ t'is $'apter. 'e >8@1 'as serial $ommuni$ation$apa ility uilt into it, t'ere y ma&ing possi le +ast data trans+er using only a +e) )ires.

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Ser&a/ ;ers*s ara//e/ Data Trans)er

I+ data is to e trans+erred on t'e telep'one line, it must e $on*erted +rom 8s and 1s toaudio tones, )'i$' are sinusoidal#s'aped signals. A perip'eral de*i$e $alled a modem, )'i$'stands +or Xmodulator0demodulatorY, per+orms t'is $on*ersion.

Serial data $ommuni$ation uses t)o met'ods, asyn$'ronous and syn$'ronous. 'esyn$'ronous met'od trans+ers a lo$& o+ data at a time, )'ile t'e asyn$'ronous met'od trans+ersa single yte at a time.

In data transmission i+ t'e data $an e transmitted and re$ei*ed, it is a dupletransmission. 'is is in $ontrast to simple transmissions su$' as )it' printers, in )'i$' t'e$omputer only sends data. uple transmissions $an e 'al+ or +ull duple , depending on)'et'er or not t'e data trans+er $an e simultaneous. I+ data is transmitted one )ay at a time, it isre+erred to as 'al+ duple . I+ t'e data $an go ot' )ays at t'e same time, it is +ull duple . =+

$ourse, +ull duple re uires t)o )ire $ondu$tors +or t'e data lines, one +or transmission and one+or re$eption, in order to trans+er and re$ei*e data simultaneously.

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S&m(/e 2a/)- and 1*//-D*(/e Trans)ers

Asynchrono*s ser&a/ comm*n&cat&on and data )ram&n''e data $oming in at t'e re$ei*ing end o+ t'e data line in a serial data trans+er is all 8s

and 1s it is di++i$ult to ma&e sense o+ t'e data unless t'e sender and re$ei*er agree on a set o+rules, a proto$ol, on 'o) t'e data is pa$&ed, 'o) many its $onstitute a $'ara$ter, and )'en t'edata egins and ends.

Start and sto( b&tsAsyn$'ronous serial data $ommuni$ation is )idely used +or $'ara$ter#oriented

transmissions, )'ile lo$oriented data trans+ers use t'e syn$'ronous met'od. In t'easyn$'ronous met'od, ea$' $'ara$ter is pla$ed et)een start and stop its. 'is is $alled framing.In t'e data +raming +or asyn$'ronous $ommuni$ations, t'e data, su$' as ASCII $'ara$ters, are

pa$&ed et)een a start it and a stop it. 'e start it is al)ays one it, ut t'e stop it $an eone or t)o its. 'e start it is al)ays a 8 -lo)/ and t'e stop it -s/ is 1 -'ig'/.

Data trans)er rate'e rate o+ data trans+er in serial data $ommuni$ation is stated in ps - its per se$ond/.

Anot'er )idely used terminology +or ps is aud rate. Ho)e*er, t'e aud and ps rates are notne$essarily e ual. 'is is due to t'e +a$t t'at aud rate is t'e modem terminology and is de+inedas t'e num er o+ signal $'anges per se$ond. In modems a single $'ange o+ signal, sometimestrans+ers se*eral its o+ data. As +ar as t'e $ondu$tor )ire is $on$erned, t'e aud rate and ps aret'e same, and +or t'is reason )e use t'e ps and aud inter$'angea ly.

'e data trans+er rate o+ gi*en $omputer system depends on $ommuni$ation portsin$orporated into t'at system. For e ample, t'e early IBMPC0 $ould trans+er data at t'e rateo+ 188 to 688 ps. In re$ent years, 'o)e*er, Pentium ased PCS trans+er data at rates as 'ig' as@65 ps. It must e noted t'at in asyn$'ronous serial data $ommuni$ation, t'e aud rate isgenerally limited to 188,888 ps.

RS4 4 Standardso allo) $ompati ility among data $ommuni$ation e uipment made y *arious

manu+a$turers, an inter+a$ing standard $alled GS7


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sin$e t'e standard )as set long e+ore t'e ad*ert o+ t'e ; logi$ +amily, its input and output*oltage le*els are not ; $ompati le. In GS7


48/71


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Mo ile! + !-"""# $%" , "#mail! em edded.$ourse%&restte$'nology.$om , (e ! ))).&restte$'nology.$om 9>


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DB- (&n connector

&n 1*nct&ons:

Pin es$ription

1 ata $arrier dete$t - C /

7 Ge$ei*ed data -G /

< ransmitted data - /

9 ata terminal ready- G/

@ Signal ground -:E /

6 ata set ready - SG/

J Ge uest to send -G S/

> Clear to send -C S/

Ging indi$ator -GI/

.ote: C , SG, G S and C S are a$ti*e lo) pins.

'e met'od used y GS#7D ! $arries data +rom " to t'e C".-----------------------------------------------------------------------------------------------------------------------------------------------------------------




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R>D ! $arries data +rom C" to t'e "S< ! signal ground

"3%! connect&on to RS4 4:

'e GS78@1 'as t)o pins t'at are used spe$i+i$ally +or trans+erring and re$ei*ingdata serially. 'ese t)o pins are $alled and G and a part o+ t'e port < group -P


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-a/ Inside MA 78@1 and MA 7


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"m edded

Controller

GB.

1B.

1B.

GB.7

8@1?s AG di*ides t'e ma$'ine $y$le +re uen$y o+ 71.6 &Hz y # it, auto#reload.

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SB81 @ser&a/ b*))er7 re'&ster

a yte o+ data to e trans+erred *ia t'e line must e pla$ed in t'e SB F register SB F 'olds t'e yte o+ data )'en it is re$ei*ed y t'e G line $an e a$$essed li&e any ot'er register

M=2 SB F,N? ? load SB FR99H, ASCII +or ? \

M=2 SB F,A $opy a$$umulator into SB FM=2 A,SB F $opy SB F into a$$umulator

)'en a yte is )ritten, it is +ramed )it' t'e start and stop its and trans+erred serially *iat'e pin

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55/71


)'en t'e its are re$ei*ed serially *ia G , it is de+rame y eliminating t'e stop and start its, ma&ing a yte out o+ t'e data re$ei*ed, and t'en pla$ing it in t'e SB F

SC,. @ser&a/ contro/7 re'&ster !

o program t'e start it, stop it, and data it

E am(/e (ro'rams

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Mo ile! + !-"""# $%" , "#mail! em edded.$ourse%&restte$'nology.$om , (e ! ))).&restte$'nology.$om @@


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E erc&ses

! (rite an >8@1 C program to send t)o di++erent strings to t'e serial port. Assuming t'at

S( is $onne$ted to pin P7.8, monitor its status and ma&e a de$ision as +ollo)s! S( R 8!

send your +irst name S( R 1! send your last name Assume A; R 11.8@ 7 MHz, aud

rate o+ 688, ># it data, 1 stop it.

4 Program t'e >8@1 to re$ei*e ytes o+ data serially, and put t'em in PI. Set t'e aud rate at

9>88, ># it data, and 1 stop it.

(rite a program to send t'e te t string 3Hello3 to Serial N1. Set t'e aud rate at 688, >#

it data, and 1 stop it.

$ Assume t'at a s)it$' is $onne$ted to pin P7.8.(rite a program to monitor t'e s)it$' and

per+orm t'e +ollo)ing!

I+ S( R 8 send t'e message 3Hello3 to t'e Serial N8 port.-----------------------------------------------------------------------------------------------------------------------------------------------------------------


Mo ile! + !-"""# $%" , "#mail! em edded.$ourse%&restte$'nology.$om , (e ! ))).&restte$'nology.$om @J


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I+ S( R 1 send t'e message 3:ood ye3 to t'e Serial N1 port.

% Assume t'at t'e >8@1 serial port is $onne$ted to t'e C=M port o+ t'e IBM PC, and on t'e

PC )e are using t'e Hyper erminal program to send and re$ei*e data serially. PI and P7

o+ t'e >8@1 are $onne$ted to ;" s and s)it$'es, respe$ti*ely. (rite an >8@1 program to

-a/ send to t'e PC t'e message 3(e Are Geady3, - / re$ei*e any data sent y t'e PC and

put it on ;" s $onne$ted to PI, and -$/ get data on s)it$'es $onne$ted to P7 and send it

to t'e PC serially. 'e program s'ould per+orm part -a/ on$e, ut parts - / and -$/

$ontinuously. se t'e 9>88 aud rate.

# Assume a s)it$' is $onne$ted to pin P;J. (rite a program to monitor its status and send

t)o messages to serial port $ontinuously as +ollo)s!

S(R8 send 3E=3

S(R1 send 3U"S3

Assume A; R 11.8@ 7 MHz, 688 aud, ># it data, and 1 stop it.

I.TERR8 TS

A single mi$ro$ontroller $an ser*e se*eral de*i$es. 'ere are t)o )ays to do t'at! IE "GG P Sor P=;;IE:.

,LLI.


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7. " ternal 'ard)areInterrupt 8

888< P8@1, ut manymanu+a$turersL data s'eets state t'at t'ere are si interrupts sin$e t'ey in$lude reset .t'e siinterrupts in t'e >8@1 are allo$ated as a o*e.

1. Geset. ('en t'e reset pin is a$ti*ated, t'e >8@1 4umps to address lo$ation 8888.t'is is t'e po)er#up reset.

7. )o interrupts are set aside +or t'e timers! one +or imer 8 and one +or imer 1.Memorylo$ation 888BH and 881BH in t'e interrupt *e$tor ta le elong to imer 8 and imer 1,respe$ti*ely.


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Eoti$e t'at a limited num er o+ ytes are set aside +or ea$' interrupt. For e ample, atotal o+ > ytes +rom lo$ation 888< to 888A is set aside +or IE 8, e ternal 'ard)are interrupt8.similarly,a total o+ > ytes +rom lo$ation 88BH to 8817H is reser*ed +or F8, imer 8 interrupt.I+ t'e ser*i$e routine +or a gi*en interrupt is s'ort enoug' to +it in t'e memory spa$e allo$ated toit, it is pla$ed in t'e *e$tor ta le ot'er)ise, and an ;ZMP instru$tion is pla$ed in t'e *e$tor ta leto point to t'e address o+ t'e ISG. In t'at rest o+ t'e ytes allo$ated to t'at interrupt are unused.

From t'e a o*e ta le also noti$e t'at only t'ree ytes o+ G=M spa$e are assigned tot'e reset pin. t'ey are G=M address lo$ation 8,1 and7.address lo$ation < elongs to e ternal'ard)are interrupt 8.+or t'is reason, in our program )e put t'e ;ZMP as t'e +irst instru$tion andredire$t t'e pro$essor a)ay +rom t'e interrupt *e$tor ta le, as s'o)n elo)

Ste(s &n e ec*t&n' an &nterr*(t

pon a$ti*ation o+ an interrupt, t'e mi$ro$ontroller goes t'roug' t'e +ollo)ing steps.

1. It +inis'es t'e instru$tion it is e e$uting and sa*es t'e address o+ t'e ne t instru$tion -PC/on t'e sta$&.

7. It also sa*es t'e $urrent status o+ all t'e interrupts internally -i.e., not on t'e sta$&/.


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Ste(s &n enab/&n' an &nterr*(t: o ena le an interrupt,

1. Bit J o+ t'e I" register -"A/ must e set to 'ig' to allo) t'e reset to ta&e e++e$t.I+ "AR1, interrupts are ena led and )ill e responded to i+ t'eir $orresponding it in I" are 'ig'.I+ "AR8, no interrupt )ill e responded to, e*en i+ t'e asso$iated it in t'e I" register is 'ig'.

Interr*(t Enab/e Re'&ster

"A I".J disa les all interrupts. I+ "AR8, no interrupts is a$&no)ledged. I+ "AR1, ea$' interrupt sour$e is indi*idually ena led disa led By setting or $learing its ena le it. ## I".6 Eot implemented, reser*ed +or +uture use.K" 7 I".@ "na les or disa les imer 7 o*er+lo) or $apture interrupt ->8@7

=nly/"S I".9 "na les or disa les t'e serial port interrupts.

" 1 I".< "na les or disa les imers 1 o*er+lo) interrupt

" 1 I".7 "na les or disa les e ternal interrupt 1.

" 8 I".1 "na les or disa les imer 8 o*er+lo) interrupt.

" 8 I".8 "na les or disa les e ternal interrupt.

Interr*(t r&or&ty Re'&ster

Wr&te a C (ro'ram that cont&n*o*s/y 'ets a s&n'/e b&t o) data )rom I andsends &t to / 3 5h&/e s&m*/taneo*s/y creat&n' a sF*are 5a;e o) 433 @as (er&od on (&n 4 %8se t&mer 3 to create the sF*are 5a;e-----------------------------------------------------------------------------------------------------------------------------------------------------------------




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Ass*me that >TAL !! 3% 4 M2G .

Wr&te a C (ro'ram that cont&n*o*s/y 'ets a s&n'/e b&t o) data )rom I and sends &t to / ,

&n the ma&n 5h&/e s&m*/taneo*s/y @a7 creat&n' a sF*are 5a;e o) 433 *s (er&od on (&n 4 %

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and @b7 send&n' /etter JAJ to the ser&a/ (ort 8se T&mer 3 to create the sF*are 5a;e Ass*me

that >TAL !! 3% 4 M2G 8se the #33 ba*d rate

E>AM LE R,


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! (rite a C program using interrupts to do t'e +ollo)ing!

1. Ge$ei*e data serially and send it to P=,7. Gead port PI, transmit data serially, and gi*e a $opy to P7,88.

4 (rite a C program using interrupts to do t'e +ollo)ing!

1. :enerate a 18888 Hz +re uen$y on P7.1 using = ># it auto#reload,7. se timer 1 as an e*ent $ounter to $ount up a 1#Hz pulse and display it on P=.

'e pulse is $onne$ted to " 1.

Assume t'at A; R 11.8@ 7 MHz. Set t'e aud rate at 688.

Assume t'at t'e IE 1 pin is $onne$ted to a s)it$' t'at is normally 'ig'. ('ene*er itgoes lo), it s'ould turn on an ;" . 'e ;" is $onne$ted to PI .< and is normally o++.

('en it is turned on it s'ould stay on +or a +ra$tion o+ a se$ond. As long as t'e s)it$' is pressed lo), t'e ;" s'ould stay on.

$ (rite a program in )'i$' t'e >8@1 reads data +rom PI and )rites it to P7 $ontinuously)'ile gi*ing a $opy o+ it to t'e serial C=M port to e trans+erred serially. Assume t'at

A; R 11.8@ 7 MHz. Set t'e aud rate at 688.% (rite a program using interrupts to do t'e +ollo)ing!

1. Ge$ei*e data serially and send it to P=,7. Ha*e port PI read and transmitted serially, and a $opy gi*en to P7,88.

# (rite a C program using interrupts to do t'e +ollo)ing!

1. :enerate a 18888 Hz +re uen$y on P7.1 using = ># it auto#reload,7. se timer 1 as an e*ent $ounter to $ount up a 1#Hz pulse and display it on P=.

'e pulse is $onne$ted to " 1.

Assume t'at A; R 11.8@ 7 MHz. Set t'e aud rate at 688.

LCD @L&F*&d Crysta/ D&s(/ay7

;i uid $rystal displays -;C s/ 'a*e materials )'i$' $om ine t'e properties o+ ot'

li uids and $rystals. Gat'er t'an 'a*ing a melting point, t'ey 'a*e a temperature range )it'in

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)'i$' t'e mole$ules are almost as mo ile as t'ey )ould e in a li uid, ut are grouped toget'er

in an ordered +orm similar to a $rystal.

An ;C $onsists o+ t)o glass panels, )it' t'e li uid $rystal material sand )it$'ed in

et)een t'em. 'e inner sur+a$e o+ t'e glass plates are $oated )it' transparent ele$trodes )'i$'

de+ine t'e $'ara$ter, sym ols or patterns to e displayed polymeri$ layers are present in et)een

t'e ele$trodes and t'e li uid $rystal, )'i$' ma&es t'e li uid $rystal mole$ules to maintain a

de+ined orientation angle.

=ne ea$' polarisers are pasted outside t'e t)o glass panels. 'ese polarisers )ould rotate

t'e lig't rays passing t'roug' t'em to a de+inite angle, in a parti$ular dire$tion

('en t'e ;C is in t'e o++ state, lig't rays are rotated y t'e t)o polarisers and t'e

li uid $rystal, su$' t'at t'e lig't rays $ome out o+ t'e ;C )it'out any orientation, and 'en$e t'e

;C appears transparent.

('en su++i$ient *oltage is applied to t'e ele$trodes, t'e li uid $rystal mole$ules )ould

e aligned in a spe$i+i$ dire$tion. 'e lig't rays passing t'roug' t'e ;C )ould e rotated y t'e

polarisers, )'i$' )ould result in a$ti*ating 0 'ig'lig'ting t'e desired $'ara$ters.

'e ;C Ls are lig't)eig't )it' only a +e) millimeters t'i$&ness. Sin$e t'e ;C Ls

$onsume less po)er, t'ey are $ompati le )it' lo) po)er ele$troni$ $ir$uits, and $an e po)ered

+or long durations.

'e ;C s )onLt generate lig't and so lig't is needed to read t'e display. By using

a$&lig'ting, reading is possi le in t'e dar&. 'e ;C Ls 'a*e long li+e and a )ide operating

temperature range.

C'anging t'e display size or t'e layout size is relati*ely simple )'i$' ma&es t'e ;C Ls

more $ustomer +riendly.

'e ;C s used e $lusi*ely in )at$'es, $al$ulators and measuring instruments is t'e

simple se*en#segment displays, 'a*ing a limited amount o+ numeri$ data. 'e re$ent ad*an$es in

te$'nology 'a*e resulted in etter legi ility, more in+ormation displaying $apa ility and a )ider

temperature range. 'ese 'a*e resulted in t'e ;C s eing e tensi*ely used in

tele$ommuni$ations and entertainment ele$troni$s. 'e ;C s 'as e*en started repla$ing t'e

$at'ode ray tu es -CG s/ used +or t'e display o+ te t and grap'i$s, and also in small 2

appli$ations.

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LCD o(erat&on

In re$ent years t'e ;C is +inding )idespread use repla$ing ;" s -se*en#segment ;" or ot'er

multi segment ;" s/. 'is is due to t'e +ollo)ing reasons!

1. 'e de$lining pri$es o+ ;C s.

7. 'e a ility to display num ers, $'ara$ters and grap'i$s. 'is is in

$ontra$t to ;" s, )'i$' are limited to num ers and a +e) $'ara$ters.


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&n descr&(t&on )or LCD:

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Mo ile! + !-"""# $%" , "#mail! em edded.$ourse%&restte$'nology.$om , (e ! ))).&restte$'nology.$om 6>


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LCD Command Codes

Code

@he 7 Command to LCD Instr*ct&on Re'&ster

1 Clear display s$reen

7 Geturn 'ome

9 e$rement $ursor

6 In$rement $ursor

@ S'i+t display rig't

J S'i+t display le+t

> isplay o++, $ursor o++

A isplay o++, $ursor on

C isplay on, $ursor o++

" isplay on, $ursor on

F isplay on, $ursor lin&ing

18 S'i+t $ursor position to le+t

19 S'i+t $ursor position to rig't

1> S'i+t t'e entire display to t'e le+t

1C S'i+t t'e entire display to t'e rig't

>8 For$e $ursor to eginning o+ 1 st line

C8 For$e $ursor to eginning o+ 7 nd line

7 lines and @ J matri

8ses:

'e ;C s used e $lusi*ely in )at$'es, $al$ulators and measuring instruments are

t'e simple se*en#segment displays, 'a*ing a limited amount o+ numeri$ data. 'e re$ent

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Mo ile! + !-"""# $%" , "#mail! em edded.$ourse%&restte$'nology.$om , (e ! ))).&restte$'nology.$om J8


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micro controler 8051

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