Memory Selector Devices

An Chen

2014 AVS TFUG Seminar

Outline

• Emerging memories and crossbar array architecture

• Memory selector device options and requirements

Asymmetry and nonlinearity for device selection

Selector device requirements

• Crossbar array modeling with selector device

Crossbar array model and parameters

Impact of selectors on crossbar array operations

A case study: 4kb crossbar array with nonlinear selectors

• Summary

2

Emerging Memory Taxonomy

3

Memory

Volatile

SRAM

DRAM

Stand-alone

Embedded

Nonvolatile

Baseline

Flash

NOR

NAND

Prototypical

FeRAM

PCM

MRAM

STT-RAM

Emerging

Ferroelectric Memory

FeFET

FTJ

ReRAM

Electrochemical Metallization Bridge

Metal Oxide - Bipolar Filamentary

Metal Oxide - Unipolar Filamentary

Metal Oxide - Bipolar Nonfilamentary

Mott Memory

Carbon Memory

Macromolecular Memory

Molecular Memory

Two

terminal

structures

4F2 footprint

Crossbar Array and Sneak Paths

Vdd

Vout

RS (sensing resistor)

Rj

Selected path

One sneak path Bitlines

Vertical Crossbar Array and Sneak Paths

5

BL1

BL2

BL3

BL4

WL1

WL3

WL2

WL4

Selected path: WL1 BL4

via junctions: 4

Sneak path 1 (dashed):

WL1 BL3 WL3 BL4

via junctions: 3, 11, 12

Sneak path 1 (dotted):

WL1 BL2 WL2 BL4

via junctions: 2, 6, 8

1

2

3

4

5

6

7

8

9

10

11

12 WL2 WL1 WL4 WL3

Layer 1 Layer 2

4

3

2

1

8

7

6

5

16

15

14

13

12

11

10

9

Sensing Margin (SM) Vdd

Vout

Rj

Rn

Rmn

Rm

WL(1)

WL(2)

WL(3)

WL(m)

BL(1) BL(2) BL(3) BL(n)……

Selected device

RS (sensing resistor)

(Share WL with Rj)

(Share BL with Rj)

(Share no

lines with Rj)

If access resistance and line

resistance are ignored, crossbar

arrays can be simplified

Vdd

RS

Rj

Rm Rmn

Rn

Vout

sWL

uWL

sBL uBL

Vdd Vout

Rj

Rn Rmn Rm

RS

Vout

Rj=Ron

Rj=Roff

Vout

Unselected

BLs Unselected

WLs

Writing Voltage Margin (WVM)

Vdd

Rj

disturbance voltage decay

WVM =

V(selected device) – max. V(unselected devices)

• Location affect voltage

• Line resistance cause voltage decay

Vdd

Vdd/2

Vdd/2

Vdd/2

Vdd/2 Vdd/2 Vdd/2 0

Vdd/2

Vdd

0

Vdd

Vdd/3

Vdd/3

Vdd/3

2Vdd/3 2Vdd/3 2Vdd/3 0

-Vdd/3

Vdd/3

Vdd

1/2 bias scheme

1/3 bias scheme

Outline

• Emerging memories and crossbar array architecture

• Memory selector device options and requirements

Asymmetry/nonlinearity for device selection

Selector device performance requirements

• Crossbar array modeling with selector device

Crossbar array model and parameters

Impact of selectors on crossbar array operations

A case study: 4kb crossbar array with nonlinear selectors

• Summary

8

Asymmetry/Nonlinearity for Device Selection

Features of sneak paths:

• There is always a reverse

conduction segment

• Unselected devices typically

have lower voltage than the

selected device

• Asymmetry (reverse resistance >> forward resistance) sneak path resistance

is increased by reverse resistance

• Nonlinearity (voltage-dependent resistance) unselected devices with lower

voltage are more resistive and reduce leakage through leakage paths ……

R(i,j)

R(i,1) R(1,j)R(1,1)

R(i,2) R(1,j)R(1,2)

R(i,n) R(m,j)R(m,n)

(n-1

)(m

-1)

par

alle

l p

ath

s

WLi BLj

BL1

BL2

BLn

WL1

WL1

WLm

……

……

Selector Device Options

Asymmetry Nonlinearity

Memory Selector Devices

Transistor

Planar

Vertical

Diodes

Si diodes

Oxide/oxide heterojunctions

Metal/oxide Schottky junctions

Self-rectification

Volatile switch

Threshold switch

Mott switch

Nonlinear devices

External nonlinear select devices

MIEC

Complementary structures

Intrinsic nonlinearity

Nonlinear Bidirectional Diode Selector

11

Panasonic: ISSCC 25.6 (2012)

Oxide Heterojunction Selector

12

Forward current: NiO/TiO < NiO/ZnO < NiO/InZnO < CuO/InZnO

105 A/cm2

Cell size: 0.5m 0.5m

1mA

1mA

1010 nm2 size with J = 1MA/cm2 I = 1A

RC effect

Samsung: IEDM 771 (2007)

Volatile Threshold Switch Selectors

13

AsTeGeSi switch

Samsung: IEDM 2.6.1 (2012)

APL 100, 123505 (2012)

Si-As-Te switch

VLSI Tech (2012)

NbO2-x switch

MIEC: Mixed Ionic Electronic Conduction

14

<30nm size >108 endurance

Local stoichiometry

As-fabricated After-cycling

Structure I-V characteristics

IBM: VLSIT (2010), VLSIT 94 (2011), IEDM, 36 (2012)

Selector Device Parameters and Requirements

Parameters Requirements

On/off ratio (or

rectification ratio,

nonlinearity ratio)

Sufficiently high for given memory element

characteristics and array size

Maximum on-current Sufficiently high for memory operation

Threshold voltage Needs to be minimized

Scalability

Comparable with memory elements Operation polarity

Speed

Endurance

Manufacturability Compatible with memory and CMOS

processing

Examples of Reported Oxide Diodes

Ref: Adv. Mater. 19, 73 (2007); IEDM 771 (2007); Adv. Mater. 15, 1409 (2003); Nanotech. 21, 1 (2010); APL 92, 162904 (2008); VLSI

Tech. 24 (2009); APL 94, 082905 (2009); APL 96, 262901 (2010).

1.0E-6

1.0E-4

1.0E-2

1.0E+0

1.0E+2

1.0E+4

1.0E+6

1.0E-10 1.0E-6 1.0E-2 1.0E+2

r = 1 r = 104

r = 108

1MA/cm2

p-CuOx/n-InZnOx poly-Si p-n

ITO/TiO2/Pt Pt/TiO2/Ti

p-NiOx/n-TiOx

p-ZnO.Rh2O3/n-InGaZnO4

Reverse J (A/cm2)

Fo

rwar

d J

(A

/cm

2)

Ti/TiO2/Pt

Pt/TiO2/Pt

(a)

1.0E-6

1.0E-4

1.0E-2

1.0E+0

1.0E+2

1.0E+4

1.0E+6

1.0E-10 1.0E-6 1.0E-2 1.0E+2

r = 1 r = 104

r = 108

1MA/cm2

Reverse J (A/cm2)

Fo

rwar

d J

(A

/cm

2) p-CuOx/n-InZnOx

poly-Si p-n

ITO/TiO2/Pt

Pt/TiO2/Ti

p-NiOx/n-TiOx

p-ZnO.Rh2O3/n-InGaZnO4

Ti/TiO2/Pt

Pt/TiO2/Pt

(b)

Current density at 1V Current density at 0.5V

Selector-Memory Parameter Balance

Threshold switch parameters:

Vhold, Vth, RL, RH

RRAM parameters:

Vset, Vreset, Ron, Roff

Adv. Mater. 19, 3919 (2007)

Volatile switch

selector

RRAM

RL

RH

RRAM

RON

Vhold Vth

1

2

I

V

Balanced

parameters

RON

Vhold Vth

RL

RH

2

1

V

I Unbalanced

parameters

Outline

• Emerging memories and crossbar array architecture

• Memory selector device options and requirements

Asymmetry/nonlinearity for device selection

Selector device performance requirements

• Crossbar array modeling with selector device

Crossbar array model and parameters

Impact of selectors on crossbar array operations

A case study: 4kb crossbar array with nonlinear selectors

• Summary

18

A Crossbar Array Model and Solution

RBL

RWL

RS_BL1

RS_BL2

RS_WL1 RS_WL2

{VAPP_BL1}

{VAPP_BL2}

{V

AP

P_W

L1}

{V

AP

P_W

L2 }

IEEE TED 60, 1318 (2013)

Crossbar Array Parameters

Memory element

• Switching I, V

• RLRS, RHRS, on/off ratio

• Variation

Array parameters

• Size (mn)

• Line resistance

• Single- or dual-bias

Selector devices

• Nonlinearity

• Asymmetry

• Contact resistance

Array operation

• Supply voltage (Vdd)

• Sensing/bias schemes

• Parallel access

Distinguishable on/off states

Sufficient writing V/I without disturbance

Efficient operations

Technology Design

Sensing margin

Writing voltage margin

Power efficiency

Nonlinear and Rectifying Selectors

21

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

-2 -1 0 1 2-2 -1 0 1 2 Voltage (V)

Curr

ent

(A)

10-2

10-4

10-6

10-8

10-10

Oxide diode

IEDM (2007)

1E+0

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

-2 -1 0 1 2Voltage (V)

-2 -1 0 1 2

Res

ista

nce

(k

) 106

104

102

100

Contact

resistance

RC effect

I(V) = I0[exp(qV/nkT)-1]

p-CuOx /

n-InZnOx

1E-01

1E+00

1E+01

1E+02

1E+03

1E+04

1E+05

1E+06

-2 -1 0 1 2Voltage (V)

Curr

ent

den

sity

(A

/cm

2)

1E+0

1E+1

1E+2

1E+3

1E+4

1E+5

-2 -1 0 1 2

Voltage (V)

-2 -1 0 1 2

104

102

100

Res

ista

nce

(k

)

J(V) = J0sinh(V)

J0 = 5 A/cm2

= 5.8 V-1

Bidirectional diode

TaN/SiNx/TaN

ISSCC 25.6 (2012)

Device area:

(0.38 m)2

-2 -1 0 1 2

106

105

104

103

102

101

100

10-1

• A typical nonlinear characteristics is from tunneling transport mechanisms

• Rectifying selectors can be p-n junction, heterojunction, or Schottky diode

• I-V characteristics well described by hyperbolic or exponential functions

• Maximum current may be limited by contact resistance

Line Resistance Induced Voltage Decay

22

BLBLWLWLddRj RIRIVV

0%

20%

40%

60%

80%

100%

1 10 100 1000

"1/2 bias" scheme

"1/3 bias" scheme

unsel. WL/BL grounded

RL = 0.01

RL = 0.1

RL = 1

RL = 10

Number of junctions along a line

(Vo

ltag

e at

ju

nct

ion

)/V

dd

“1/3 bias”: V drops to 2Vdd/3

“1/2 bias”: V drops to Vdd/2

“ground”: V drops to 0

Vdd

Sneak current

Rj

Selected WL

Selector Reduces Voltage Degradation

23

• Integrating nonlinear selector devices significantly reduces line

resistance induced voltage decay

0%

20%

40%

60%

80%

100%

1 10 100 1000

1R

1S1R

"1/2 bias" scheme

"1/3 bias" scheme

Unsel. WL/BL grounded

bidirectional nonlinear

diode selector

RL = 1

Number of junctions along a line

(Volt

age

at j

unct

ion)/

Vdd

1S1R

1R

Sneak Leakage Reversal with Partial Bias

24

1E-2

1E-1

1E+0

1E+1

1E+2

10 100 100010 100 1000Number of junctions

Juncti

on c

urr

ent (

A) 102

101

100

10-1

10-2

Ground unsel. WL/BL

“1/2 bias” scheme

How far Vdd can reach

in “1/2 bias” scheme

RL = 1

Junction

leakage

reverse

direction

Vdd

Vdd/2 Vdd/2 Vdd/2 Vdd/2

Voltage drive from Vdd

can only reach junction k

Rj

BL(k+1) … BL (n-1)

help to pull up Rj voltage

Sneak current flow

WL BL

Sneak current flow

BL WL1 2 k k+1 n • With selected VWL = Vdd and

selected VBL = 0, sneak path

leakage is usually WL BL

• Reverse leakage

occurs in partial

bias schemes

• After reversal, the

device at the end of

WL is driven by

partial biased BLs

instead of VWL

Selector Reduces Leakage and Line Current

25

1E-2

1E+0

1E+2

1E+4

1 10 100 1000

1R

1S1R

"1/2 bias" scheme

"1/3 bias" scheme

Ground unsel. WL/BL

1 10 100 1000

Junction number along selected WL

Curr

ent

along s

elec

ted W

L (

A)

104

102

100

10-2

1E+0

1E+2

1E+4

1E+6

1 2 3Ground “1/3 bias” “1/2 bias”Bias of unsel. WLs/BLs

I WL(B

L1

)

I WL(B

L1

02

4)

106

104

102

100

1R

1S1R

RL = 1

• Selector devices reduce both the sneak leakage through unselected

junctions and the access line current

Writing Voltage Margin of a 4kb Array

26

0

50

100

150

200

0 1 2

Cu

rren

t (

A)

Voltage (V)

VS

0 1.0 2.0

200

150

100

50

0

VR

LRS

HRS

Selector

• Selectors helps to maintain nearly constant junction voltage margin

• However, only a portion of junction voltage drops on the memory

element

0%

20%

40%

60%

80%

100%

1E-6 1E-5 1E-4 1E-3

1RSelected

junction

voltage

Maximum unselected

junction voltage

WVM

0%

20%

40%

60%

80%

100%

1E-6 1E-5 1E-4 1E-3

1R

Selected

junction

voltage

Maximum unselected

junction voltage

1S1R

1R

Selected

junction

voltage

Maximum unselected

junction voltage

1S1R

0%

20%

40%

60%

80%

100%

1E-6 1E-5 1E-4 1E-3

Selected

Max. unselected

VR in 1S1R

V1S1R

100%

80%

60%

40%

20%

0%

Vo

lta

ge

/ V

dd

10-2 10-1 100 101

Bit-to-bit line resistance, RL ()

Effect of Selector Properties

27

0%

10%

20%

30%

40%

2.0 4.0 6.0 8.0 10.0

(1/V)

Devic

e v

olt

age / V

dd Selected

device

Unselected device,

maximum

Writing voltage

margin (WVM)

1S1R

0%

5%

10%

15%

20%

1E-2 1E-1 1E+0102 103 104

Contact resistance, RC ()

20%

15%

10%

5%

0%

Dev

ice

vo

ltag

e /

Vd

d

Selected device voltage

Max. voltage

of unselected

devices

Writing

margin

• Higher exponential factor of selectors

(stronger nonlinearity) improves writing

voltages and margin

• Contact resistance reduce writing voltages

and margin 1E-01

1E+01

1E+03

1E+05

-2 -1 0 1 2

Voltage (V)

Res

ista

nce

(k

)

Sensing Margin of a 4kb Array

0%

2%

4%

6%

8%

10%

1E-6 1E-5 1E-4 1E-3

0%

2%

4%

6%

8%

10%

1E-6 1E-5 1E-4 1E-3

Vout (LRS)

Vout (HRS)

Sensing margin

1S1R

10-2 10-1 100 101 10-2 10-1 100 101

Line resistance RL ()

Vout (LRS)

Vout (HRS) (a) (b)

10%

8%

6%

4%

2%

0%

1R

Sen

sin

g m

arg

in

Normal Probability Plot

Vout

0.01 0.02 0.03 0.04 0.05

-2

-1.5

-1

-0.5

0

0.5

1

1.5

297.7%

84.1%

50.0%

15.9%

2.28%

Sensing voltage / Vdd

1% 2% 3% 4% 5%

Acc

um

ula

tive

pro

bab

ilit

y

■ LRS

□ HRS

Sensing

margin

RL = 10 1R

1S1R

• Worst-scenario sensing margin

is nearly zero without selector

• Selector greatly improves the

sensing margin

• Analytical solutions ignoring

line resistance and selector I-V

may over-estimate sensing

margin

Symp. VLSI Tech. 37 (2012)

Summary

• Two terminal selector with good scalability is essential for high-density crossbar memory arrays.

• Nonlinearity and asymmetry in device characteristics can enable device selection functions. Rectifying diodes, volatile switches, and nonlinear devices can be used as selectors.

• Selectors reduce sneak leakage and voltage/current decay, which helps to ensure sufficient operating voltage/current.

• Voltage dividing effect of selectors reduce disturbance but also requires higher array Vdd for CBA operation.

• Selectors with stronger exponential dependence are more effective in improving operation margins.

• CBA design and optimization have to consider the balance between memory elements and selector devices.

29