memory segmentation of intel 8086 -...

Digital Logic Design Ch1-1

Memory Segmentation of Intel 8086

Dr. M. Hebaishy


Memory Segmentation

The total memory size is divided into segments of various sizes.

A segment is just an area in memory.

The process of dividing memory this way is called Segmentation.

In memory, data is stored as bytes.

Each byte has a specific address.

Intel 8086 has 20 lines address bus.

With 20 address lines, the memory that can be addressed is 220 bytes.

220 = 1,048,576 bytes (1 MB).

8086 can access memory with address ranging from 00000 H to FFFFF H.


In 8086, memory has four different types of segments.

These are:

» Code Segment

» Data Segment

» Stack Segment

» Extra Segment

Each of these segments are addressed by an address stored in corresponding segment

register.

These registers are 16-bit in size.

Each register stores the base address (starting address) of the corresponding segment.

Because the segment registers cannot store 20 bits, they only store the upper 16 bits.


How is a 20-bit address obtained if there are only 16-bit registers?

The answer lies in the next few slides.

The 20-bit address of a byte is called its Physical Address.

But, it is specified as a Logical Address.

Logical address is in the form of:

Base Address : Offset

Offset is the displacement of the memory location from the starting location of

the segment.

Example

The value of Data Segment Register (DS) is 2222 H.

To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSBs of the address.

After appending, the starting address of the Data Segment becomes 22220H.


If the data at any location has a logical address specified as:

2222 H : 0016 H

Then, the number 0016 H is the offset.

2222 H is the value of DS.

To calculate the effective address of the memory, BIU uses the following formula:

Effective Address = Starting Address of Segment + Offset

To find the starting address of the segment, BIU appends the contents of Segment

Register with 0H. Then, it adds offset to it.

Therefore: EA = 22220 H

+ 0016 H

22236 H


BYTE – 0

BYTE – 1

BYTE – 2

- - - - -

Addressed Byte

2222 H

DS Register

22220 H

Offset = 0016 H

22236 H


Max. Size of Segment

All offsets are limited to 16-bits.

It means that the maximum size possible for segment is 216 = 65,535 bytes (64

KB).

The offset of the first location within the segment is 0000 H.

The offset of the last location in the segment is FFFF H.

Where to Look for the Offset

Segment Offset Registers Function

CS IP Address of the next instruction

DS BX, DI, SI Address of data

SS SP, BP Address in the stack

ES BX, DI, SI Address of destination data (for string operations)


The contents of the following registers are:

CS = 1111 H

DS = 3333 H

SS = 2526 H

IP = 1232 H

SP = 1100 H

DI = 0020 H

Calculate the corresponding physical addresses for the address bytes

in CS, DS and SS.

Quiz


1. CS = 1111 H

The base address of the code segment is 11110 H.

Effective address of memory is given by 11110H + 1232H = 12342H.

2. DS = 3333 H

The base address of the data segment is 33330 H.

Effective address of memory is given by 33330H + 0020H = 33350H.

3. SS = 2526 H

The base address of the stack segment is 25260 H.

Effective address of memory is given by 25260H + 1100H = 26350H

Solution


What are the characteristic features of a RAM?

The essential features of a RAM are:

1. It is volatile in nature—i.e., when the power is switched off, data stored at the

different memory locations are totally lost.

2. When data/instruction is written at a memory location, previous data stored at this location is

destroyed and replaced by the new data.

3. When data/instruction is read from an address location, the existing data is not lost (destroyed).

What are bit and byte organized memories?

For a 2n × m memory, where n is the number of address lines such that a maximum of 2n memory

locations can be accessed and m is the word length, if m is 1 then the memory is said to be bit

organized, whereas if m is 8, then the memory is said to be byte organized.

Explain how the entire addressable memory space of 8085 can be conceived of the pages of a book?

The entire addressable memory space is 216 = 65,536 lines, because 8085 has 16 address lines. This

is arbitrarily divided into 256 pages (0 to 255 pages) with each page consisting of 256 lines (0 to

255 lines), as shown in Fig.


Arranging total memory space of 8085 into pages and lines


The sixteen address lines can be divided into higher (A15 – A8) and lower (A7 – A0) eight bits. On each

page there are 256 lines defined by the lower byte (A7 – A0), while each page of the book is defined by

the different combinations of the upper byte (A15 – A8).

The following figure shows an arbitrary but convenient way of showing the total memory space, with

each block consisting of 4 K lines i.e., 16 pages.


What is usually meant by the speed of a memory?

Usually, the term ‘speed of a memory’ is meant the time needed to access the memory. This is

also known as ‘access time’.

Mention the address capability of 8086 and also show its memory map.

8086, via its 20-bit address bus, can address 220 = 1,048,576 or 1 MB of different memory

locations. Thus the memory space of 8086 can be thought of as consisting of 1,048,576 bytes or

524,288 words. The memory map of 8086 is shown in Fig. where the whole memory space

starting from 00000 H to FFFFF H is divided into 16 blocks—each one consisting of 64 KB. This

division is arbitrary but at the same time a convenient one—because the most significant hex digit

increases by 1 with each additional block. Thus, 30000 H memory location is 65,536 bytes higher

in memory than the memory location 20000 H.

The lower and upper ends of the memory map are shown separately—earmarking some spaces as

reserved and some as ‘dedicated’. The reserved locations are meant for future hardware and

software needs while the dedicated locations are used for processing of specific system interrupts

and reset functions.

Digital Logic Design Ch1-15 Memory map for the 8086 microprocessor. Some memory locations are dedicated or reserved.


Discuss logical address, base segment address and physical address.

The logical address, also goes by the name of effective address or offset address (also known as

offset), is contained in the 16-bit IP, BP, SP, BX, SI or DI.

The 16-bit content of one of the four segment registers (CS, DS, ES, SS) is known as the base

segment address.

Offset and base segment addresses are combined to form a 20-bit physical address (also called

real address) that is used to access the memory. This 20-bit physical address is put on the address

bus (AD19 – AD0) by the BIU.

Describe how the 20-bit physical address is generated.

The 20-bit physical (real) address is generated by combining the offset (residing in IP, BP, SP,

BX, SI or DI) and the content of one of the segment registers CS, DS, ES or SS. The process of

combination is as follows:

The content of the segment register is internally appended with 0 H (0000 H) on its right most end

to form a 20-bit memory address—this 20-bit address points to the start of the segment. The offset

is then added to the above to get the physical address.

Fig. shows pictorially the actual process of generating a 20-bit physical address.

Thus, Physical Address = Segment Register content 16 D + Offset.


Physical address generation


Although 8086 is a 16-bit μP, it deals with 8-bit memory. Why?

This is so for the following two reasons:

» It enables the microprocessor to work with both on bytes and words. This is very important

because many I/O devices such as printers, terminals, modems etc, transfer ASCII coded data

(7 or 8 bits).

» Quite a few of the operation codes of 8086 are single bytes while so many other instructions

are there which vary from 2 to 7 bytes. By working with byte-width memory, these varied

opcodes can easily be handled.

What is the maximum size of the memory that can be accessed by 8086?

The two status codes S4 and S3 together point to the segment register used for 20-bit physical

address generation and can be examined by external circuitry to enable separate 1 MB address

space for each of CS, ES, DS, and SS. This would enable memory address to be expanded to a

maximum of 4MB for 8086 μP.


Addressing Modes of 8086


What is meant by addressing mode?

An instruction consists of an opcode and an operand. The operand may reside

in the accumulator, or in a general purpose register or in a memory location.

The manner in which an operand is specified (or referred to) in an instruction is

called addressing mode.

To perform any operation, we have to give the corresponding instructions to

the microprocessor.

In each instruction, programmer has to specify 3 things:

Operation to be performed.

Address of source of data.

Address of destination of result.

The method by which the address of source of data or the address of destination of

result is given in the instruction is called Addressing Modes.

The term addressing mode refers to the way in which the operand of the instruction

is specified.


Different addressing modes of 8086.

The following are the different addressing modes of 8086:

» Register operand addressing.

» Immediate operand addressing.

» Memory operand addressing.

The different memory addressing modes.

The different memory addressing modes are:

» Direct Addressing

» Register Indirect Addressing

» Based Addressing

» Indexed Addressing

» Based Indexed Addressing and

» Based Indexed with displacement.

Types of Addressing Modes


How the physical address is generated for the different memory addressing

modes?

Physical address (for the operand) is the address from which either a read or write operation is

initiated. The following shows the manner of generation of physical address.

Physical address = Segment base : Effective address

= Segment base : Base + Index + Displacement

i.e., effective address, for its generation, can have as many as three elements: Base, Index and

Displacement. Thus the effective address is generated from the following:

Effective address = Base + Index + Displacement

The segment registers can be CS, SS, DS or ES. Base can be BX or PB. Index can be SI or DI and

the Displacement can either be 8-bit or 16-bit.

It should be noted that not all the three elements viz., base, index or displacement are always used

for effective address calculations.


Give examples each of (a) Register Addressing mode (b) Immediate Addressing mode.

(a) Register Addressing Mode.

In this mode, either an 8-bit or a 16-bit general purpose register contains the operand.

Some examples are:

MOV AX, BX

MOV CX, DX

ADD AL, DH

ADD DX, CX

The content of BX register is moved to AX register in the first example, while in the third example,

content of DH is added to the content of AL. Here, source and destination of data are CPU registers.

(b) Immediate Addressing Mode.

In this mode, the operand is contained in the instruction itself, i.e., the operand forms a part of the

instruction itself. The operand can be either 8-bit or 16-bit in length.

Some examples are:

MOV AL, 83 H

ADD AX, 1284 H

In the first example, 83 H is moved to AL register while in the second example, 1284 H is added to the

contents of AX register. Here, source of data is within the instruction.


Discuss the Direct Addressing Mode.

In a way it is similar to ‘Immediate Addressing Mode’. In Immediate Addressing Mode,

data follows the instruction opcode, while in this case an effective address follows the

same. Thus in this case:

PA = Segment base : Direct address.

By default, the segment base register is DS. Thus,

PA = DS : EA

But if a segment override prefix (SEG) is used in the instruction, then any one of the

four segment registers can be referenced. Hence, in general,

As an example, MOV CX, [ALPHA]

It means, “move the contents of the memory location, which is labelled as

ALPHA in the current data segment, into register CX”.


Thus, if DS = 0300 H, and value assigned to ALPHA is 3216 H, then

PA = 03000 H + 3216 H = 06216 H

Thus, data contained in address locations 06217 H and 06216 H will

be stored in CH and CL registers respectively.

MOV [0404 H], CX would move the contents of CL to offset address

0404 H (relative to data segment register DS) and CH to 0405 H.

Here, memory address is supplied within the instruction.


Draw and explain the memory mapped I/O scheme for 8086.?

In this scheme, CPU looks to I/O ports as if it is part of memory. Some of the memory space is

earmarked (dedicated) for I/O ports or addresses. The memory mapped I/O

scheme is shown in Fig. below in which the memory locations starting from

C0000 H to C0FFF H (4 KB in all) and from D0000 H to D0FFF H (4 KB in

all) are assigned to I/O devices.


Give the characteristics of Memory mapped I/O?

Execution speed

Data transfer

Device address

What is SIM?

SIM: Set interrupt Mask. It is a 1-byte instruction. Used for three functions

a. To set the Mask

b. To reset the flip flop

c. Implement the I/O

What is RIM?

RIM: Read Interrupt Mask Used for three functions

a. To read interrupt mask

b. To identify the pending interrupt

c. To receive serial data


Input/Output Interface of

8086


What kind of I/O is used for IN and OUT instructions?

For 8086 based systems, isolated I/O is used with IN and OUT instructions.

The IN and OUT instructions are of two types: direct I/O instructions and

variable I/O instructions.

The different types of instructions are tabulated in Fig:

Which register(s) is/are involved in data transfers?

Only AL (for 8-bits) or AX (for16-bits) register is involved in data transfer

involving the 8086’s CPU and I/O devices—thus they are also known as

accumulator I/O.


Bring out the differences between direct I/O instructions and

variable I/O Instructions.

Differences between direct and variable I/O instructions:


Give one example each of (a) direct I/O (b) variable I/O instruction.?

(a) An example of direct I/O instruction is as follows:

IN AL, 0F2 H

On execution, the contents of the byte wide I/O port at address location F2 H

will be put into AL register.

(b) An example of this type is:

MOV DX, 0C00F H

IN AL, DX

On execution, at first DX register is loaded with the input port having

address C00F H. The second instruction ensures that the port content is moved

over to AL register.


Thank You

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