MemoryRAM

Mano and Kime

Sections 6-2, 6-3, 6-4

RAM - Random-Access Memory

Byte - 8 bitsWord - Usually in multiples of 8

K Address lines can reference2k memory locations

b1b2b3b4 … bn00011011

n-bit words

10110101101101010110101110110110101101101010101111100101

81632

We call this a 1024 x 16 memory - 1024 memory locations ( 0 - 1023 ) that will each hold 16-bit words.

32K x 8 Static RAM1

2

3

4

5

6

7

9

1011

12

8

19

20

17

18

15

1613

14

21

22

23

24

25

26

27

28

GND

Vcc

A12

A0

D0

D1

D2

A1

A2

A3

A4

A5

A6

A7

D7

D6

D5

D4

D3

A10

A9

A8

A11

51256S

CE__

A14

OE__

A13

WE__

Static RAMA Static RAM cell - 1 bit

Recall...When Select is 0, S = 0 , R = 0 S-R Latch is in No Change State Outputs C and /C are both 0

Data In

Complement ofData In

When Select is 1, the Data in and its complementget latched into the memory cell

A PARTICULAR BIT IN A SELECTED WORD

0110 10010100 00111110 10110111 1000

4 x 8 RAM

4 memory locations,8 - bits each

Bits are written in parallel

A 16 x 1 RAM Chip16 memory locations,1 bit each

2k locations with k select lines2k=16, k = 4

Decoder controls AddressSelecting

1

00

0

0

1

1

1

1

Address decoder enables the RAM cellfor the 1-bit word selected anddisables all others

Tri - State Buffer

Tri - State Buffer

High Impedance

Tri-state buffers can be connectedtogether to form a multiplexedoutput line

The inverter ensures thatthe enable ‘select’ bits arealways complements ofeachother

Both buffers are enabled at the same timethus both are ‘driving’ the same line at thesame time

OK if values are the same (both high or bothlow) but if ‘opposing’ values are presented then you can expect high currentresulting in SMOKE!

Using a tri-state buffer for a multiplexed output

Using a4 x 4 RAMCELL toimplementa 16 x 1 RAM

Row Select

ColumnSelect

An 8 x 2 RAMusing a 4 x 4 RAM CELL Array

Chip Select

Dynamic RAM

1 Mbit (1,048,576) x 1 Dynamic RAM

1

2

3

4

5

6

7

8

9 10

11

12

13

14

15

16

Vcc

Q

A0

D

W 17

18Vss

RAS CAS

A1

A2

A3

A9

A8

A7

A6

A5

A4

TF

Need 20 address lines.Only have 10 address lines, A0 - A9.Multiplex lower and upper10 address lines using RASand CAS signals.

DRAM Bit Slice Model

Standard Symbol for a 64K x 8 RAM Chip

Remember making a 4-to-16 decoder using 5 2-to-4 decoders…

En En En En

0123

I3 I2 I1 I0

O15 O0

A 256K x 8 RAMusing 4 64K x 8 RAM Chips

The 2 most significant bits select the RAM chip

The other 16 bits address thememory locations

How about a 64K x 16 RAM using two 64K x 8 RAM chips

Most significant 8 bits Least significant 8 bits