memory mapped i/o section 8.5, appendix a.8. how should the keyboard
DESCRIPTION
I/O Processor Control Interface What kind of control/data need be transferred? Keyboard: processor keyboard: data ready? read-data? keyboard processor: data ready Printer: processor printer: data-sent print font, resolution? printer processor: printing done. error conditions – out of paper, tonerTRANSCRIPT
Memory Mapped I/O
Section 8.5, Appendix A.8.
Processor
keyboard
monitor
mouse
printer
Funny deviceAssembly linerobot controller
How should theprocessor control &communicate withthe I/O devices?
Bus
I/O Processor Control Interface
What kind of control/data need be transferred?
Keyboard: processor keyboard: data ready?
read-data? keyboard processor: data ready
Printer: processor printer: data-sent
print font, resolution? printer processor: printing done. error conditions – out of paper, toner
I/O Processor Control Interface contd.
Assembly-line robot: processor robot: move (direction, amount)
action: grab, tightenrobot processor: error- obstacle, diagnostics
Hard disk: processor disk: seek sector seek track read/write block disk processor: data-ready error conditions – bad block
I/O Processor Control Interface contd.
Should we include instructions for these control tasks?
Is there enough uniformity between I/O devices to agree on a single set of instructions to communicate with them?
How about the I/O devices we have not even foreseen yet?
Hard to develop an instruction set to control today’s and tomorrow’s devices!
Memory-Mapped I/O Contd.
Make the interface between the I/O device & processor soft. Let it be developed as a data structure.
Control
Data
An I/O handler, a program that uses these data structures to coordinate the control and data transfer.
Where does this control/data data structure reside?
Memory-Mapped I/O Contd.
OS
Text/Program
Static data
Dynamic data
Stack
I/O0x7fffffff
0x10000000
0x400000
0xffffffff
The control and data registers are mapped in the memory.
Memory-mapped I/O
Keyboard example
getchar(): reads an ASCII byte from keyboard and deposits it in $v0.
getchar: move $v0, 0($s0) ?
$s0 0x80000000
processor
Keyboard
Data register 0x80000000Control register R 0x80000004
poll: lw $t0, 4($s0) andi $t0, $t0, 0x1 beq $t0, $zero, poll
How Does Keyboard Know It’s Memory Map?
processor
Keyboard
Data register 0xf0000000Control register R 0xf0000004
CS Base(0xf0000000)
#Bytes (256) Chip-Select 0 (CS0)
ChipEnable
PollingPolling some synchronization flag repeatedly until flag is true.
Producer
Consumer
Sharedresource Lock
Is it efficient to poll?
Sometimes yes, sometimes no!
Polling Overhead
Keyboard 100 B/sMouse 200 B/sScanner 400KB-1MB/sLine printer 1KB/sLaser printer 200KB-.5MB/sVideo monitor 50MB-1GB/sNetwork card 1MB-100MB/sModem 2KB-8KB/sFloppy disk 100KB/s
Device Data Rate1600X1200 pixels/fr7.68 Mpixels/Fr2B/Pixel15.36 MB/Fr60 Fr/s921.6 MB/sInterlaced 30Fr/s:460.8 MB/s
Polling overhead contd.Polling overhead: 600 cycles transfer to polling procedure, access the device, return to the user program. CPU: 1GHz
Fraction of CPU time spent polling?: mouse: must be polled at least 30 times/s
Polling clock cycles: 30 polls/s * 600 c/poll = 18000 c/sCPU clock cycles/s: 109c/sPolling overhead: (18000)/(109)=18*10-4% = .0018%
Polling overhead contd.Fraction of CPU time spent polling?: floppy disk: transfers in 2B units at a data rate of 100 KB/s.
Polling clock cycles: 50K polls/s * 600 c/poll = 30M c/sCPU clock cycles/s: 109c/sPolling overhead: (3*107)/(109)=.03 = 3%
Polling rate?: (100 KB/s)/(2B/poll) = 50K polls/s
Polling overhead contd.Fraction of CPU time spent polling?: network card: transfers in 8B units at a data rate of 10 MB/s.
Polling clock cycles: 1.25M polls/s * 600 c/poll = 750M c/sCPU clock cycles/s: 109c/sPolling overhead: (75*107)/(109)=.75 = 75%
Polling rate?: (10 MB/s)/(8B/poll) = 1.25M polls/s
Polling overhead contd.Fraction of CPU time spent polling?: video monitor: transfers in 16B units at a data rate of 320 MB/s.
Polling clock cycles: 20M polls/s * 600 c/poll = 12G c/sCPU clock cycles/s: 109c/sPolling overhead: (12*109)/(109)=12 = 1200%
Polling rate?: (320 MB/s)/(16B/poll) = 20M polls/s
Alternative to Polling
Producer wakes up the consumer!
Interrupts / Exceptions: term used in computer architecture.
Exceptions/interrupts can be external or internal.
Keyboard interrupts the processor to indicate that the data is ready. External --- interrupts.
Internal exceptions: divide by zero, arithmetic overflow, data alignment error. Internal --- exceptions.
Why Interrupt Driven I/O?Polling is what we have seen:
main () { while(1) { PollKeyboard(); }
How to poll keyboard: Read port to see if a key is
pressed Must poll every n ms, the
minimal time period a key is pressed; otherwise user keystroke is lost.
If the program has tasks to do:
main () { task1(); PollKeyboard(); task2(); PollKeyboard(); …}
Overhead: Overhead = Polling
frequency × Polling overhead
Ease of programming: Hard to mix polling with a
normal process
Interrupt-Based C Programmingchar input_buffer[1024];
main(){ set_interrupt_handler(); task1(); task2();
/* process buffered input */
read_user_input();
// more tasks}
void interrupt_handler(int type)
{ PollKeyboard();
… /* write to input_buffer */
}
Details are platform-dependent Desktop systems: OS
manages all interrupts, put input into buffers; or send signal to application programs
Embedded systems: applications handle interrupts
Normal Control FlowIn a processor, the program counter (PC) takes a sequence of values
a0, a1, …, an-2, an-1
where each ak is the address of an instruction Ik.
Control transfer: each transition from ak to ak+1 Flow of control, or control flow: sequence of control
transfers
“Smooth” control flow: Ik and Ik+1 are adjacent in memoryChanges to smooth flow: Ik+1 not adjacent to Ik
Branches Calls, returns
Exceptional Control FlowExceptional control flow (ECF)
Abrupt changes in control flow not caused by program statements and variables: Ik+1 is external to the program
Hardware timer goes off at regular intervals I/O request completes, e.g., A/D conversion, disk I/O Packets arrive at network adapter Instruction attempts divide by zero Arithmetic overflow occurs Virtual memory page fault occurs Memory access violation
Occurs at all levels in a computer system: hardware, operating system, user
Exceptions form of ECF implementation details vary from system to system DEFINITION: an abrupt change in the control flow in
response to some change in the processor’s state Event: change in processor’s state, where state is encoded in
various bits and signals inside the processor Event might be related or unrelated to current instruction
User program
Exception handler
Event occurs here
Icurr
Inext
Exception Exception processing
Exception return (optional)
Classes of ExceptionsFour classes of exceptions:
1. Interrupts2. Traps3. Faults4. Aborts
Class Cause A/S Return behavior
Interrupt Signal from I/O device Async Always returns to next
instructionTrap Intentional
exception Sync Always returns to next instruction
Fault Potentially recoverable error Sync Might return to current
instructionAbort Nonrecoverable
error Sync Never returns
How is an exception signaled? How is the desired exception service
indicated? How does the processor prioritize and
accept exceptions? How is the control transferred from the
interrupted program to the exception service?
How is the interrupted program resumed?
Exception processing
Exception processing: Exception signaling
Internal exception: who initiates the exception? who needs to know that an exception has occurred?
Processor controller needs to be aware of an exception.
Exceptions are generated by instructions:
Arithmetic overflow Illegal instruction Data alignment error
Exception processing: Exception signaling Contd.
External interrupt: Interrupts generated by external devices such as keyboard & mouse?
Processor
IRQ: interrupt request
Exception processing: Exception signaling Contd.
ProcessorPriorityencoder
Level 1
Level 2Level 3
Level 4
Level 5
Level 6
Level 7
I0I1I2
000: no interrupt010: level 2 int.
Exception processing: Exception Service
Two General Mechanisms:(1) Centralized dispatch: exception handler decodes the cause. (MIPS style)(2) Vectored dispatch: the hardware based on a vector number invokes the appropriate service. (PowerPC style)
How can an exception service be specified?
What is an exception service? A robot? A mechanical service?A procedure (program): its address specifies the
desired service. Typically called ISP (interrupt service procedure).
Exception processing: Exception Service Contd.
Exception handler0x80000080
PC: 0x80000080
add $t0, $t1, $t1div $t0, $t3mfhi $t2addi $t2, $t2, 1
PC:0x80000180
Exception Handler
if (cause == Arithmetic Overflow) ArithmeticOverflowHandler();else if (cause == DivideByZero) DivideByZeroHandler();else if (cause == Illegal Instruction) IllegalInstructionHandler();else if (cause == external interrupt) InterruptHandler();---------- Cause Register
00Causecode
Cause RegisterCause Register
00Causecode
4
0 Ext. interrupt4 Load addr.
error5 Store addr.
error11 CPU12 Overflow
00SW0SW1IP0IP1IP2IP3IP4IP5Pending interrupts
Part of conceptual co-processor 0
mfc0 $t0, $13 or mfc0 $t0, $cause
Vectored Interrupts:Motorola
Each exception & interrupt has a 8-bit vector #: 0-255 (for Motorola 68xxx family)
123456
C
System reset
Data addr errorInst addr errorExt. interrupt
Alignment error
System call
Vector#ISP address 4 byte
Starting address of ISP =vector#*4 + starting addressof vector table = 0x1000 + 3*4 (for data addr error).
Vectored Interrupts:PPCPPC maintains an exception vector table.Only 32 vectors available.
Each vector is given 100 hex bytes (256B) of space in Exception vector table. A primitive ISP goes in that space.
Vector 0Addr: 0x00000000
Vector 1 Addr: 0x00000100
Vector 2 Addr: 0x00000200
Addr: 0x00001f00Vector 31
Exception processing: prioritization
If multiple exceptions/interrupts raised simultaneously, how do we prioritize them?
In general: internal exceptions (software raised) are always given higher priority than the external interrupts (hardware device initiated).
Within software exceptions, there might be multiple levels of prioritization: 2 in MIPS.
Within external interrupts, multiple levels of priority: 6 in MIPS.
Exception processing: prioritizationcontd.
Cause Register
00Causecode
400SW0SW1IP0IP1IP2IP3IP4IP5
Pending interrupts
Look at all the pending interrupts at the entry into the exception-handler. If more than one is 1, choose based on the priority.
Can a higher priority interrupt pre-empt the ISP for a lower priority interrupt?
There can be nested exception service procedures!
Exception processing: Control transfer
Exception-handler is just like any other procedure.Calling is not done through a procedure call.It is called by the processor controller by forcing its address 0x80000080 into PC.
What should be saved before forcing 0x80000080 into PC (so that we can resume the interrupted program)?
Current program’s state including its address.
Exception processing: Control transfer Contd.
Right before PC 0x80000080, the current PC is saved in EPC: PC EPC (Exception PC).
EPC is Reg. 14 in co-processor 0: mfc0 $t0, $14 or mfc0 $t0, $EPC
Other program state is kept in Status Register:
I.E.K/U15 8Interrupt
mask
Exception processing: Control transfer Contd.
While in exception-handler, can another exception be accepted?
EPC gets overwritten similar to $ra!
One of the first acts in exception-handler should be to save EPC, cause, and status register on a stack.
While saving these registers, should we disable all the interrupts?
Exception processing: Control transfer Contd.
I.E.K/U
At entry into exception-handler: 0 0(1) All exceptions are disabled.(2) K/U=0: kernel mode (supervisor mode).
I.E.K/UI.E.K/UI.E.K/Ucurrentprev.old
I.E.K/UI.E.K/UI.E.K/U0 0
Exception processing: Control transfer Contd.
exception-handler(){ /* keep the interrupts disabled */ (1) save EPC, cause, status regs on system stack. (2) enable interrupts. (3) decode cause and call appropriate ISP. }
exception-handler: mfc0 $k0, $cause mfc0 $k1, $EPC sw $k0, -4($sp) sw $k1, -8($sp) sw $t0, -12($sp) addi $sp, $sp, -12 mfc0 $t0, $status ori $t0, $t0, 0x1 mtc0 $status, $t0 andi $k0, $k0, 0x3c beq $k0, $zero, interrupt --- ---
Exception processing: Control transfer PPC
Machine State Register (MSR)
LE
LE=0Big-endian
RI
RI=1: recoverable
00DRIRIP0
IP=0: exceptionVector tableStarts at 0x000else 0xfff
PREE0PR=0: supervisor =1: user
EE=ext. interrupt enable =0: disable =1:enable
PPC Exception Registers
PC saved here
Machine Status Save/Restore Register 0 (SRR0)
Machine Status Save/Restore Register 1 (SRR1)
MSR
Save MSR bitsException specific info
LE
RI
IP
EE
PR
0000
1-4
000000
10-15
PPC Exception Registers
MSR
LE
RI
IP
EE
PR
On an exception:
ILE
000
mtmsr r2: r2 MSRmfmsr r3: MSR r3
mtspr SRR0, r2: r2 SRR0mfspr r3, SRR1: SRR1 r3
Each exception handler must save SRR0, SRR1, and MSR before enabling exceptions (EE=1).
PPC Exception PrioritiesNon-maskable, asynchronous: Priority 1: System reset Priority 2: Machine check
Synchronous, maskable: instruction dependent ones such as alignment, FP: Priority 3, 4.
Asynchronous, maskable: external interrupt (priority 5) decrementer (priority 6).
Exception processing: resume
Need to return from the exception handler to the interrupted program.
Should we just use jr EPC?
A special instruction: rfe return from exception. only restores the status register.
I.E.K/UI.E.K/UI.E.K/U
EPC PC: need to use jr explicitly.
Exception processing: PPC resume
return from interrupt: rfi.
MSR[16-23, 25-27, 30-31] SRR1[16-23, 25-27, 30-31]
PC SRR0[0-29]||00
Interrupt Driven Keyboard
ISP:
getchar: lw $v0, 0($s0) jr $ra
processor
Keyboard
Data register 0x80000000Control register R 0x80000004
IRQ
Interrupt-Handler
exception-handler(){ if (cause == interrupt at level 1) getchar();}exception-handler: mfc0 $k0, $cause mfc0 $k1, $EPC sw $k0, -4($sp) sw $k1, -8($sp) sw $t0, -12($sp) addi $sp, $sp, -12 mfc0 $t0, $status ori $t0, $t0, 0x1 mtc0 $status, $t0 andi $t0, $k0, 0x3c bne $t0, $zero, noninterrupt
00Causecode00SW0SW1IP0IP1IP2IP3IP4IP5
andi $t0, $k0, 0x800 beq $t0, $zero, otherinterrupt jal getcharotherinterrupt: -- --- ---noninterrupt: -- --- --- rfe jr $k1
Interrupt-Handler A-35, HP
00Causecode00SW0SW1IP0IP1IP2IP3IP4IP5 0000
.ktext 0x80000080sw $a0, save0sw $a1, save1
mfc0 $k0, $13 #cause
mfc0 $k1, $14 #EPC
sgt $v0, $k0, 0x44bgtz $v0, done
move $a0, $k0move $a1, $k1jal print_excp
done: lw $a0, save0 lw $a1, save1 addiu $k1, $k1, 4
rfe jr $k1
.kdatasave0: .word 0save1: .word 0
Transmitter Control
The character typed at the keyboard is echoed back to the keyboard (and displayed).
processor
Keyboard
Rec. Data register 0x80000000Rec. Control reg R 0x80000004
Trans. Data Reg.Trans. Control Reg.
IE
RIE0x800000080x8000000c
IRQ
lw $t0, 0($s0) ori $t0, $t0, 0x2 sw $t0, 0($s0) #enables interrupt
MIPS-32 Exception handling
Cause register
00Causecode00SW0SW1IP0IP1IP2IP3IP4IP5BD
BD=1: an instruction in the branch delay slot caused this exception.
I.E.EXL15 8Interrupt
mask
Status Register
Exception levelK/U 0
0
MIPS-32 Interrupt-Handler
.ktext 0x80000180sw $a0, save0sw $a1, save1
mfc0 $k0, $13 #cause
srl $a0, $k0, 2 andi $a0, $a0, 0xf
bgtz $a0, done
move $a0, $k0mfc0 $a1, $14jal print_excp
done: mtc0 $0, $13 mfc0 $k0, $12 andi $k0, 0xfffd ori $k0, 0x1 mtc0 $k0, $12 lw $a0, save0
lw $a1, save1 addiu $k1, $k1, 4
eret
.kdatasave0: .word 0save1: .word 0