memory - cornell university...0 1 z 100 111 dq tri-state buffers • if enabled (e=1), then q = d...
TRANSCRIPT
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Memory
[Weatherspoon, Bala, Bracy, and Sirer]
Prof. Hakim WeatherspoonCS 3410
Computer ScienceCornell University
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Announcements
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• Level Up (optional enrichment)• Teaches CS students tools and skills needed in
their coursework as well as their career, such as Git, Bash Programming, study strategies, ethics in CS, and even applying to graduate school.
• Thursdays at 7-8pm in 310 Gates Hall, starting this week
• http://www.cs.cornell.edu/courses/cs3110/2019sp/levelup/
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AnnouncementsMake sure you are• Registered for class, can access CMS• Have a Section you can go to. • Lab Sections are required.
• “Make up” lab sections only Friday 11:40am or 1:25pm
• Bring laptop to Labs• Project partners are required for projects starting
w/ project 2• Project partners will be assigned (from the same lab
section, if possible)
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Announcements• Make sure to go to your Lab Section this week• Completed Proj1 due Friday, Feb 15th• Note, a Design Document is due when you submit
Proj1 final circuit• Work alone
BUT use your resources• Lab Section, Piazza.com, Office Hours• Class notes, book, Sections, CSUGLab
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AnnouncementsCheck online syllabus/schedule • http://www.cs.cornell.edu/Courses/CS3410/2019sp/schedule• Slides and Reading for lectures• Office Hours• Pictures of all TAs• Project and Reading Assignments• Dates to keep in Mind
• Prelims: Tue Mar 5th and Thur May 2nd • Proj 1: Due next Friday, Feb 15th• Proj3: Due before Spring break• Final Project: May 16th
Schedule is subject to change
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Goals for todayMemory
• CPU: Register Files (i.e. Memory w/in the CPU)• Scaling Memory: Tri-state devices• Cache: SRAM (Static RAM—random access memory• Memory: DRAM (Dynamic RAM)
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Last time: How do we store one bit
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D Flip Flop stores 1 bitQD
clk
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Goal for todayHow do we store results from ALU computations?
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alu
PC
imm
memory
memorydin dout
addr
target
offset cmpcontrol
=?
new pc
registerfile
inst
extend
+4 +4
Big Picture: Building a Processor
A Single cycle processor
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alu
PC
imm
memory
memorydin dout
addr
target
offset cmpcontrol
=?
new pc
registerfile
inst
extend
+4 +4
Big Picture: Building a Processor
A Single cycle processor
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Goal for todayHow do we store results from ALU computations?How do we use stored results in subsequent operations?
Register File
How does a Register File work? How do we design it?
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Register FileRegister File
• N read/write registers• Indexed by
register numberDual-Read-Port
Single-Write-Port32 x 32
Register File
QA
QB
DW
RW RA RBW
32
32
32
1 5 5 5
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Register FileRecall: Register• D flip-flops in parallel • shared clock• extra clocked inputs:
write_enable, reset, …
clk
D0
D3
D1
D2
4 44-bitreg
clk
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Register FileRecall: Register• D flip-flops in parallel • shared clock• extra clocked inputs:
write_enable, reset, …
clk
D0
D3
D1
D2
32 3232-bitreg
clk
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Register File• N read/write registers• Indexed by
register number
How to write to one register in the register file?
Register FileReg 0
….Reg 30Reg 31
Reg 15-to-32decoder
5RW W
D32
addix1, x0, 1000001
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Aside: 3-to-8 decoder truth table & circuit
i2 i1 i0 o0 o1 o2 o3 o4 o5 o6o7
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
3-to-8decoder
3RW
…
001
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Register File• N read/write registers• Indexed by
register number
How to read from two registers?
Register File32
Reg 0Reg 1….
Reg 30Reg 31
MUX
MUX
32QA
32QB
55
RBRA
….
….add x1, x0, x5
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Register FileRegister File
• N read/write registers• Indexed by
register number
Implementation:• D flip flops to store
bits• Decoder for each
write port• Mux for each read
port
32Reg 0Reg 1….
Reg 30Reg 31
MUX
MUX
32QA
32QB
55
RBRA
….
….
5-to-32decoder
5RWW
D32
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Register FileRegister File
• N read/write registers• Indexed by
register number
Implementation:• D flip flops to store bits• Decoder for each write port• Mux for each read port
Dual-Read-PortSingle-Write-Port
32 x 32 Register File
QA
QB
DW
RW RA RBW
32
32
32
1 5 5 5
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Register FileRegister File
• N read/write registers• Indexed by
register number
Implementation:• D flip flops to store bits• Decoder for each write port• Mux for each read port
What happens if same register read and written during same clock cycle?
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Register File tradeoffs+ Very fast (a few gate delays for
both read and write)+ Adding extra ports is
straightforward– Doesn’t scale
e.g. 32Mb register file with 32 bit registersNeed 32x 1M-to-1 multiplexor and 32x 20-to-1M decoderHow many logic gates/transistors?
Tradeoffs a
b
c
d
e
f
g
h
s2s1s0
8-to-1 mux
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TakewayRegister files are very fast storage (only a few gate delays), but does not scale to large memory sizes.
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Goals for todayMemory
• CPU: Register Files (i.e. Memory w/in the CPU)• Scaling Memory: Tri-state devices• Cache: SRAM (Static RAM—random access
memory)• Memory: DRAM (Dynamic RAM)
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Next GoalHow do we scale/build larger memories?
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Building Large MemoriesNeed a shared bus (or shared bit line)
• Many FlipFlops/outputs/etc. connected to single wire• Only one output drives the bus at a time
• How do we build such a device?
S0D0
shared line
S1D1 S2D2 S3D3 S1023D1023
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Tri-State Devices
E
E D Q0 0 z0 1 z1 0 01 1 1
D Q
Tri-State Buffers• If enabled (E=1), then Q = D• Otherwise, Q is not connected (z = high impedance)
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Tri-State Devices
E
E D Q0 0 z0 1 z1 0 01 1 1
D Q
Tri-State Buffers• If enabled (E=1), then Q = D• Otherwise, Q is not connected (z = high impedance)
Q
Vsupply
Gnd
D
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Tri-State Devices
E
E D Q0 0 z0 1 z1 0 01 1 1
D Q
Tri-State Buffers• If enabled (E=1), then Q = D• Otherwise, Q is not connected (z = high impedance)
DQ
E Vsupply
Gnd
D
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Tri-State Devices
E
E D Q0 0 z0 1 z1 0 01 1 1
D Q
Tri-State Buffers• If enabled (E=1), then Q = D• Otherwise, Q is not connected (z = high impedance)
DQ
E Vsupply
GndA B OR NOR0 0 0 10 1 1 01 0 1 01 1 1 0
A B AND NAND0 0 0 10 1 0 11 0 0 11 1 1 0
0
0
1
0
off
offz
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Tri-State Devices
E
E D Q0 0 z0 1 z1 0 01 1 1
D Q
Tri-State Buffers• If enabled (E=1), then Q = D• Otherwise, Q is not connected (z = high impedance)
DQ
E Vsupply
GndA B OR NOR0 0 0 10 1 1 01 0 1 01 1 1 0
A B AND NAND0 0 0 10 1 0 11 0 0 11 1 1 0
1
1
1
1
off
on0
0
0
0
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Tri-State Devices
E
E D Q0 0 z0 1 z1 0 01 1 1
D Q
Tri-State Buffers• If enabled (E=1), then Q = D• Otherwise, Q is not connected (z = high impedance)
DQ
E Vsupply
GndA B OR NOR0 0 0 10 1 1 01 0 1 01 1 1 0
A B AND NAND0 0 0 10 1 0 11 0 0 11 1 1 0
1
1
0
0
on
off1
1
1
1
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Shared BusS0D0
shared line
S1D1 S2D2 S3D3 S1023D1023
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TakewayRegister files are very fast storage (only a few gate delays), but does not scale to large memory sizes.
Tri-state Buffers allow scaling since multiple registers can be connected to a single output, while only one register actually drives the output.
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Goals for todayMemory
• CPU: Register Files (i.e. Memory w/in the CPU)• Scaling Memory: Tri-state devices• Cache: SRAM (Static RAM—random access
memory)• Memory: DRAM (Dynamic RAM)
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Next GoalHow do we build large memories?
Use similar designs as Tri-state Buffers to connect multiple registers to output line. Only one register will drive output line.
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Memory• Storage Cells + bus• Inputs: Address, Data (for writes)• Outputs: Data (for reads)• Also need R/W signal (not shown)
• N address bits 2N words total• M data bits each word M bits
M
NAddress
Data
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• Storage Cells + bus• Decoder selects a word line• R/W selector determines access type• Word line is then coupled to the data lines
Memory
Data
Addr
ess
Dec
oder
R/W
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• Storage Cells + bus• Decoder selects a word line • R/W selector determines access type• Word line is then coupled to the data lines
Memory
Din
8
Dout
8
22Address
Chip SelectWrite Enable
Output Enable
Memory4M x 8
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E.g. How do we design a 4 x 2 Memory Module?
(i.e. 4 word lines that areeach 2 bits wide)?
Memory
2-to-4decoder
Address
D Q D Q
D Q D Q
D Q D Q
D Q D Q
Dout[1] Dout[2]
Din[1] Din[2]
enable enable
enable enable
enable enable
enable enable
0
1
2
3Write Enable
Output Enable
4 x 2 SRAM
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E.g. How do we design a 4 x 2 Memory Module?
(i.e. 4 word lines that areeach 2 bits wide)?
Memory
2-to-4decoder
2Address
D Q D Q
D Q D Q
D Q D Q
D Q D Q
Dout[1] Dout[2]
Din[1] Din[2]
enable enable
enable enable
enable enable
enable enable
0
1
2
3Write Enable
Output Enable
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E.g. How do we design a 4 x 2 Memory Module?
(i.e. 4 word lines that areeach 2 bits wide)?
Memory
2-to-4decoder
2Address
D Q D Q
D Q D Q
D Q D Q
D Q D Q
Dout[1] Dout[2]
Din[1] Din[2]
enable enable
enable enable
enable enable
enable enable
0
1
2
3Write Enable
Output Enable
Word lines
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E.g. How do we design a 4 x 2 Memory Module?
(i.e. 4 word lines that areeach 2 bits wide)?
Memory
2-to-4decoder
2Address
D Q D Q
D Q D Q
D Q D Q
D Q D Q
Dout[1] Dout[2]
Din[1] Din[2]
enable enable
enable enable
enable enable
enable enable
0
1
2
3Write Enable
Output Enable
Bit lines
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SRAM CellTypical SRAM Cell
B
word linebit l
ine
Each cell stores one bit, and requires 4 – 8 transistors (6 is typical)
Pass-ThroughTransistors
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SRAM CellTypical SRAM Cell
B
word linebit l
ine
Each cell stores one bit, and requires 4 – 8 transistors (6 is typical)Read:• pre-charge B and B to Vsupply/2• pull word line high• cell pulls B or B low, sense amp detects voltage difference
1 01) Pre-charge
B = Vsupply/23) Cell pulls B low
i.e. B = 0
1) Pre-charge B = Vsupply/2
3) Cell pulls B highi.e. B = 1
Disable (wordline = 0)2) Enable (wordline = 1)
onon
offoff
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Disabled (wordline = 0)
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SRAM CellTypical SRAM Cell
B
word linebit l
ine
Each cell stores one bit, and requires 4 – 8 transistors (6 is typical)Read:• pre-charge B and B to Vsupply/2• pull word line high• cell pulls B or B low, sense amp detects voltage differenceWrite:• pull word line high• drive B and B to flip cell
1) Enable (wordline = 1)
2) Drive B highi.e. B = 1
2) Drive B lowi.e. B = 0
→ →1 0 10
onon offoff
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E.g. How do we design a 4 x 2 SRAM Module?
(i.e. 4 word lines that areeach 2 bits wide)?
SRAM
2-to-4decoder
2Address
D Q D Q
D Q D Q
D Q D Q
D Q D Q
Dout[1] Dout[2]
Din[1] Din[2]
enable enable
enable enable
enable enable
enable enable
0
1
2
3Write Enable
Output Enable
Bit Line
Word lines
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E.g. How do we design a 4 x 2 SRAM Module?
(i.e. 4 word lines that areeach 2 bits wide)?
SRAM
2-to-4decoder
2Address
D Q D Q
D Q D Q
D Q D Q
D Q D Q
Dout[1] Dout[2]
Din[1] Din[2]
enable enable
enable enable
enable enable
enable enable
0
1
2
3Write Enable
Output Enable
4 x 2 SRAM
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SRAM
22Address
Dout
Din
Write EnableOutput Enable
4M x 8 SRAM
8
8
E.g. How do we design a 4M x 8 SRAM Module?
(i.e. 4M word lines that are each 8 bits wide)?
Chip Select
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SRAM
12Address [21-10]
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
12 x 4096decoder
mux
1024
mux
1024
mux
1024
mux
1024
mux mux
1024 1024
mux
1024
mux
1024
Dout[7]1
Dout[6]1
Dout[5]1
Dout[4]1
Dout[3]1
Dout[2]1
Dout[1]1
Dout[0]1
Address [9-0]10
4M x 8 SRAM
E.g. How do we design a 4M x 8 SRAM Module?
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SRAM
12Address [21-10]
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
4k x 1024SRAM
rowdecoder
1024 1024 1024 1024 1024 1024 1024 1024Address [9-0]10
4M x 8 SRAM
E.g. How do we design a 4M x 8 SRAM Module?
column selector, sense amp, and I/O circuits
Shared Data Bus
Chip Select (CS)R/W Enable
8
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SRAM Modules and ArraysA21-0
Bank 2
Bank 3
Bank 4
4M x 8SRAM
4M x 8SRAM
4M x 8SRAM
4M x 8SRAM
R/W
msb lsb
CS
CS
CS
CS
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SRAM• A few transistors (~6) per cell• Used for working memory (caches)
• But for even higher density…
SRAM Summary
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Dynamic RAM: DRAMDynamic-RAM (DRAM)
• Data values require constant refresh
Gnd
word linebit l
ine
Capacitor
Each cell stores one bit, and requires 1 transistors
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Dynamic RAM: DRAMDynamic-RAM (DRAM)
• Data values require constant refresh
Gnd
word linebit l
ine
Capacitor
Each cell stores one bit, and requires 1 transistors
Pass-ThroughTransistors
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Dynamic RAM: DRAMDynamic-RAM (DRAM)
Gnd
word linebit l
ine
Capacitor
Each cell stores one bit, and requires 1 transistorsRead:• pre-charge B and B to Vsupply/2• pull word line high• cell pulls B low, sense amp detects voltage difference
0
Disable (wordline = 0)
1) Pre-chargeB = Vsupply/2
3) Cell pulls B lowi.e. B = 0
2) Enable (wordline = 1)
onoff
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Dynamic RAM: DRAMDynamic-RAM (DRAM)
Gnd
word linebit l
ine
Capacitor
Each cell stores one bit, and requires 1 transistorsRead:• pre-charge B and B to Vsupply/2• pull word line high• cell pulls B low, sense amp detects voltage differenceWrite:• pull word line high• drive B charges capacitor
0 1→2) Drive B high
i.e. B = 1Charges capacitor
onoff
Disable (wordline = 0)1) Enable (wordline = 1)
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Single transistor vs. many gates• Denser, cheaper ($30/1GB vs. $30/2MB)• But more complicated, and has analog sensing
Also needs refresh• Read and write back…• …every few milliseconds• Organized in 2D grid, so can do rows at a time• Chip can do refresh internally
Hence… slower and energy inefficient
DRAM vs. SRAM
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MemoryRegister File tradeoffs
+ Very fast (a few gate delays for both read and write)+ Adding extra ports is straightforward– Expensive, doesn’t scale– Volatile
Volatile Memory alternatives: SRAM, DRAM, …– Slower+ Cheaper, and scales well– Volatile
Non-Volatile Memory (NV-RAM): Flash, EEPROM, …+ Scales well– Limited lifetime; degrades after 100000 to 1M writes
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SummaryWe now have enough building blocks to build machines that can perform non-trivial computational tasks
Register File: Tens of words of working memorySRAM: Millions of words of working memoryDRAM: Billions of words of working memoryNVRAM: long term storage
(usb fob, solid state disks, BIOS, …)
Next time we will build a simple processor!