memory contents contentsoperation address (binary) (hex)
DESCRIPTION
Input the value from a keyboard connected to the port at address 05H. Add 7 to the value read in. Output the result to a display connected to the port at address 02H. Memory Contents ContentsOperation address (Binary) (Hex) 00100 H 11100100E4Input From - PowerPoint PPT PresentationTRANSCRIPT
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Memory Contents Contents Operationaddress (Binary) (Hex)
00100 H 11100100 E4 Input From00101 H 00000101 05 Port 05 H00102 H 00000100 04 Add00103 H 00000111 07 07 H00104 H 11100110 E6 Output to00105 H 00000010 02 Port 02 H
1. Input the value from a keyboard connected to the port at address 05H.
2. Add 7 to the value read in.3. Output the result to a display connected to the port at
address 02H.
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SEQUENCE
f. CPU sends out address of first instruction to memory
g. CPU sends out memory ‘Read’ control signal to enable memory
n. Instruction byte sent from memory to CPU on data bus (goes into
instruction
register IR of CPU)
e. Address next memory location to get rest of the instruction
h. Send memory ‘Read’ control signal to enable memory
o. Port address byte sent from memory to CPU on data bus
u. CPU sends out port address on address bus
v. CPU sends out Input ‘Read’ control signal to enable port
x. Data from port sent to CPU on data bus
d. CPU sends address of next instruction to memory
j. CPU sends memory ‘Read’ control signal to enable memory
p. Instruction byte from memory sent to CPU on Data bus
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c. CPU sends next address to memory to get rest of instruction
k. CPU sends memory ‘Read’ control signal to enable memory
q. Number 07 H sent from memory to CPU on data bus
b. CPU sends address of next instruction to memory
l. CPU sends memory ‘Read’ control signal to enable memory
r. Instruction byte from memory sent to CPU on data bus
a. CPU sends out next address to get rest of instruction
m. CPU sends out memory ‘Read’ control signal to enable memory
s. Port address byte sent from memory to CPU on data bus
t. CPU sends out port address on address bus
y. CPU sends out data to port on data bus
w. CPU sends out Output ‘Write’ signal to enable port
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a b c d e f n o p q r sg h j k l m
Memory
CPU
Control bus
Address bus D
ata
bus
Control bus
x yt u v w
I/O
Display
Keyboard
0 1 2 3
4 5 6 7
8 9 + -
P O R T 0 5 P O R T 0 2
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Symbols Description Examples
Capital letters and numerals Denotes a register A, MBR, R1
Subscript Denotes a bit of a register A2, Bi, B6
Parentheses ( ) Denotes a portion of a register PC(H)
Arrow Denotes transfer of information A B
Colon : Denotes termination of control function P : , x’T 0 :
Comma , Seperates two microoperations A B, B A
Square brackets [ ] Specifies an address for memory transfer MBR M[MAR]
Table. 1 Basic symbols for register-transfer logic
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Register A
Register B
Register C
Register D
Load0
1
2
3
4x1MuxNo.1
0
1
2
3
4x1MuxNo.n
.
.
.
.
.
.
.
.
x y
Select
0 1 2 3z
w
E
Enable
SelectDestinationdecoder
Line No.1
Line No. nn bus lines
An A1
Bn B1
Cn C1
Dn D1
Bus System for four registers
.
4x1MuxNo.1
.
.
.
.
.
..
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Bus SiControl
So
Output Control
Input Control
Bidirectional Bus
Bus disabled(high impedance)
Bi-directional bus buffer
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S1 0
S0 1
2E 2 x 4 3 Decoder
Select
Enable
A0
B0
C0
D0
Bus line for bit 0
Bus line with three-state-buffers
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A0
A1
A3
A2
B0
B1
B3
B2
MUX
Destinationdecoder
Memory unitMUX
Select
Read
Write
Address bus
Select
Select
Inputs
Outputs
Data bus
Memory that communicates with multiple registers
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SymbolicDesignation Description
F A + B Contents of A plus B tranfered to F
F A – B Contents of A minus B tranfered to F
B B’ Compliment register B ( 1’s compliment )
B B’ + 1 Form the 2’s compliment of the contents of register B
F A + B’ + 1 A plus the 2’s compliment of B transferred to F
A A + 1 Increment the contents of A by 1 ( count up )
A A - 1 Decrement the contents of A by 1 ( count down )
Arithmetic microoperations
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Boolean funtions Microoperations Name
F = 0 F 0 ClearF1 = xy F A . B ANDF2 = xy’ F A . B’ F3 = x F A Transfer AF4 = x’y F A’ . BF5 = y F B Transfer BF6 = x(+) y F A (+) B Exclusive-ORF7 =x + y F A + B ORF8 = ( x + y )’ F ( A + B )’ NORF9 = ( x (+) y )’ F ( A (+) B )’ Exclusive-NORF10 = y’ F B’ Compliment BF11 = x + y’ F A + B’F12 = x’ F A’ Compliment AF13 = x’ + y F A’ + BF14 = ( xy )’ F ( A + B )’ NANDF15 = 1 F All 1’s Set to all 1’s
Logic Microoperations
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Symbolic Descriptiondesignation
shl A Shift – left register A, contents of rigt-most flip flop becomes 0
Shr A Shift – right register A, contents of leftt-most flip flop becomes 0
Cil A Circulate left contents of register A
Cir A Circulate right contents of register A
ashl A Arithmetic shift- left contents of register A
ashr A Arithmetic shift left contents of register A
Shift Microoperations
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A1 A2 A3 A4 B1 B2 B3 B4
A B
F4 F3 F2 F1
F
CoutOutputcarry
S2 Mode select
S1
S0
Functionselect
Cin Input Carry
Block diagram of a 4-bit ALU
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X1
X4
X3
X2
Y1
Y4
Y3
Y2
C2
Ci
C4
C3
C5 Cout
F2
F1
F3
F4(FA)
(FA)
(FA)
(FA)
Cin
S1
S0
A1
B1
A4
A3
A2
B2
B4
B3
.
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Function X Y Output FunctionsSelect Equals Equals Equals
S2 S1 S0 Cin
0 0 0 0 A 0 F = A Transfer A
0 0 0 1 A 0 F = A+1 Increment A
0 0 1 0 A B F = A+B Add B to A
0 0 1 1 A B F = A+B+1 Add B to A plus 1
0 1 0 0 A B’ F = A+B’ Add 1’s compliment of B to A
0 1 0 1 A B’ F = A+B’+1 Add 2’s compliment of B to A
0 1 1 0 A All 1’s F = A-1 Decrement A
0 1 1 1 A All 1’s F = A Transfer A
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0
3
2
1
4X1MUX
Ai
Bi
S1
S0
Fi
S2 S1 S0 Output Operation
1 0 0 Fi = Ai + Bi OR
1 0 1 Fi = Ai (+) Bi XOR
1 1 0 Fi = Ai . Bi And
1 1 1 Fi = Ai NOT
Function Table
Logic Diagram
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One stage ofarithmetic
circuit
One stage oflogic circuit
2 X 1MUX0
1
Ci+1Ci
Fi
Ai
S2
S0
S1
Bi
S2
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S2 S1 S0 Xi Yi Ci Fi = Xi (+) Yi Operation Req Function
1 0 0 Ai 0 0 Fi = Ai Trasfer A OR
1 0 1 Ai Bi 0 Fi = Ai (+) Bi XOR XOR
1 1 0 Ai Bi’ 0 Fi = Ai (.) Bi Equivalence AND
1 1 1 Ai 1 0 Fi = Ai’ NOT NOT
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S2
S1
S0
A1
B1
B1’
Cin
S2’ C1
C2
S2’
X1
Y1
Full adder
F1
S2S1’S0’S2S1S0’
S0
B1
B1Z1
Z2
S1
Logic Diagram of ALU
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Function Output FunctionsSelect
S2 S1 S0 Cin
0 0 0 0 F = A Transfer A
0 0 0 1 F = A+1 Increment A
0 0 1 0 F = A+B Addition
0 0 1 1 F = A+B+1 Add with carry
0 1 0 0 F = A-B-1 Subtract with borrow
0 1 0 1 F = A-B Subtraction
0 1 1 0 F = A-1 Decrement A
0 1 1 1 F = A Transfer A
1 0 0 x F = A+B OR
1 0 1 x F = A(+)B XOR
1 1 0 x F = A.B And
1 1 1 x F = A’ Compliment A
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CPU
Data bus
Clock output
Interrupt Acknowledge
Bus Granted
Read
Write
Address bus
Power supply
Clock input
Reset
Interrupt request
Bus Request
Fig. Control signals in a microprocessor
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B
D
F G
E
C
Program counter (PC)
Stack pointer
Address register (AR)
Address buffers
Multiplexer
Instructionregister
(IR)
Instructiondecoder
Statusregister
Temporaryregister
(T)
ALU
Accumulatorregister (A)
Timing and
control
Re
gis
ter
se
lec
t
Data buffers
8 bit internal bus
Bidirectional data bus (DBUS)
Address bus (ABUS)
Other controls
WR(Write)
RD(read)
H L
16 9 8 1
Fig. Block diagram of microprocessor
8 1
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Instruction(program)
Operand(data)
Memory4096 x 16
Binary operand
Processor register(Accumulator)
Op code Address
15 0
Instruction format
15 12 11 0
Fig. Stored program organization
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AC AC
I Op code Address
15 14 12 11 0
(a). Instruction format
1 ADD 457
Operand
22
457
(b). Direct address (c). Indirect address
0 ADD 300
1350
Operand
35
300
1350
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Heaxadecimal Instructioncode symbol Description Function
78 MOV A,B Move B to A A B
3E MVI Move immediate operand to A A D8
7E MOV A,FG Move to A with register indirect A M[FG]
77 MOV FG,A Move A with register indirect M[FG] A
3A LDA AD16 Load A direct A M[AD16]
80 Add B ADD B to A A A + B
86 SUB B Subtract B from A A A – B
A0 ANA B AND B to A A A.B
04 INR B Increment B B B + 1
2F CMA Compliment A A A’
37 STC Set carry bit to 1 C 1
C3 JMP AD16 Jump unconditionally PC AD16
DA JC AD16 Jump on carry If (C=1) then (PC AD16)
Table. Partial list of instructions for mocroprocessor
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Next op-code 46
35
03
46
35
03
46
73
CALL Op-code
26
CALL Op-code
26
73
Next op-code
Subroutine
Return op-code
First op-code
First op-code
Subroutine
Return op-code
First op-code
Subroutine
Return op-code
Next op-code
CALL Op-code
26
73
Main program
3500
3501
3502
3503
(a). Initial values
(b). After execution of the CALL instruction
(c). After execution of RETURN instruction
SubroutineStack
PC
PC
PC
SP
SP
SP
3500
3501
3502
3503
3503
7800
7803
7800
7801
7802
7803
7803
2673
2686
2673
2686
Fig. Numerical example for the call-subroutine and return-from-subroutine instructions.
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1
4
2
3IEN
End of instruction execution
Interruptenable
Interrupt
request
Interrupt source
Interrupt vector (DBUS)
Interrupt acknowledge
(INTACK)
Fig. Vectored Interrupt Configuration
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Input Outputs(Interrupt source)
( Partial Address ) ( Interrupt request )
I0 I1 I2 I3 x y R
1 x x x 0 0 1
0 1 x x 0 1 1
0 0 1 x 1 0 1
0 0 0 1 1 1 1
Fig. Priority encoder truth table
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Chip select 1
Chip select 2
Read
Write
7-bitaddress
CS1
CS2’
RD
WR
AD7
8-bit data bus
128x8RAM
Fig. Block diagram of a RAM chip
Fig. Function table of RAM chip
CS1 CS2’ RD WR Memory function State of data bus
0 0 x x Inhibit High impedance
0 1 x x Inhibit High impedance
1 0 0 0 Inhibit High impedance
1 0 0 1 Write Input data to RAM
1 0 1 x Read Output data from RAM
1 1 x x Inhibit High impedance
8-bitDatabus
Chip select 1
Chip select 2
9-bitaddress
CS1 512x8 ROM
CS2’
AD9
Fig. Block diagram
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Address bus Hexadecimal addressComponent 10 9 8 7 6 5 4 3 2 1
RAM 1 0000-007F 0 0 0 x x x x x x x
RAM 2 0080-00FF 0 0 1 x x x x x x x
RAM 3 0100-017F 0 1 0 x x x x x x x
RAM 4 0180-01FF 0 1 1 x x x x x x x
ROM 0200-03FF 1 x x x x x x x x x
Table. Memory address map for microcomputer
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Microprocessor Address bus
16-11 10 9 8 7-1 RD WR Data bus
CS1 128x8CS2’ RAM1RDWR DataAD7
Decoder 3 2 1 0
CS1 128x8CS2’ RAM3RDWR DataAD7
CS1 128x8CS2’ RAM2RDWR DataAD7
CS1 128x8CS2’ RAM4RDWR DataAD7
CS1 512x8CS2’ ROM
Data AD9
1-7
8
9Fig. Memory connection to the microprocessor
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Argument register
0 1 0 0 0 3 4 5 0
6 7 1 0 0 2 7 7 7
1 2 3 4 2 2 3 4 5
Address Data
Fig. The Associative Mapping cache
CPU address ( 15 bits)
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Tag Index
0 0 0 0 0
7 7 7 7 7
0 0 0
7 7 7
6-bits 9-bits
Octal address
Octal address
32K x 12Main memory
Address = 15 bitsData = 12 bits
512 x 12Cache memory
Address = 9 bitsData = 12 bits
Fig. Addressing relationships between main and cache memories
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1 2 2 0
2 3 4 0
3 4 5 0
4 5 6 0
5 6 7 0
6 7 1 0
0 0 1 2 2 0
0 2 6 7 1 0
Memory dataMemoryaddress
0 0 0 0 0
0 2 7 7 7
0 2 0 0 0
0 1 7 7 7
0 0 7 7 7
0 1 0 0 0
Index address
0 0 0
7 7 7
Fig. Direct Mapping cache organization
Tag Data
(a). Main memory
(b). Cache memory
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0 0 0 0 1 3 4 5 0 0 2 5 6 7 0
7 7 7 0 2 6 7 1 0 0 0 2 3 4 0
Index Tag Data Tag Data
Fig. Set-associative mapping cache with set size of two.
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Auxiliary memory
Program 1
Data 1, 1
Data 1, 2
Program 2
Data 2, 1
Program 1
Data 1, 1
Address spaceN = 1024 K = 2²º
Memory spaceM = 32 K = 2¹ˢ
Fig. Relationship between address and memory space in a virtual memory system.
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Page 3
Page 2
Page 1
Page 0
Page 7
Page 6
Page 5
Page 4
Block 3
Block 2
Block 1
Block 0
Address spaceN = 8 k = 2¹³ Memory space
M = 4 K = 2¹²
Fig. Address space and memory spsce split into groups of 1 k words.
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1 0 1 0 1 0 1 0 1 0 0 1 1
0
1 1 1
0 0 1
0
0
0 1 1
1 0 1
0
0 1 1
Block 0
MBR
0 1 0 1 0 1 0 1 0 0 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Page No. Line number
Main memoryaddress register
Tableaddress
Presence bit
Virtualaddress
Main memory
Memory pagetable bufferregister
Block 1
Block 2
Block 3
Fig. Memory table in a paged system.
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4- bit Sequencecounter (SC)
Controllogicgates
I
11 - 012131415
Control outputs
D0
D7
.
.
.
T0
T15 ...
15 14 2 1 0
4 X 16decoder
7 6 5 4 3 2 1 0
Increment (INR)
Clear (CLR)
Clock
Instruction register (IR)
Other inputs
3 X 8decoder
Control Unit of basic computer
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Controladdressregister
Next address
generator(Sequencer)
Controlmemory(ROM)
Controldata
register
Externalinput
Controlword
Next address information
Fig. Microprogrammed control organization
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Instruction code
Mapping logic
Multiplexers
Control address register(CAR)
Control Memory
Branch logic
SubroutineRegister
(SBR)
Incrementer
Micro operations
Fig. Selection of address for control memory
Statusbits
MUXselect
Branch address
Select a status bit
Clock
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Chip select and read/write control
Port A dataregister
Port A controlregister
Bus buffers
Port B dataregister
Port B controlregister
Data bus
Inte
rna
l b
us
CS
RS1
RS2
RD
WR
Interrupt
Reset
0 x x None – data bus in high impedance
1 0 0 Port A data register
1 0 1 Port A control register
1 1 0 Port B data register
1 1 1 Port B control register
CS RS1 RS2 Register select
Fig. Block diagram of parallel peripheral interface.
I/O bus
Handshake lines
I/O bus
Handshake lines
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Chip select and read/write control
Transmitter Register
Controlregister
Bus buffers
Statusregister
Receiverregister
Inte
rna
l b
us
CS
RS
RD
WR
0 x x None
1 0 WR Transmitter register
1 1 WR Control register
1 0 RD Receiver register
1 1 RD Status register
CS RS Operation Register selected
Fig. Block diagram of a typical serial communication interface.
Data Bus
Reset
Shiftregister
Transmitter control and clock
Shiftregister
Receiver control and clock
Transmit
clock
Transmitter
data
clock
data
Receiver
Receive
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Chip select and read/write control
Address bus buffers
Addressregister
Data bus buffers
Byte countregister
Controlregister
Inte
rna
l b
us
CS
RS1
RS2
WR
RD
Fig. Block diagram of DMA controller
Data Bus
Reset
DMA request
DMA Acknowledge
Read / write
Address bus
Interrupt
BR
BG
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R1
R3 R4
R2
R5
Multiplier
Adder
Ai Bi
Fig. Example of parallel processing
Ci
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Chip select and read/write control
Transmitter Register
Controlregister
Bus buffers
Statusregister
Receiverregister
Inte
rna
l b
us
CS
RS
RD
WR
0 x x None
1 0 WR Transmitter register
1 1 WR Control register
1 0 RD Receiver register
1 1 RD Status register
CS RS Operation Register selected
Fig. Block diagram of a typical serial communication interface.
Data Bus
Reset
Shiftregister
Transmitter control and clock
Shiftregister
Receiver control and clock
Transmit
clock
Transmitter
data
clock
data
Receiver
Receive
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Clock Segment1 Segment2 Segment3pulse number R1 R2 R3 R4 R5
1 A1 B1
2 A2 B2 A1 * B1 C1
3 A3 B3 A2 * B2 C2 A1 * B1 + C1 4 A4 B4 A3 * B3 C3 A2 * B2 + C2
5 A5 B5 A4 * B4 C4 A3 * B3 + C3
6 A6 B6 A5 * B5 C5 A4 * B4 + C4
7 A7 B7 A6 * B6 C6 A5 * B5 + C5
8 A7 * B7 C7 A6 * B6 + C6
9 A7 * B7 + C7
Table: Content of registers in pipeline example
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R
R
R
R
R
R
R
R
Choose exponent
Compare exponentsby subtraction
Adjust exponent
Align mantissas
Add or subtractmantissas
Normalizeresult
Fig. Pipeline for floating-point addition and subtraction
a bExponentsA BMantissas
Segment 1:
Segment 2:
Segment 4:
Segment 3:
Difference
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B register
A register
Complementer andparallel adder
Sequence counter (SC)
Q register
As
Bs
Qs
E
Qn
(rightmost bit )
0
Fig. Hardware for multiply operation
multiplicand
multiplier
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Multiplcand in BMultiplier in Q
As Qs (+) Bs Qs Qs (+) Bs A 0, E 0
SC n-1
EA A + B
Shr EAQSC SC-1
END(product in reg A & Q)
Qn
SC
Fig. Flow chart for multiply algorithm
= 0 = 1
Not equal to zero = 0
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HA
C S
HA
C S
a0
a1
b1 b0
b1 b0
c3 c2 c1 c0
b1 b0 multiplicand
a1 a0 multiplier
a0 b1 a0 b0 1st Partial product a1 b1 a1 b0 2nd Partial product
c3 c2 c1 c0 Sum
Fig. 2-bit by 2-bit array multiplier
a0 b0a0 b1
a1 b1
a1 b0
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Addend Augend 4-bit adder
sum and output carry
Addend Augend 4-bit adder
sum and output carry
0
C6 C5 C4 C3 C2 C1 C0
Fig. 4-bit by 3-bit array multiplier
a0
a1
a2b3 b2 b1 b0
b3 b2 b1 b0
b3 b2 b1 b0
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Fetch instructionfrom memory
Decode instructionand calculate
effective address
Fetch operand from memory
Execute instruction
Interrupt handling
Update PC
Empty pipe
Branch
Interrupt?Yes
Yes
No
Segment : 1
Segment : 2
Segment : 3
Segment : 4
No
Fig. Four segment CPU pipeline
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Step : 1 2 3 4 5 6 7 8 9 10 11 12 13
Instruction: 1 FI DA FO EX
2 FI DA FO EX
(Branch) 3 FI DA FO EX
4 FI - - FI DA FO EX
5 - - - FI DA FO EX
6 FI DA FO EX
7 FI DA FO EX
Fig. Timing of instruction pipeline