8051 INTERFACING TO EXTERNAL MEMORY

Interrupt locations in the program memory

8051 Data memory map

On-chip and Off-chip Program Code Access

On-chip and off-chip code ROMIn such a system we still have EA = Vcc, meaning that upon reset the 8051 executes the on-chip program first; then, when it reaches the end of the on-chip ROM it switches to external ROM for the rest of the program cod

MEMORY ADDRESS DECODING

Logic gate as decoder

74LS138 decoder

74LS138 as Decoder

Find the address range for following (a) Y4 (b) Y2 (c) Y7 Using the 74LS138 3-8 decoder

8051 INTERFACING WITH EXTERNAL ROM

EA pin

Connect the EA pin to Vcc to indicate that the program code is stored in the mC's on-chip ROM.

To indicate that the program code is stored in external ROM, this pin must be connected to GND.

Program stored enable pin

74LS373 D Latch

P0 and P2 role in providing addresses

Address/Data Multiplexing

Data, Address, and Control Buses for the 8031

8031 Connection to External Program ROM

8051 Connection to External Data ROM

External ROM for dataFor the ROM containing the program code, PSEN is used to fetch the code. For the ROM containing data, the RD signal is used to fetch the data.

8031 Connection to External Data ROM and External Program ROM

8051 Connection to External Data RAM

A single external ROM for code and data

8031 system with ROM and RAM

8051 Accessing 256Kx8 External NV-RAM

8051 accessing 256 K 8 external NV – RAM

Example 1• Design a 8051 system with following specifications• (1) 8051 CPU working at 12 MHz• (2) 32 KB program memory (IC 2764) (8 KB)• (3) 16 KB data memory (IC 6264) (8 KB) • (4) 8255 PPI

• ROM Organization

Memory Map of EPROM

Example 1

Example 1

Memory map of RAM

Final design Implementation

Example 1

Example 2

• With neat schematic diagram show the interfacing of 8051 with following memory and I/O subsystem.

• (1) 32 KB SRAM (16 KB device)• (2) 32 KB EPROM (16 KB device)• (3) 8 LEDs with driver

Memory map for EPROM and RAM

ROM /RAM Organization

Decoder for ROM /RAM

Example 2

Example 2

Final design Implementation

Example 3• Design 8KB (4 KB ) of RAM and 4 KB EOROM with 8051. The starting

address of ROM is 8000H.

Example 3

Final design Implementation

• The Flash program memory supports both parallel programming and in serial In-System Programming (ISP).

• Parallel programming mode offers gang-programming at high speed, reducing programming costs and time to market.

• ISP allows a device to be reprogrammed in the end product under software control.

• The capability to field/update the application firmware makes a wide range of applications possible.

• The P89V51RD2 is also In-Application Programmable (IAP), allowing the Flash program memory to be reconfigured even while the application is running.

• Program Store Enable: PSEN is the read strobe for• external program memory. When the device is executing• from internal program memory, PSEN is inactive• (HIGH). When the device is executing code from• external program memory, PSEN is activated twice each• machine cycle, except that two PSEN activations are• skipped during each access to external data memory. A• forced HIGH-to-LOW input transition on the PSEN pin• while the RST input is continually held HIGH for more• than 10 machine cycles will cause the device to enter• external host mode programming.