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XAPP1301 (v1.2) February 28, 2018 1www.xilinx.com

SummaryThis application note describes specifications, guidelines, and best practices for using the UltraScale+™ FPGAs with the FSGD2104 and FIGD2104 lidless packages.

IntroductionDue to the ever-growing size, performance, and complexity of modern FPGA designs, power density has steadily increased from generation to generation, making thermal management increasingly challenging. In response, Xilinx has been investing in new packaging technology to reduce device thermal resistance, allowing for increased power dissipation in the same thermal environment without increasing junction temperature. The FSGD2104 and FIGD2104 packages (referred to collectively as D2104) in UltraScale+™ FPGAs are an innovative lidless packaging design targeting the largest Xilinx 16nm FinFET stacked silicon interconnect (SSI) technology devices, allowing for up to 10°C cooler operation at the same power dissipation.

For these packages, component thermal management must be carefully designed to obtain optimum device performance while guaranteeing long-term component reliability. Due to the wide range of mechanical designs available for different applications, it is necessary to design system-level thermal simulation to analyze the thermal interaction of the components for a specific chassis.

To facilitate system-level thermal design and analysis, this application note describes thermal models of the XCVU13P, XCVU11P, and XCVU9P FPGAs in the D2104 package. These thermal models can be incorporated in system-level thermal models and analyzed using computational fluid dynamics (CFD) simulation software (e.g., IcePak and FloTHERM). They are created using the above mentioned simulation software packages and are ready for use.

Precise mechanical design is vital to optimum device performance. Often, these devices must be subjected to severe mechanical shock and vibration tests. Without good mechanical design, they will not meet these rigorous requirements. To maintain good contact between heat sinks and the FPGA, innovative designs have been implemented to ensure maximum thermal performance.

This document presents unique thermal and mechanical designs and requirements for these devices. The reference designs were performed using SOLIDWORKS and are available in Reference Design.

Application Note: UltraScale+, FPGAs

XAPP1301 (v1.2) February 28, 2018

Mechanical and Thermal Design Guidelines for the UltraScale+ FPGA D2104 Lidless Flip-Chip PackagesAuthor: Brian Philofsky, Gamal Rafai-Ahmed, and Ivor Barber

http://www.xilinx.com

Traditional Flip-Chip Package vs. Lidless Flip-Chip


Traditional Flip-Chip Package vs. Lidless Flip-ChipXilinx offers flip-chip BGA packages, which exhibit a low-resistance thermal path to allow adequate cooling of the devices. These packages incorporate a heat spreader lid with additional thermal interface material (TIM1), as shown in Figure 1.

Materials with high thermal conductivity and consistent process applications deliver low thermal resistance up to the heat spreader. A parallel effort to ensure optimized package electrical return paths produces the added benefit of an enhanced power and ground plane arrangement in the package. A boost in copper density on the planes improves the overall thermal conductivity through the laminate. The extra density and distribution via fields in the package also increases the vertical thermal conductivity.

The lidless packaging (see Figure 2) offers the same package substrate design and thus the same electrical and board thermal conductivity as traditional flip-chip packaging. However, removing the lid (heat spreader) and the TIM1 material allows direct contact between the external heat sink and the die. This further reduces the thermal resistance, exhibiting improved thermal behaviors. It also facilitates the use of custom passive or active heat sink designs incorporating two-phase cooling methods directly adjacent to the source of the dissipated heat on the die, allowing for a more efficient means of removing the heat from the IC. Consequently, the device can operate in higher ambient temperature environments, area-constrained surroundings, and/or higher power operations than previously.

X-Ref Target - Figure 1

Figure 1: Heat Spreader with Thermal Interface Material


Figure 2: Lidless Flip-Chip Package Diagram


Package Mechanical Specifications


Package Mechanical Specifications

Package Mechanical DescriptionThe FPGAs packaged in the D2104 flip-chip ball grid array (FCBGA) package are soldered directly to a PCB surface. The package size is nominally 52.5 mm x 52.5 mm in the XCVU13P configuration and 47.5 mm x 47.5 mm in the XCVU9P and XCVU11P combinations with a ball pitch of 1.0 mm. One of the unique features of the D2104 package is the addition of a stiffener ring around the periphery of the package substrate, providing additional package rigidity and helping to improve the overall package coplanarity (flatness). It also serves as a guide for the heat sink solution applied to the device.

Package Mechanical DrawingsDetailed mechanical drawings are available for the D2104 packages in Xilinx Product Specification UltraScale and UltraScale+ FPGAs Packaging and Pinouts (UG575) [Ref 1]. Refer to this document for the precise mechanical specification of the package.

FPGA Component Keep-Out ZonesIn the FCBGA package, capacitors can be placed in the area surrounding the FPGA die. The die-side capacitors, which are only slightly shorter than the die height, might be electrically conductive so contact with electrically conductive materials must be avoided. A thermal and mechanical solution design must not interfere with the package stiffener where it is higher than the die. Therefore, the thermal solution must have an island, as shown in the heat sink reference design.

Thermal Management StrategyExceptional thermal management starts with good package design. However, it only comes to fruition with a well-designed heat sink solution to accompany it.

Heat Sink Solutions at the System LevelTaking into consideration the system's physical, mechanical, and environmental constraints, the overall thermal budget must be maintained so that it does not exceed the device’s maximum operating temperature. The heat sink is an integral, if not the most important, part of the thermal management solution to maintain a safe operating temperature. As a result, the following are important:

• ΘJC parameters from UltraScale and UltraScale+ FPGAs Packaging and Pinouts (UG575) [Ref 1] must not be directly used to determine the thermal performance of the device application. These parameters are calculated according to JEDEC JESD51 standards, where system parameters differ greatly from most applications. Instead, run system thermal


Thermal Management Strategy


simulations in worst-case environmental conditions using the DELPHI thermal models, which more accurately represent the device thermal performance under all boundary conditions.

• Consider the mechanical specifications of the package, as well as selecting the best thermal interface between the die and the thermal management solution to ensure the lowest thermal contact resistance.

The XCVU13P-D2104 is used in the following example:

° The nominal stiffener height on the package is higher than the die by 1.1 mm. Therefore, the heat sink must have an island to contact the SSI die.

Dimensional properties of XCVU13P-D2104 contact island:

Width = 34 mm

Length = 42 mm

Height = 1.5 mm

Flatness: < 75 µm

Surface roughness = 3~5 µm

See the XCVU13P-D2104 heat sink Reference Design for more information.

This island has TIM coverage of 31.5 x 33.5 mm, such as PCM780SP from Laird or PTM6500D from Honeywell.

• The total thermal contact of the thermal interface material is based on the above parameters from the thermal interface supplier’s data sheet.

• The applied pressure on the package must be in the range of 20–40 PSI. Lower pressure risks poor thermal contact and higher pressure risks damaging the device.

• Consider all uncertainties in modeling with the above factors plus the thermal solution’s manufacturing variations (e.g., fan airflow tolerance, heat pipe performance tolerance, variation of the attachment of fins to heat sink base, as well as surface flatness).




Figure 3 reveals the PCM780SP coverage after 1000 Thermal BLR Cycles for 0°C to 100°C. The package passed 5000 Thermal cycles without any failure.

The reference design file includes heat sink design examples with CAD files, to assist in designing heat sinks for these packages. Figure 4 through Figure 6 are examples of heat sink designs.


Figure 3: Example of Heat Sink for VU13P-D2104 with PCM780SP




The Heat Pipe with Etching Design for XCVU11P-D2104 is available from supplier NTK (HK) LIMITED with P/N 19020000009.


Figure 4: Example of Heat Sink (Heat Pipe with Etching) Design for XCVU11P-D2104




The Heat Pipe with Etching Design for XCVU9P-D2104 is available from supplier NTK (HK) LIMITED with P/N 19020000010.






The Heat Pipe with Etching Design HSP0017 for the XCVU13P-D2104 is available from supplier NTK (HK) LIMITED with P/N 19020000011.

NTK (HK) LIMITED’s contact information can be found through the Xilinx support website at:

https://www.xilinx.com/support/answers/68150.html




https://www.xilinx.com/support/answers/68150.html

Thermal Simulation and the Use of Thermal Models


Xilinx recommends that the applied pressure on the package be in the approximate range of 20 to 40 PSI for optimum performance of the thermal interface material (TIM) between the package and the heat sink. See the below equations to determine the pressure. Contact Xilinx for additional considerations if you are using a different applied pressure. Thermocouples should not be present between the package and the heat sink, as their presence degrades the thermal contact and results in incorrect thermal measurements. To determine the appropriate applied pressure, use the following equation:

The applied pressure (PSI)= 15N/A

Where:

• N is the BGA number.

• A is the contact area of the package and the heat sink in mm2.

Thermal Simulation and the Use of Thermal Models Xilinx offers and supports a suite of integrated device power analysis tools to help users quickly and accurately estimate their design power requirements. Download and fill out the latest version of the Xilinx Power Estimator (XPE) from http://www.xilinx.com/power. The variability of design power requirements makes it difficult to apply predetermined thermal solutions to fit all users. The estimated power of the device via XPE coupled with your operating conditions and system constraints dictate the appropriate solution.

Xilinx recommends using the DELPHI thermal model during thermal modeling of the system. Do not use a 2-resistor model for thermal simulation and design, which is less precise and accurate compared to the DELPHI model. Detailed models might consume more simulation memory and runtime during use. The user of the thermal model needs to consider thermal sensor accuracy, thermal interface material parameters, and potential manufacturing variations. Examples of manufacturing variations include:

• Fan airflow tolerance.

• Heat pipe performance tolerance.

• Fin attachment to the heat-sink base.

• Surface flatness.


http://www.xilinx.com/power



Detailed ModelThe detailed thermal model is a direct representation of the device and package. This model provides geometric details describing the packaging, specifically in regards to the lid, TIM, die, under fill, substrate, and solder balls or leads. Each specific component in the detail model has associated material properties. Due to the computationally intensive nature of this model, do not use it early in thermal management development when several iterations might be needed to find the solution. Instead, use it at the end of the development cycle to finalize the system’s thermal margin.

DELPHI ModelTable 1 through Table 3 show the thermal resistances for the devices using the D2104 packaging. The DELPHI model seeks to capture the thermal behavior of the packages more accurately at predetermined critical points (junction, case, top, leads, and so on) with the reduced set of nodes. Unlike a full 3D model, these are computationally efficient and work well in an integrated system simulation environment. The DELPHI model is more appropriate for estimating the value of the thermal solution in the early stages of a design.

The DELPHI model is available on the Xilinx support download center (under Model Type, see Package Thermal Models) at:

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models.html

Thermal Resistance ParametersTable 1: XCVU13P-D2104 DELPHI Thermal Resistance Values (°C/watt)

Top Inner Bottom Inner Top Outer Bottom Outer Side

Junction 0.003 0.38 ∞ 1.68 100.00

Top Inner ∞ ∞ ∞ ∞

Bottom Inner ∞ 4.29 3.6

Top Outer ∞ ∞

Bottom Outer ∞

Table 2: XCVU11P-D2104 DELPHI Thermal Resistance Value (°C/watt)


Junction 0.004 0.39 ∞ 5.38 225.00

Top Inner ∞ ∞ 135.18 ∞

Bottom Inner ∞ 17.79 ∞

Top Outer ∞ ∞

Bottom Outer 1.44


http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models.html



The DELPHI model is available precompiled in both Ansys IcePak and Mentor FloTHERM. If using a different thermal modeling tool, the DELPHI model can be constructed using the above thermal resistances. These thermal resistances must be in a block with the structure shown in Figure 7 and the dimensions specified in Table 4.

The bottom inner area is shown in Figure 8 and the dimensions are specified in Table 5.

Table 3: XCVU9P-D2104 DELPHI Thermal Resistance Value (°C/watt)


Junction 0.003 0.40 ∞ 4.78 75.00

Top Inner ∞ ∞ 661.15 ∞

Bottom Inner ∞ 35.21 ∞

Top Outer ∞ ∞

Bottom Outer 1.43


Figure 7: The Top Inner Area Location in the Top Outer Area

Table 4: Top Inner and Top Outer Dimensions (mm)

Device Top Inner Top Outer Side

X Y X Y Z

XCVU13P-D2104 28.72 37.08 52.5 52.5 2.724

XCVU11P-D2104 28.72 27.78 47.5 47.5 2.724

XCVU9P-D2104 25.55 34.44 47.5 47.5 2.724

X18049-102616




For accurate results, ensure that the constructed model accurately represents the package, especially if the simulation tool is not FloTHERM or IcePak. The reported DELPHI model has better accuracy compared to the detail model versus solely the two-resistor model.

Table 6 shows the comparison between the detailed model and DELPHI Model for the XCVU11P-D2104.


Figure 8: The Bottom Inner Area Location in the Bottom Outer Area

Table 5: Bottom Inner and Bottom Outer Dimensions (mm)

Bottom Inner Bottom Outer

X Y X Y

XCVU13P-D2104 30.07 38.82 52.5 52.5

XCVU11P-D2104 28.72 27.78 47.5 47.5

XCVU9P-D2104 25.56 34.46 47.5 47.5

Table 6: Comparison between the Detailed Model and Different DELPHI Model for XCVU11P-D2104

Boundary h (W/m2 K) Detailed Model DELPHI Model

Top Boundary 100 125.9°C 125.8°C

10000 1.8°C 1.8°C

Bottom Boundary 100 (ke = 0.78) 58.1°C 57.6°C

100 (ke = 9.6) 42.6°C 43.0°C

X18050-102616




Table 7 shows the comparison between the detailed model and DELPHI model for the XCVU9P-D2104.

Table 8 shows the comparison between the detail model and DELPHI model for the XCVU13P-D2104.

Two-Resistor Model

A two-resistor thermal model is not recommended. Instead, use a detailed representation for the most accurate results. For example, Table 9 reveals that with different thermal solutions, the heat spreading inside the package varies to different values. The same variation of RJB also occurs when the package is mounted in a PCB with different layers and the PCB has the means to dissipate its heat to the surrounding environment.

Table 9 shows the variation of RJC and RJB as functions of the surrounding conditions for three Virtex UltraScale+ devices. The reported RJC and RJB enable comparison of different packages under the same condition.

Note: In Table 9, the thermal resistance from junction to case is constant because the present package does not have a metal lid. The thermal resistance from junction to case does not change when the die is exposed to any external fluid cooling. Therefore, do not to place a thermocouple between the die and any surface it’s in contact with. This creates potentially poor thermal contact and can lead to the package overheating. Junction temperature values should be taken from SYSMON.




10000 1.6°C 1.6°C


100 (ke = 9.6) 42.5°C 42.9°C




10000 1.4°C 1.3°C


100 (ke = 9.6) 35.3°C 37.2°C

Table 9: Variation of RJC with Different External Thermal Solution by Customer

Device h (W/m2 K) 100 1000 5000 10000 JEDEC

XCVU13P-D2104 RJC 0.003 0.003 0.003 0.003 0.003

XCVU11P-D2104 RJC 0.004 0.004 0.004 0.004 0.004

XCVU9P-D2104 RJC 0.003 0.003 0.003 0.003 0.003




Table 10 shows the thermal resistance from junction to board, RJB, for three Virtex UltraScale+ devices.

The effective thermal conductivity of the PCB, ke, as referenced in Lemczyk et al. (1992)

Equation 1

The relation of RJB as a function of ke can be correlated as shown in Figure 9 through Figure 11:

For XCVU13P-D2104: RJB = 0.2564ke–0.154

Table 10: Variation of RJB with the Different External Thermal Solutions

Devices h (W/m2 K) Kx,y=25, Kz=0.4 Keffective=0.78

Kx,y=50, Kz=0.75 Keffective=1.48

Kx,y=90, Kz=1.5 Keffective=2.45

Kx,y=110, Kz=5 Keffective=9.6

XCVU13P-D2104 100 0.272 (modified JEDEC) 0.244 0.212 0.185




Figure 9: XCVU13P-D2104: The Relationship between RJB and ke

ke2 kxkz( )kx kz+---------------------=

ke

RJB

(C/W

) X

XX

0.300

0.280

0.260

0.240

0.220

0.200

0.180

0.160

0

(RJB based on modified JEDEC is 0.272)

RJB =0.2564ke-0.154

5 10 15 20 25 300.140

X

X20231-012318




For XCVU11P-D2104: RJB = 0.3063ke–0.157

For XCVU9P-D2104: RJB = 0.318ke–0.173





ke

RJB

(C/W

) X

X

X

0.360

X0.340

0.320

0.300

0.280

0.260

0.240

0.220

0.200

0.180

0.1600


RJB =0.3063ke-0.157

5 10 15 20 25 30

X20232-012318

ke

RJB

(C/W

)

X

X

X

0.360

X0.340

0.320

0.300

0.280

0.260

0.240

0.220

0.200

0.180

0.1600


RJB =0.318ke-0.173

5 10 15 20 25 30

X20233-012318


Example Heat Sink Thermal Performance for VU13P-D2104


Example Heat Sink Thermal Performance for VU13P-D2104Figure 12 through Figure 14 present graphical data extracted from experiments done with the VU13P-D2104 device.

The graph data in Figure 13 and Figure 14 was extracted from thermal simulations using the VU13P-D2104 package models with the heat sink solution shown above for a 150 Watt FPGA design. Using the first graph on the left in Figure 13, with an air flow rate of 30 CFM, the designer can calculate an effective thermal resistance of ~0.23°C/Watt. Using the second graph (Figure 13, on the right), the thermal solution operating at that airflow measures (at SYSMON) approximately 35°C above ambient, implying that the maximum ambient under these conditions can be as high as 65°C. Using an equivalent lidded package like the B2104 would yield a maximum ambient temperature of 58°C (7°C lower), as shown in the experiment data in Figure 14.


Figure 12: Thermal Map Above Ambient @ 30CFM

Thermal Map above ambient @ambient @ 30CFM 150W Design

Core 118.75 W

25W 25W

25W 25W

25W

25W

Core 218.75 W

25W 25W

25W 25W

25W 25W

25W 25W

Core 318.75 W

25W 25W

25W 25W

25W 25W

25W 25W

Core 418.75 W

25W 25W

25W 25W

25W 25W

25W 25W

X20234-012318


Figure 13: 150W Design

0.35

10

RH

S+T

IM2 (°

C/W

)

0.31

0.27

0.23

0.19

0.1520 30 40 50 60 70

50.0

0.16

Sys

Mon

Tem

pera

ture

(°C

)

45.0

40.0

35.0

30.0

25.00.32

RHS+TIM2 (°C/W) Flow Rate (CFM)

RHS+TIM2 = 0.808Flowrate-0.342

Lidless Package

Lidless Package

Lidless Package

Lidless Package

SysMon=153.69xRHS+TIM21.0777

X20235-022018

0.20 0.24 0.28


Removing Heat Sink Phase Change Material


• The following pad recommendations are listed in the “Recommended PCB Design Rules for BGA Packages” chapter of UltraScale and UltraScale+ FPGAs Packaging and Pinouts (UG575) [Ref 1]:

° PCB Pad Recommendations

° Pad Type Recommendations

° Solder Pad Recommendation

• Package Mechanical Loading Specifications

For this type of lidless FPGA packages, the thermal management solution applies a mechanical load on the SSI die to ensure good thermal contact without any negative mechanical impact on the package. Therefore, the necessary applied pressure to ensure thermal performance of the thermal interface material between the heat sink base and the FPGA SSI die is in the range of 20 to 40 psi.

Removing Heat Sink Phase Change MaterialIf heat sinks are removed or reworked, the phase change material residue must be removed from the die surface. Laird Technologies, Inc. has provided the following guidance for complete removal of the phase change material from the component.

Instructions: 1. Separate the Components

2. Scrape Away Thick Residue

3. Clean Remaining Residue with Solvent

4. First Aid


Figure 14: Experimental Comparison between Lid and Lidless Devices

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.110 20 30 40 50 60 70

Lidless LID-PART Heat sink with heat pipesDimensions: 90x90x27mmBase thickness: 4.5mmFin Thickness is 0.16mmFin number is 72

92W 100W

RJ-A = 2.311CFM-0.645RJ-A = 2.3549CFM-0.599

CFM

Rj-a

X20236-012318


Removing Heat Sink Phase Change Material


Separate the Components

At room temperature, use a back and forth twisting motion to break the bond between the phase change TIM and mated components (i.e., heat sink and CPU). See Figure 15.

For smaller components (typically 15 mm x 15 mm or less), the bond usually breaks free easily at room temperature. For larger components, situations where minimal movement is available, or if using fragile components, heat the component (preferable) or heat sink to between 40°C and 60°C before removal.

While the guideline is between 40°C and 60°C, you might find that heating to 35°C is adequate. Others might prefer to heat to 70°C so that the phase change TIM is very soft and the components are easy to separate.

Scrape Away Thick Residue

For a faster clean-up once components are separated, scrape away large amounts of residual material with a plastic spatula or a wooden tongue depressor. A clean dry rag also works well to wipe away excess material.

Clean Remaining Residue with Solvent

Using a clean cloth/wipe, wet it with one of the solvents below and wipe away any remaining residue.

• Toluene (best)

• Acetone (very good)

• Isoparaffinic hydrocarbon (trade names Isopar and Soltrol) (very good)

• Isopropyl alcohol (OK)


Figure 15: Breaking the Bond between TIM and Mated Components

Phase change

TIMHeat Sink

CPU


Measurement Debug


First Aid

Safe handling, disposal, and first aid measures for PCM780SP are included in the Laird Technologies MSDS. Read the MSDS before using or handling this product. It can be found on the Laird Technologies, Inc. website, www.lairdtech.com.

Measurement DebugWhen performing in-system thermal testing, to ensure accurate data and not incur damage to the device, do not place a thermocouple in between the die and the heat sink. On the extreme side, it might cause additional mechanical and/or thermal stress to the die, leading to damage. Even if damage does not occur, it often leads to thicker and or uneven TIM thickness, leading to different thermal performance from a system without the thermocouple. To obtain the device temperature, use System Monitor (SYSMON) because it is an non-invasive means to get accurate die measurements while debugging the system.

Reference DesignDownload the reference design files for this application note from the Xilinx website.

Table 11 shows the reference design matrix.

Table 11: Reference Design Matrix

Parameter Description

General

Developer name Dino Fernandez

Target devices UltraScale+ D2104 Package

Source code provided Yes

Source code format SOLIDWORKS CAD Files

Design uses code and IP from existing Xilinx application note and reference designs or third party

No

Simulation

Functional simulation performed N/A

Timing simulation performed N/A

Test bench used for functional and timing simulations

N/A

Test bench format N/A

Simulator software/version used N/A

SPICE/IBIS simulations N/A

Implementation


http://www.lairdtech.com/

https://secure.xilinx.com/webreg/clickthrough.do?cid=474390

References


ReferencesThe following websites contain additional information on heat management and contact information:

1. UltraScale and UltraScale+ FPGAs Packaging and Pinouts (UG575)

2. UltraScale+ FPGAs - Package Thermal Models (Xilinx support)

Refer to the following websites for interface material sources:

1. Solidworks (www.solidworks.com)

2. Laird (www.lairdtech.com)

3. Honeywell (www.electronicmaterials.com)

4. Henkel (www.henkel.com)

5. Bergquist Company (www.bergquistcompany.com)

6. AOS Thermal Compound (www.aosco.com)

7. Chomerics (www.chomerics.com

8. Kester (www.kester.com)

Refer to the following websites for CFD tools that Xilinx supports with thermal models:

1. Mentor (FloTHERM)

2. ANSYS (IcePak)

Synthesis software tools/versions used N/A

Implementation software tools/versions used

N/A

Static timing analysis performed N/A

Hardware Verification

Hardware verified Yes

Hardware platform used for verification D2104 Test Board

Table 11: Reference Design Matrix (Cont’d)

Parameter Description


http://www.chomerics.com/

https://www.xilinx.com/support/documentation/user_guides/ug575-ultrascale-pkg-pinout.pdf

http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/package-thermal-models/utrascale-plus-fpgas.html

http://www.solidworks.com

http://www.lairdtech.com/

https://www.electronicmaterials.com/

www.bergquistcompany.com

http://www.kester.com/

www.aosco.com

https://www.henkel.com

https://www.mentor.com/products/mechanical/flotherm/

www.ansys.com

Revision History


Refer to the following papers on thermal modeling:

1. Lemczyk, T.F., Mack, B., Culham, J.R. and Yovanovich, M.M., 1992, “Printed Circuit Board Trace Thermal Analysis and Effective Conductivity,” ASME J. Electronic Packaging, Vol. 114, pp. 413 - 419.

2. Refai-Ahmed, G. and Karimanal, K., 2003, “Validation of Compact Conduction Models of BGA Under Realistic Boundary,” J. of Components and Packaging Technology, Vol. 26, No. 3, pp. 610-615.

3. Sansoucy, E, Refai-Ahmed, G., and Karimanal, K., 2002, “Thermal Characterization of TBGA Package for an integration in Board Level Analysis,” Eighth Intersociety on Thermal Conference Phenomena in Electronic Systems, San Diego., USA.

4. Karimanal, K. and Refai-Ahmed, G., 2002, “Validation of Compact Conduction Models of BGA Under Realistic Boundary Conditions,” Eighth Intersociety on Thermal Conference Phenomena in Electronic Systems, San Diego, USA.

5. Karimanal, K. and Refai-Ahmed, G., 2001, “Compact conduction Model (CCM) of Microelectronic Packages—a BGA Validation Study,” APACK Conference on Advance in Packaging, Singapore.

Revision HistoryThe following table shows the revision history for this document.

Date Version Revision

02/28/2018 1.2 Revised text and updated figures throughout document.

Minor editorial updates and clarifications.

08/22/2017 1.1 Updated figures.

01/09/2017 1.0 Initial Xilinx release.


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http://www.xilinx.com/legal.htm#tos

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