Measuring Network Performance of Multi-Core Multi-Cluster (MCMCA)

Norhazlina Hamid

nh3g11@ecs.soton.ac.uk

Supervisor: R J Walters and G B Wills

PUBLIC SERVICE DEPARTMENT OF MALAYSIA

Outline Introduction and Definition

Motivation

Related Work

Research Objectives

The Architecture

Methodology

Conclusion and Progress Work2

Introduction

The emergence of High Performance computing (HPC) that includes Cluster computing has improved the availability of powerful computers and high speed network technologies.

The implementation of multi-core cluster as a platform of high performance network will supports high availability and enables scalability of the networks.

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Definition

Multi-Core Multi-Cluster Architecture (MCMCA) is a collection of multiple multi-core cluster, interconnect by a network.

MCMCA are built from:

Cluster computing is a collection of computer, interconnect by a network which work together to form a single computer

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Definition

A multi-core cluster is a cluster where some or all the nodes in the cluster have multi-core processors

Multi-cluster architecture is a multiple cluster system that is connected via the cluster interconnection networks

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Motivation

Existing models do not address the potential performance of the interconnection networks within large-scale multi-core clusters .

A high communication latency of interconnection network can dramatically reduce the efficiency of the cluster system.

Scaling up by adding more processors to each cluster increase the processing power.

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Related Works

Furhad et al. (2013) proposed the EnMesh topology to address the issue of communication delays that occur with long distance communication within the remote nodes of a NoC.

Mohsen et al. (2013) proposed a new mapping technique to assign parallel processes into processing cores of a multi-core cluster which based on queuing network modelling of a limited-size cluster.7

Objectives

To propose a new architecture for multi-core multi-cluster.

To investigate the performance of interconnection networks of multi-core multi-cluster architecture.

To demonstrate the feasibility of the proposed architecture by computer simulation experiment and measurements.

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The Architecture of MCMCA

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Core Core

Cache Cache

Dual-Core Chip

Memory

Core Core

Cache Cache

Dual-Core Chip

Memory

Multi-cluster Network (MCN)

Intra-Cluster Network (ACN)

Core Core

Cache Cache

Dual-Core Chip

Memory

Core Core

Cache Cache

Dual-Core Chip

Memory

Inter-Cluster Network (ECN)

Key:Intra-Chip :Inter-Chip :Intra-Cluster Network :Inter-Cluster Network : Multi-Cluster Network:

Inter-ChipIntra-Chip

Extended Multi-core Cluster System Architecture (EMCSA)

Intra-Chip Inter-Chip

Cluster 0

Core Core

Cache Cache

Dual-Core Chip

Memory

Core Core

Cache Cache

Dual-Core Chip

Memory

Intra-Cluster Network (ACN)

Core Core

Cache Cache

Dual-Core Chip

Memory

Core Core

Cache Cache

Dual-Core Chip

Memory

Inter-Cluster Network (ECN)

Inter-ChipIntra-ChipIntra-Chip Inter-Chip

Cluster 1

Communication Network

There are five communication networks in MCMCA1. IntrA-chip Communication network (AC)2. IntEr-chip Communication network (EC)3. IntrA-Cluster Network (ACN)4. IntEr-Cluster Network (ECN)5. Multi-Cluster Network (MCN)

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IntrA-chip Communication network (AC)

11Message passing between two processor cores on

the same chip

IntEr-chip Communication network (EC)

12Message passing across processors on

different chips but within a node

IntrA-Cluster Network (ACN)

13Message passing between processors on

different nodes but within the same cluster

Communication Network

14Message passing between clusters

Methodology Computer simulation experiments using

OMNeT network simulation tool.

Focus on network latency to measure the performance.

Early stage experiments are based on a single-core multi-cluster architecture.

The experiments have been performed using given configuration and parameters of previous paper to create baseline results.

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Experiment Results Results from the experiments have shown that as the

traffic rate increases, the average communication latency increases following the assumptions that the messages are delayed by having to wait for resources before traversing into a network.

The results confirm that the simulation model is a good basis to measure the communication latency for a large-scale cluster, and can be extended to multi-core multi-cluster architecture.

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Methodology Network Latency (∑NL) are obtained from:– Total Network Latency of Message Passing

Within Cluster (L) – Total Network Latency of Message Passing

Between Clusters (L)– Probability of outgoing message in a cluster

(P)– Probability of message in a cluster (1-P)

Analytical Formula:

∑NL = (L x (1-P)) + (L x P)17

Methodology Both Network Latency (L and L) are obtained

from:– Waiting time at the source node (W)– Delay while traversing the network(D)– Time for each packet to reach its destination node

(E)– Waiting time at transfer switch between clusters

(Wts)

Analytical Formula:L = W + D + E

L = W + D + E + 2Wts

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Conclusion

Presenting a new architecture for measuring the performance of interconnection networks in MCMCA.

Progress work:1. Developing a MCMCA simulation model.2. Conduct a simulation experiments with

different network technology and bandwidth.

3. Developing analytical equation for the architecture.

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Published Paper1. Hamid, Norhazlina, Walters, Robert John and Wills, Gary

Brian (2014) Performance evaluation of multi-core multi-cluster architecture. In, Emerging Software as a Service and Analytics, Barcelona, ES,03 - 05 Apr 2014. Scitepress9pp, 46-54.

2. Hamid, Norhazlina, Walters, Robert John and Wills, Gary Brian, " An Architecture for Measuring Network Performance in Multi-Core Multi-Cluster Architecture (MCMCA). In, Euro-Asia Conference on Computational Intelligence and Communication Networks, Antalya, Turkey, 21-23 Apr 2014."

3. Hamid, Norhazlina, Walters, Robert John and Wills, Gary Brian, " An Architecture for Measuring Network Performance in Multi-Core Multi-Cluster Architecture (MCMCA)," International Journal of Computer Theory and Engineering vol. 7, no. 1, pp. 57-61, February 2015.

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Q & A

Thank you.

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