measurement and modelling of specific behaviors in 28nm fd ... · nosh sh vd = 50 mv … 1 v sh –...

D. Flandre, UCL / ICTEAM MOS-AK Workshop, Leuven, 11 Sept. 2017

Denis Flandre, Valeriya Kilchytska, Cecilia Gimeno, David Bol, Babak Kazemi Esfeh, Jean-Pierre Raskin

Measurement and modelling of specific behaviors in 28nm FD SOI UTBB MOSFETs of importance for

analog / RF amplifiers

ICTEAM Institute, Université catholique de Louvain Louvain-la-Neuve, Belgium


Context

q  VT adjustment q  Improved SCE control (suppression of SUB depletion)

FD-SOI: Unique Analog design opportunity

• New design opportunity by controlling analog device characteristics through back gate biasing techniques © Courtesy Ph. Flatresse, ST M, confidential

No pocket implant

Total dielectric isolation

No channel doping

FD-SOI

Body Bias: 85mV/V VTh adjust in FD-SOI

2

UTBB

→ Also better other analog performances ? And are they correctly modeled ?


Outline

ü  Context

ü  Analog / RF Figures of Merit :

from device assessment to circuit design at low frequency

ü  UTBB specificities & challenges

Back gate biasing & FoM variation with frequency

ü  Wideband RF amplifier

Non-linear performance

ü Conclusions

3


Analog / RF figures of merit

q  Transconductance gm q  Drive current, Id q  Output conductance, gd q  Early voltage, VEA (VEA=Id/gd) q  gm/Id ratio q  Gate capacitance, Cgg q  Parasitics (C, R)

Key-factors @ MOSFET-level Ø  fT = gm/(2·π·Cgg) Ø  fmax α fT, Rg Ø  Av0 = gm/gd = (gm/Id)·VEA ≠ const ( f )

@ IC (amplifier)-level Ø  GBW = gm/(2·π·CL) = = (gm/Id) ·(Id /(2·π·CL))

ð depends on

4


Methodology : device assessment & circuit design

q  independent on VT q  independent on L (except SCE) q  independent on Vsub

Allow fair comparison of different devices & at different conditions

L=30nmL=30nm

WI: ~1/SWI: ~1/S

SI: SI: µµ, n, n

10-12 10-10

Gm

/I d, V

-1

0

Normalized drain current, Id/(W/L), A10-8 10-6 10-4

10

20

30

RRsdsdvvsatsat

Vsub = - 2 → 2 V

Baseband applications (High gain, High precision)

High Frequency applications (High drive current)

V. Kilchytska et al. SSE 2012

L=30nmL=30nm

WI: ~1/SWI: ~1/SWI: ~1/SWI: ~1/S

SI: SI: µµ, n, n

10-12 10-10

Gm

/I d, V

-1

0

Normalized drain current, Id/(W/L), A10-8 10-6 10-4

10

20

30

RRsdsdvvsatsat

Vsub = - 2 → 2 V

Baseband applications (High gain, High precision)

High Frequency applications (High drive current)


√(2µCox/nIdnorm)

gm / Id vs Id,norm gm - Av Analog Metric

Intrinsic gain, Av0

g m/W

Vd=1 VVg=VTh+0.6 V

Intrinsic gain, Av0

g m/W

Vd=1 VVg=VTh+0.6 V

ShortShort--LL

LongLong--LL

SCE, Rsd

Intrinsic gain, Av0

g m/W

Vd=1 VVg=VTh+0.6 V

Intrinsic gain, Av0

g m/W

Vd=1 VVg=VTh+0.6 V

ShortShort--LL

LongLong--LL

SCE, Rsd

q  analogue of Ion– Ioff digital metric q  very visual q  independent of VT

5


Comparison of UTBB vs bulk

x 1.1 in SOI → (n/µ) / 1.2

6

gm / Id gd

gm/Id ~ 10 – 20 % and gd ~ 2 – 10 x better in UTTB than bulk

depending on length, bias, temperature and frequency conditions


Circuit validation at low frequency and power A Fully-Differential OTA in 28 nm UTBB FDSOI CMOS Harikumar et al, ECCTD 2015

DC open-loop gain (dB)40 50 60 70 80 90

Tota

l bia

s cu

rrent

(A)

10 -6

10 -5

BulkFD SOI

Harikumar

SPICE simulations

7


q  Vsub → “+” ð Id norm↑ of 5-10% (sign of µ ↑)

q  Vsub → “–” ð VEA ↑ (as a result of DIBL improvement) ð Gm/Id ↑ ↑ (at low Vg=Vd) (result of VT shift) ð one can win ~ 5 dB (in max Av range)

UTBB Specificities (1) : Effect of Vsub


⇒ Choice of Vsub “+” or “-” depends on targeted applications (either Id ↑ or Av ↑)

Vsub → “–” : S↓, DIBL↓, but VT ↑ ð Ion↓

Vsub → “+”: µ ↑ ð Gm max & Ion ↑ Trade-off for analog FoM ???

Vbg=0 V

Vbg=+1 V

Vbg=-1 V Vbg+ Vbg-

AV0 (dB) 20 24 28 32 36

g m/W

(mS/µm

)

0

0.4

0.8

1.2

1.6

↑↑↑↑↑↑↓↓--

↓↓↓↓↓↓↑↑++

AAv0v0ggmm/I/IddVVEAEAIIdd, g, gmmVVbgbg

↑↑↑↑↑↑↓↓--

↓↓↓↓↓↓↑↑++

AAv0v0ggmm/I/IddVVEAEAIIdd, g, gmmVVbgbg

8


gd (f) & gm (f) ⇒ Gain (f)

⇒  Performance prediction from DC data is insufficient ⇒  Quest for wide-f characterization ⇒  gm – Av analogue metric is strongly f-dependent:

gm ↑, gd ↑ ↑, Av ↓ with f↑

Frequency-dependent effects: Floating body, self-heating, substrate coupling, …

f↑

f↑

L↑ S parameters

VNA 40 kHz → 4 GHz

de-embedding

Sij → Yij conversion

gd = Re(Ydd)

S parametersVNA 40 kHz → 4 GHz

de-embedding

Sij → Yij conversion

gd = Re(Ydd)

S. Makovejev et al. ULSI 2014

9

UTBB Specificities (2) : Effect of frequency


⇒  GP allows to suppress SUB-related gd (f) variation ⇒  SH is the main reason of gd(f) variation

p-substrate

n n

G

pBOX

S D

SUB

p-substrate

n n

G

pBOX

S D

SUB

GP

gd(f) = gintr + Δgd_FB(f) + Δgd_SH(f) + Δgd_SUB(f)

noGP

with GP

S. Makovejev et al. ULSI 2014

10

UTBB Specificities (3) : Effect of self-heating (SH)

D. Flandre, UCL / ICTEAM MOS-AK Workshop, Leuven, 11 Sept. 2017 11

SH extraction using RF (S-param) method

• Rth in bulk lower than in FDSOI • Cth higher in bulk than in FDSOI due to larger Si volume available for generated heat • Temperature rise due to self-heating up to

~32 K in bulk and ~87 K in FDSOI

• In spite of stronger SH effect, FDSOI outperform bulk in terms of Analog FoM in entire frequency range • While thermal effects are stronger in FDSOI, their influence on device parameters is limited

gm - Av analogue metric

S. Makovejev et al. EuroSOI-ULIS 2015

( ) addLFdd

SHdth dTdIVgI

gR

_

_

+

Δ=

ddth VIRT =Δ

S. Makovejev et al. ULIS 2014

FDSOI

bulk

SH and its effect on Analog FoM in 28 FDSOI vs bulk

0 0.25 0.5 Power, mW/µm


Outline

12

ü  Context

ü  Analog / RF Figures of Merit :

from device assessment to circuit design at low frequency

ü  UTBB specificities & challenges

Back gate biasing & FoM variation with frequency

ü  Wideband RF amplifier

Non-linear performance

ü Conclusions


Wideband LNA

13

Crucial for efficient low-power multi-standard applications such as -  UWB (Ultra-Wide Band) -  SDR (Software-Defined Radio)

High gain up to 6 - 10 GHz + •  impedance matching •  noise figure •  linearity •  low area (inductorless)


Wideband inductor-less LNA

14

UTBB FD-SOI versus Bulk

Noise-cancelling Inductor-less architecture

With high linearity For 6 - 10 GHz

Software-Defined Radios In 28nm CMOS

!

G. De Streel et al. IEEE S3S Conf. 2015

C. Gimeno et al. IMS Conf. 2017


Non-linearity figures of merit

15

Noise floor

Pout

PinIIP3

OIP3

Pin, 1dB

1 dBPout, 1dB

Dyn

amic

rang

e (D

R)

Y = g1X + g2X2 + g3X

3Considering IIP3 of an amplifier in open loop is proportional to while in feedback

(g1 / g3)1/2

g3 − 2g22 / g1

with

Considering a memoryless circuit excited by a sinusoidal signal with AC amplitude A


Transconductance : Bulk vs UTBB SOI

16

q  Advantage of FDSOI is very clear in below–around – VTh

q  Vg >VTh+0.2 V ⇒ Bulk curves stretch out w.r.t FDSOI to higher Id and higher gm1

q  Contrarily FDSOI curves quasi-saturate with Vd↑

Normalized Drain Current, Id/(W/L) (µA) 0

10

20

30

40

50

Nor

mal

ized

Tra

nsco

nduc

tanc

e, g

m1/(

W/L

) (µ

S)

0 10 20 30

Vd=

Bulk

FDSOI Vd = 50 mV … 1 V

Rsd effect ???

q  RF measurements give : Rsd_FDSOI <Rsd_bulk

q  Id-Vd curves do not indicate higher Rsd in FDSOI

⇒ Not related to Rsd L=30 nm; W= 48.6 µm

V. Kilchytska et al. EUROSOI-ULIS 2017


Second-derivative gm2 : Experiments vs SPICE

17

q  Difference in the Vd behavior of FDSOI and Bulk devices is not well reproduced by Spice simulations

q  At low Vd: Spice curves agree well for both Bulk and FDSOI devices q With Vd ↑: discrepancy is rather strong in FDSOI device q  “Stretching” of bulk curves is well reproduced, but not “saturation” of FDSOI ones,

which in Spice simulations behave in the same way as bulk

Measurements Spice simulations


Silvaco ATLAS simulations : with SH or not

Normalized Drain Current, Id/(W/L) (µA) 0

10

20

30

40

50

Nor

m. T

rans

cond

ucta

nce,

gm

1/(W

/L)

(µS)

0 10 20

Vd=

noSH

SH Vd = 50 mV … 1 V

SH – solid lines noSH – dashed lines

Normalized Drain Current, Id/(W/L) (µA) 0 10 20

Vd=

noSH

SH

Vd = 50 mV … 1 V

SH – solid lines noSH – dashed lines

0

-5⋅10-5

5⋅10-5

1⋅10-4

Nor

mal

ized

2nd

I d d

eriv

ativ

e, g

m2/(

W/L

) strongly suggests that the experimental difference

in FDSOI vs Bulk is (at least partially) due to SH

V. Kilchytska et al. EUROSOI-ULIS 2017

Preliminary RF experiments show similar trend


Impact of back-gate bias on non-linearities

19

B. Kazemi et al. ESSDERC 2017 DC :

RF :


Wideband LNA SPICE simulations

20

Back-bias improvement also obtained in simulations over large process and temperature variations

C. Gimeno et al., IEEE S3S Conf. 2017


Conclusions ü Analog / RF FoM are excellent in FDSOI to design high-performance amplifiers (gain, bandwidth, power consumption) but specificities require cautious modeling (back bias, frequency, self-heating)

ü Non-linearities in FDSOI and Bulk MOSFETs compared by measurements and simulations :

Minimization at lower biases in FDSOI w.r.t bulk, which is beneficial for LP applications

Application of a positive back-gate (or body) bias in FDSOI allows for further non-linearity reduction

ü Next : noise ? (see L. Van Brandt ’s presentation in this workshop)


ACKNOWLEDGEMENTS

22

Research projects & Major partners : STM, LETI, IMEC…

WELCOME Characterization Platform (ELEN/ICTEAM/UCL):

https://sites.uclouvain.be/welcome/index.php

measurement and modelling of specific behaviors in 28nm fd ... · nosh sh vd = 50 mv … 1 v sh –...

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