mc9s08dz60

HCS08Microcontrollers

freescale.com

MC9S08DZ60MC9S08DZ48MC9S08DZ32MC9S08DZ16

Data Sheet

MC9S08DZ60Rev. 46/2008

8-Bit HCS08 Central Processor Unit (CPU)

40-MHz HCS08 CPU (20-MHz bus) HC08 instruction set with added BGND instruction Support for up to 32 interrupt/reset sources

On-Chip Memory

Flash read/program/erase over full operating voltage andtemperature MC9S08DZ60 = 60K MC9S08DZ48 = 48K MC9S08DZ32 = 32K MC9S08DZ16 = 16K

Up to 2K EEPROM in-circuit programmable memory;8-byte single-page or 4-byte dual-page erase sector;Program and Erase while executing Flash; Erase abort

Up to 4K random-access memory (RAM)Power-Saving Modes

Two very low power stop modes Reduced power wait mode Very low power real time interrupt for use in run, wait,

and stop

Clock Source Options

Oscillator (XOSC) Loop-control Pierce oscillator;Crystal or ceramic resonator range of 31.25 kHz to38.4 kHz or 1 MHz to 16 MHz

Multi-purpose Clock Generator (MCG) PLL andFLL modes (FLL capable of 1.5% deviation usinginternal temperature compensation); Internal referenceclock with trim adjustment (trimmed at factory, withtrim value stored in flash); External reference withoscillator/resonator options

System Protection

Watchdog computer operating properly (COP) resetwith option to run from backup dedicated 1-kHz internalclock source or bus clock

Low-voltage detection with reset or interrupt; selectabletrip points

Illegal opcode detection with reset Illegal address detection with reset Flash block protect Loss-of-lock protection

Development Support

Single-wire background debug interface On-chip, in-circuit emulation (ICE) with real-time bus capture

Peripherals

ADC 24-channel, 12-bit resolution, 2.5 sconversion time, automatic compare function,temperature sensor, internal bandgap reference channel

ACMPx Two analog comparators with selectableinterrupt on rising, falling, or either edge of comparatoroutput; compare option to fixed internal bandgapreference voltage

MSCAN CAN protocol - Version 2.0 A, B; standardand extended data frames; Support for remote frames;Five receive buffers with FIFO storage scheme; Flexibleidentifier acceptance filters programmable as: 2 x 32-bit,4 x 16-bit, or 8 x 8-bit

SCIx Two SCIs supporting LIN 2.0 Protocol andSAE J2602 protocols; Full duplex non-return to zero(NRZ); Master extended break generation; Slaveextended break detection; Wakeup on active edge

SPI Full-duplex or single-wire bidirectional;Double-buffered transmit and receive; Master or Slavemode; MSB-first or LSB-first shifting

IIC Up to 100 kbps with maximum bus loading;Multi-master operation; Programmable slave address;General Call Address; Interrupt driven byte-by-byte datatransfer

TPMx One 6-channel (TPM1) and one 2-channel(TPM2); Selectable input capture, output compare, orbuffered edge-aligned PWM on each channel

RTC (Real-time counter) 8-bit modulus counter withbinary or decimal based prescaler; Real-time clockcapabilities using external crystal and RTC for precisetime base, time-of-day, calendar or task schedulingfunctions; Free running on-chip low power oscillator(1 kHz) for cyclic wake-up without external components

Input/Output

53 general-purpose input/output (I/O) pins and 1input-only pin

24 interrupt pins with selectable polarity on each pin Hysteresis and configurable pull device on all input pins. Configurable slew rate and drive strength on all output

pins.

Package Options

64-pin low-profile quad flat-pack (LQFP) 10x10 mm 48-pin low-profile quad flat-pack (LQFP) 7x7 mm 32-pin low-profile quad flat-pack (LQFP) 7x7 mm

MC9S08DZ60 Series Features

MC9S08DZ60 Data SheetCovers MC9S08DZ60

MC9S08DZ48MC9S08DZ32MC9S08DZ16

MC9S08DZ60Rev. 46/2008

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc., 2007-2008. All rights reserved.

MC9S08DZ60 Series Data Sheet, Rev. 4

6 Freescale Semiconductor

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will bethe most current. Your printed copy may be an earlier revision. To verify you have the latest informationavailable, refer to:

http://freescale.com/

The following revision history table summarizes changes contained in this document.

Freescale Semiconductor, Inc., 2007-2008. All rights reserved.This product incorporates SuperFlash Technology licensed from SST.

RevisionNumber

RevisionDate Description of Changes

1 6/2006 Advance Information for alpha samples customers

2 9/2007 Product Launch. Removed the 64-pin QFN package. Changed from standard to extendedmode for MSCAN registers in register summary. Corrected Block diagrams for SCI.Updated the latest Temp Sensor information. Made FTSTMOD reserved. Updated deviceto use the ADC 12-bit module. Revised the MCG module. Updated the CPU Instruction Settable. Updated the TPM block module to version 3. Added the TPM block module version2 as an appendix for devices using 3M05C (or earlier) mask sets. Heavily revised theElectricals appendix.

3 10/2007 Removed two tables that were inadvertently included in the MC9S08DZ60 version of thebook.

4 6/2008 Sustaining update. Incorporated PS Issues # 2765, 3177, 3236, 3292, 3311, 3312, 3326,3335, 3345, 3382, 2795, 3382 and 3386 PLL Jitter Spec update. Also, added internalreference clock trim adjustment statement to Features page. Updated the TPM module tothe latest version. Adjusted values in Table A-13 Control Timing row 2 and in Table A-6 DCCharacteristics row 24 so that it references 5.0 V instead of 3.0 V.


Freescale Semiconductor 7

List of ChaptersChapter Title Page

Chapter 1 Device Overview ..............................................................................21Chapter 2 Pins and Connections.....................................................................27Chapter 3 Modes of Operation.........................................................................35Chapter 4 Memory.............................................................................................41Chapter 5 Resets, Interrupts, and General System Control..........................69Chapter 6 Parallel Input/Output Control..........................................................85Chapter 7 Central Processor Unit (S08CPUV3)............................................115Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) .............................135Chapter 9 Analog Comparator (S08ACMPV3) ..............................................167Chapter 10 Analog-to-Digital Converter (S08ADC12V1)................................173Chapter 11 Inter-Integrated Circuit (S08IICV2) ...............................................199Chapter 12 Freescale Controller Area Network (S08MSCANV1) ..................219Chapter 13 Serial Peripheral Interface (S08SPIV3) ........................................273Chapter 14 Serial Communications Interface (S08SCIV4).............................289Chapter 15 Real-Time Counter (S08RTCV1) ...................................................309Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) .................................319Chapter 17 Development Support ...................................................................347Appendix A Electrical Characteristics..............................................................369Appendix B Timer Pulse-Width Modulator (TPMV2) .......................................391Appendix C Ordering Information and Mechanical Drawings........................405



ContentsSection Number Title Page

Chapter 1Device Overview

1.1 Devices in the MC9S08DZ60 Series................................................................................................211.2 MCU Block Diagram .......................................................................................................................221.3 System Clock Distribution ...............................................................................................................24

Chapter 2Pins and Connections

2.1 Device Pin Assignment ....................................................................................................................272.2 Recommended System Connections ................................................................................................30

2.2.1 Power ................................................................................................................................312.2.2 Oscillator ...........................................................................................................................312.2.3 RESET ..............................................................................................................................312.2.4 Background / Mode Select (BKGD/MS) ..........................................................................322.2.5 ADC Reference Pins (VREFH, VREFL) ..............................................................................322.2.6 General-Purpose I/O and Peripheral Ports ........................................................................32

Chapter 3Modes of Operation

3.1 Introduction ......................................................................................................................................353.2 Features ............................................................................................................................................353.3 Run Mode.........................................................................................................................................353.4 Active Background Mode.................................................................................................................353.5 Wait Mode ........................................................................................................................................363.6 Stop Modes.......................................................................................................................................37

3.6.1 Stop3 Mode .......................................................................................................................373.6.2 Stop2 Mode .......................................................................................................................383.6.3 On-Chip Peripheral Modules in Stop Modes ....................................................................39

Chapter 4Memory

4.1 MC9S08DZ60 Series Memory Map ................................................................................................414.2 Reset and Interrupt Vector Assignments ..........................................................................................424.3 Register Addresses and Bit Assignments.........................................................................................444.4 RAM.................................................................................................................................................524.5 Flash and EEPROM .........................................................................................................................52

4.5.1 Features .............................................................................................................................52



Section Number Title Page

4.5.2 Program and Erase Times .................................................................................................534.5.3 Program and Erase Command Execution .........................................................................534.5.4 Burst Program Execution ..................................................................................................554.5.5 Sector Erase Abort ............................................................................................................574.5.6 Access Errors ....................................................................................................................584.5.7 Block Protection ................................................................................................................594.5.8 Vector Redirection ............................................................................................................594.5.9 Security .............................................................................................................................594.5.10 EEPROM Mapping ...........................................................................................................614.5.11 Flash and EEPROM Registers and Control Bits ...............................................................61

Chapter 5Resets, Interrupts, and General System Control

5.1 Introduction ......................................................................................................................................695.2 Features ............................................................................................................................................695.3 MCU Reset .......................................................................................................................................695.4 Computer Operating Properly (COP) Watchdog..............................................................................705.5 Interrupts ..........................................................................................................................................71

5.5.1 Interrupt Stack Frame .......................................................................................................725.5.2 External Interrupt Request (IRQ) Pin ...............................................................................725.5.3 Interrupt Vectors, Sources, and Local Masks ....................................................................73

5.6 Low-Voltage Detect (LVD) System .................................................................................................755.6.1 Power-On Reset Operation ...............................................................................................755.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................755.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................75

5.7 MCLK Output ..................................................................................................................................755.8 Reset, Interrupt, and System Control Registers and Control Bits ....................................................76

5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................775.8.2 System Reset Status Register (SRS) .................................................................................785.8.3 System Background Debug Force Reset Register (SBDFR) ............................................795.8.4 System Options Register 1 (SOPT1) ................................................................................805.8.5 System Options Register 2 (SOPT2) ................................................................................815.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................825.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................835.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................84

Chapter 6Parallel Input/Output Control

6.1 Port Data and Data Direction ...........................................................................................................856.2 Pull-up, Slew Rate, and Drive Strength............................................................................................866.3 Pin Interrupts ....................................................................................................................................87

6.3.1 Edge Only Sensitivity .......................................................................................................87




6.3.2 Edge and Level Sensitivity ................................................................................................886.3.3 Pull-up/Pull-down Resistors .............................................................................................886.3.4 Pin Interrupt Initialization .................................................................................................88

6.4 Pin Behavior in Stop Modes.............................................................................................................886.5 Parallel I/O and Pin Control Registers .............................................................................................89

6.5.1 Port A Registers ................................................................................................................906.5.2 Port B Registers ................................................................................................................946.5.3 Port C Registers ................................................................................................................986.5.4 Port D Registers ..............................................................................................................1016.5.5 Port E Registers ...............................................................................................................1056.5.6 Port F Registers ...............................................................................................................1086.5.7 Port G Registers ..............................................................................................................111

Chapter 7Central Processor Unit (S08CPUV3)

7.1 Introduction ....................................................................................................................................1157.1.1 Features ...........................................................................................................................115

7.2 Programmers Model and CPU Registers ......................................................................................1167.2.1 Accumulator (A) .............................................................................................................1167.2.2 Index Register (H:X) .......................................................................................................1167.2.3 Stack Pointer (SP) ...........................................................................................................1177.2.4 Program Counter (PC) ....................................................................................................1177.2.5 Condition Code Register (CCR) .....................................................................................117

7.3 Addressing Modes..........................................................................................................................1197.3.1 Inherent Addressing Mode (INH) ...................................................................................1197.3.2 Relative Addressing Mode (REL) ...................................................................................1197.3.3 Immediate Addressing Mode (IMM) ..............................................................................1197.3.4 Direct Addressing Mode (DIR) ......................................................................................1197.3.5 Extended Addressing Mode (EXT) ................................................................................1207.3.6 Indexed Addressing Mode ..............................................................................................120

7.4 Special Operations..........................................................................................................................1217.4.1 Reset Sequence ...............................................................................................................1217.4.2 Interrupt Sequence ..........................................................................................................1217.4.3 Wait Mode Operation ......................................................................................................1227.4.4 Stop Mode Operation ......................................................................................................1227.4.5 BGND Instruction ...........................................................................................................123

7.5 HCS08 Instruction Set Summary ...................................................................................................124

Chapter 8Multi-Purpose Clock Generator (S08MCGV1)

8.1 Introduction ....................................................................................................................................1358.1.1 Features ...........................................................................................................................137




8.1.2 Modes of Operation ........................................................................................................1398.2 External Signal Description ...........................................................................................................1398.3 Register Definition .........................................................................................................................140

8.3.1 MCG Control Register 1 (MCGC1) ...............................................................................1408.3.2 MCG Control Register 2 (MCGC2) ...............................................................................1418.3.3 MCG Trim Register (MCGTRM) ...................................................................................1428.3.4 MCG Status and Control Register (MCGSC) .................................................................1438.3.5 MCG Control Register 3 (MCGC3) ...............................................................................144

8.4 Functional Description ...................................................................................................................1468.4.1 Operational Modes ..........................................................................................................1468.4.2 Mode Switching ..............................................................................................................1508.4.3 Bus Frequency Divider ...................................................................................................1518.4.4 Low Power Bit Usage .....................................................................................................1518.4.5 Internal Reference Clock ................................................................................................1518.4.6 External Reference Clock ...............................................................................................1518.4.7 Fixed Frequency Clock ...................................................................................................152

8.5 Initialization / Application Information .........................................................................................1528.5.1 MCG Module Initialization Sequence ............................................................................1528.5.2 MCG Mode Switching ....................................................................................................1538.5.3 Calibrating the Internal Reference Clock (IRC) .............................................................164

Chapter 9Analog Comparator (S08ACMPV3)

9.1 Introduction ....................................................................................................................................1679.1.1 ACMP Configuration Information ..................................................................................1679.1.2 Features ...........................................................................................................................1699.1.3 Modes of Operation ........................................................................................................1699.1.4 Block Diagram ................................................................................................................170

9.2 External Signal Description ...........................................................................................................1709.3 Memory Map/Register Definition ..................................................................................................171

9.3.1 ACMPx Status and Control Register (ACMPxSC) .........................................................1719.4 Functional Description ...................................................................................................................172

Chapter 10Analog-to-Digital Converter (S08ADC12V1)

10.1 Introduction ....................................................................................................................................17310.1.1 Analog Power and Ground Signal Names ......................................................................17310.1.2 Channel Assignments ......................................................................................................17310.1.3 Alternate Clock ...............................................................................................................17410.1.4 Hardware Trigger ............................................................................................................17410.1.5 Temperature Sensor ........................................................................................................17510.1.6 Features ...........................................................................................................................177




10.1.7 ADC Module Block Diagram .........................................................................................17710.2 External Signal Description ...........................................................................................................178

10.2.1 Analog Power (VDDAD) ..................................................................................................17910.2.2 Analog Ground (VSSAD) .................................................................................................17910.2.3 Voltage Reference High (VREFH) ...................................................................................17910.2.4 Voltage Reference Low (VREFL) .....................................................................................17910.2.5 Analog Channel Inputs (ADx) ........................................................................................179

10.3 Register Definition .........................................................................................................................17910.3.1 Status and Control Register 1 (ADCSC1) ......................................................................17910.3.2 Status and Control Register 2 (ADCSC2) ......................................................................18110.3.3 Data Result High Register (ADCRH) .............................................................................18110.3.4 Data Result Low Register (ADCRL) ..............................................................................18210.3.5 Compare Value High Register (ADCCVH) ....................................................................18210.3.6 Compare Value Low Register (ADCCVL) .....................................................................18310.3.7 Configuration Register (ADCCFG) ................................................................................18310.3.8 Pin Control 1 Register (APCTL1) ..................................................................................18410.3.9 Pin Control 2 Register (APCTL2) ..................................................................................18510.3.10Pin Control 3 Register (APCTL3) ..................................................................................186

10.4 Functional Description ...................................................................................................................18710.4.1 Clock Select and Divide Control ....................................................................................18810.4.2 Input Select and Pin Control ...........................................................................................18810.4.3 Hardware Trigger ............................................................................................................18810.4.4 Conversion Control .........................................................................................................18810.4.5 Automatic Compare Function .........................................................................................19110.4.6 MCU Wait Mode Operation ............................................................................................19110.4.7 MCU Stop3 Mode Operation ..........................................................................................19210.4.8 MCU Stop2 Mode Operation ..........................................................................................192

10.5 Initialization Information ...............................................................................................................19310.5.1 ADC Module Initialization Example .............................................................................193

10.6 Application Information.................................................................................................................19510.6.1 External Pins and Routing ..............................................................................................19510.6.2 Sources of Error ..............................................................................................................196

Chapter 11Inter-Integrated Circuit (S08IICV2)

11.1 Introduction ....................................................................................................................................19911.1.1 Features ...........................................................................................................................20111.1.2 Modes of Operation ........................................................................................................20111.1.3 Block Diagram ................................................................................................................202

11.2 External Signal Description ...........................................................................................................20211.2.1 SCL Serial Clock Line ...............................................................................................20211.2.2 SDA Serial Data Line ................................................................................................202




11.3 Register Definition .........................................................................................................................20211.3.1 IIC Address Register (IICA) ...........................................................................................20311.3.2 IIC Frequency Divider Register (IICF) ...........................................................................20311.3.3 IIC Control Register (IICC1) ..........................................................................................20611.3.4 IIC Status Register (IICS) ...............................................................................................20711.3.5 IIC Data I/O Register (IICD) ..........................................................................................20811.3.6 IIC Control Register 2 (IICC2) .......................................................................................208

11.4 Functional Description ...................................................................................................................20911.4.1 IIC Protocol .....................................................................................................................20911.4.2 10-bit Address .................................................................................................................21311.4.3 General Call Address ......................................................................................................214

11.5 Resets .............................................................................................................................................21411.6 Interrupts ........................................................................................................................................214

11.6.1 Byte Transfer Interrupt ....................................................................................................21411.6.2 Address Detect Interrupt .................................................................................................21411.6.3 Arbitration Lost Interrupt ................................................................................................214

11.7 Initialization/Application Information ...........................................................................................216

Chapter 12Freescale Controller Area Network (S08MSCANV1)


12.2 External Signal Description ...........................................................................................................22212.2.1 RXCAN CAN Receiver Input Pin .............................................................................22212.2.2 TXCAN CAN Transmitter Output Pin .....................................................................22212.2.3 CAN System ...................................................................................................................222

12.3 Register Definition .........................................................................................................................22312.3.1 MSCAN Control Register 0 (CANCTL0) ......................................................................22312.3.2 MSCAN Control Register 1 (CANCTL1) ......................................................................22612.3.3 MSCAN Bus Timing Register 0 (CANBTR0) ...............................................................22712.3.4 MSCAN Bus Timing Register 1 (CANBTR1) ...............................................................22812.3.5 MSCAN Receiver Interrupt Enable Register (CANRIER) .............................................23112.3.6 MSCAN Transmitter Flag Register (CANTFLG) ..........................................................23212.3.7 MSCAN Transmitter Interrupt Enable Register (CANTIER) ........................................23312.3.8 MSCAN Transmitter Message Abort Request Register (CANTARQ) ...........................23412.3.9 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) .................23512.3.10MSCAN Transmit Buffer Selection Register (CANTBSEL) .........................................23512.3.11MSCAN Identifier Acceptance Control Register (CANIDAC) ......................................23612.3.12MSCAN Miscellaneous Register (CANMISC) ..............................................................23712.3.13MSCAN Receive Error Counter (CANRXERR) ............................................................238




12.3.14MSCAN Transmit Error Counter (CANTXERR) ..........................................................23912.3.15MSCAN Identifier Acceptance Registers (CANIDAR0-7) ............................................23912.3.16MSCAN Identifier Mask Registers (CANIDMR0CANIDMR7) .................................240

12.4 Programmers Model of Message Storage .....................................................................................24112.4.1 Identifier Registers (IDR0IDR3) ...................................................................................24412.4.2 IDR0IDR3 for Standard Identifier Mapping .................................................................24612.4.3 Data Segment Registers (DSR0-7) .................................................................................24712.4.4 Data Length Register (DLR) ...........................................................................................24812.4.5 Transmit Buffer Priority Register (TBPR) ......................................................................24912.4.6 Time Stamp Register (TSRHTSRL) .............................................................................249

12.5 Functional Description ...................................................................................................................25012.5.1 General ............................................................................................................................25012.5.2 Message Storage .............................................................................................................25112.5.3 Identifier Acceptance Filter .............................................................................................25412.5.4 Modes of Operation ........................................................................................................26112.5.5 Low-Power Options ........................................................................................................26212.5.6 Reset Initialization ..........................................................................................................26812.5.7 Interrupts .........................................................................................................................268

12.6 Initialization/Application Information ...........................................................................................27012.6.1 MSCAN initialization .....................................................................................................27012.6.2 Bus-Off Recovery ...........................................................................................................271

Chapter 13Serial Peripheral Interface (S08SPIV3)

13.1 Introduction ....................................................................................................................................27313.1.1 Features ...........................................................................................................................27513.1.2 Block Diagrams ..............................................................................................................27513.1.3 SPI Baud Rate Generation ..............................................................................................277

13.2 External Signal Description ...........................................................................................................27813.2.1 SPSCK SPI Serial Clock ............................................................................................27813.2.2 MOSI Master Data Out, Slave Data In ......................................................................27813.2.3 MISO Master Data In, Slave Data Out ......................................................................27813.2.4 SS Slave Select ...........................................................................................................278

13.3 Modes of Operation........................................................................................................................27913.3.1 SPI in Stop Modes ..........................................................................................................279

13.4 Register Definition .........................................................................................................................27913.4.1 SPI Control Register 1 (SPIC1) ......................................................................................27913.4.2 SPI Control Register 2 (SPIC2) ......................................................................................28013.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................28113.4.4 SPI Status Register (SPIS) ..............................................................................................28213.4.5 SPI Data Register (SPID) ................................................................................................283

13.5 Functional Description ...................................................................................................................284




13.5.1 SPI Clock Formats ..........................................................................................................28413.5.2 SPI Interrupts ..................................................................................................................28713.5.3 Mode Fault Detection .....................................................................................................287

Chapter 14Serial Communications Interface (S08SCIV4)

14.1 Introduction ....................................................................................................................................28914.1.1 SCI2 Configuration Information .....................................................................................28914.1.2 Features ...........................................................................................................................29114.1.3 Modes of Operation ........................................................................................................29114.1.4 Block Diagram ................................................................................................................292

14.2 Register Definition .........................................................................................................................29414.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................29414.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................29514.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................29614.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................29714.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................29914.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................30014.2.7 SCI Data Register (SCIxD) .............................................................................................301

14.3 Functional Description ...................................................................................................................30114.3.1 Baud Rate Generation .....................................................................................................30114.3.2 Transmitter Functional Description ................................................................................30214.3.3 Receiver Functional Description .....................................................................................30314.3.4 Interrupts and Status Flags ..............................................................................................30514.3.5 Additional SCI Functions ...............................................................................................306

Chapter 15Real-Time Counter (S08RTCV1)

15.1 Introduction ....................................................................................................................................30915.1.1 RTC Clock Signal Names ...............................................................................................30915.1.2 Features ...........................................................................................................................31115.1.3 Modes of Operation ........................................................................................................31115.1.4 Block Diagram ................................................................................................................312

15.2 External Signal Description ...........................................................................................................31215.3 Register Definition .........................................................................................................................312

15.3.1 RTC Status and Control Register (RTCSC) ....................................................................31315.3.2 RTC Counter Register (RTCCNT) ..................................................................................31415.3.3 RTC Modulo Register (RTCMOD) ................................................................................314

15.4 Functional Description ...................................................................................................................31415.4.1 RTC Operation Example .................................................................................................315

15.5 Initialization/Application Information ...........................................................................................316




Chapter 16Timer Pulse-Width Modulator (S08TPMV3)


16.2 Signal Description ..........................................................................................................................32416.2.1 Detailed Signal Descriptions ...........................................................................................324

16.3 Register Definition .........................................................................................................................32816.3.1 TPM Status and Control Register (TPMxSC) ................................................................32816.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................32916.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................33016.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................33116.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................333

16.4 Functional Description ...................................................................................................................33416.4.1 Counter ............................................................................................................................33516.4.2 Channel Mode Selection .................................................................................................337

16.5 Reset Overview ..............................................................................................................................34016.5.1 General ............................................................................................................................34016.5.2 Description of Reset Operation .......................................................................................340

16.6 Interrupts ........................................................................................................................................34016.6.1 General ............................................................................................................................34016.6.2 Description of Interrupt Operation ..................................................................................341

16.7 The Differences from TPM v2 to TPM v3.....................................................................................342

Chapter 17Development Support

17.1 Introduction ....................................................................................................................................34717.1.1 Forcing Active Background ............................................................................................34717.1.2 Features ...........................................................................................................................348

17.2 Background Debug Controller (BDC) ...........................................................................................34817.2.1 BKGD Pin Description ...................................................................................................34917.2.2 Communication Details ..................................................................................................35017.2.3 BDC Commands .............................................................................................................35417.2.4 BDC Hardware Breakpoint .............................................................................................356

17.3 On-Chip Debug System (DBG) .....................................................................................................35717.3.1 Comparators A and B ......................................................................................................35717.3.2 Bus Capture Information and FIFO Operation ...............................................................35717.3.3 Change-of-Flow Information ..........................................................................................35817.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................35817.3.5 Trigger Modes .................................................................................................................35917.3.6 Hardware Breakpoints ....................................................................................................361




17.4 Register Definition .........................................................................................................................36117.4.1 BDC Registers and Control Bits .....................................................................................36117.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................36317.4.3 DBG Registers and Control Bits .....................................................................................364

Appendix AElectrical Characteristics

A.1 Introduction ...................................................................................................................................369A.2 Parameter Classification ................................................................................................................369A.3 Absolute Maximum Ratings ..........................................................................................................369A.4 Thermal Characteristics .................................................................................................................370A.5 ESD Protection and Latch-Up Immunity ......................................................................................372A.6 DC Characteristics .........................................................................................................................373A.7 Supply Current Characteristics ......................................................................................................375A.8 Analog Comparator (ACMP) Electricals ......................................................................................376A.9 ADC Characteristics ......................................................................................................................376A.10 External Oscillator (XOSC) Characteristics .................................................................................380A.11 MCG Specifications ......................................................................................................................381A.12 AC Characteristics .........................................................................................................................383

A.12.1 Control Timing ...............................................................................................................383A.12.2 Timer/PWM ....................................................................................................................384A.12.3 MSCAN ..........................................................................................................................385A.12.4 SPI ...................................................................................................................................386

A.13 Flash and EEPROM ......................................................................................................................389A.14 EMC Performance .........................................................................................................................390

A.14.1 Radiated Emissions .........................................................................................................390

Appendix BTimer Pulse-Width Modulator (TPMV2)

B.0.1 Features ...........................................................................................................................391B.0.2 Block Diagram ................................................................................................................391

B.1 External Signal Description ...........................................................................................................393B.1.1 External TPM Clock Sources ..........................................................................................393B.1.2 TPMxCHn TPMx Channel n I/O Pins .......................................................................393

B.2 Register Definition .........................................................................................................................393B.2.1 Timer Status and Control Register (TPMxSC) ...............................................................394B.2.2 Timer Counter Registers (TPMxCNTH:TPMxCNTL) ...................................................395B.2.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL) ..................................396B.2.4 Timer Channel n Status and Control Register (TPMxCnSC) .........................................397B.2.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL) .........................................398

B.3 Functional Description ...................................................................................................................399B.3.1 Counter ............................................................................................................................399




B.3.2 Channel Mode Selection .................................................................................................400B.3.3 Center-Aligned PWM Mode ...........................................................................................402

B.4 TPM Interrupts ...............................................................................................................................403B.4.1 Clearing Timer Interrupt Flags .......................................................................................403B.4.2 Timer Overflow Interrupt Description ............................................................................403B.4.3 Channel Event Interrupt Description ..............................................................................404B.4.4 PWM End-of-Duty-Cycle Events ...................................................................................404

Appendix COrdering Information and Mechanical Drawings

C.1 Ordering Information ....................................................................................................................405C.1.1 MC9S08DZ60 Series Devices ........................................................................................405

C.2 Mechanical Drawings ....................................................................................................................405



Chapter 1Device OverviewMC9S08DZ60 Series devices provide significant value to customers looking to combine Controller AreaNetwork (CAN) and embedded EEPROM in their applications. This combination will provide lower costs,enhanced performance, and higher quality.

1.1 Devices in the MC9S08DZ60 SeriesThis data sheet covers members of the MC9S08DZ60 Series of MCUs:

MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16

Table 1-1 summarizes the feature set available in the MC9S08DZ60 Series.

Chapter 1 Device Overview



t

1.2 MCU Block DiagramFigure 1-1 is the MC9S08DZ60 Series system-level block diagram.

Table 1-1. MC9S08DZ60 Series Features by MCU and Pin Count

Feature MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16Flash size(bytes)

60032 49152 33792 16896

RAM size (bytes) 4096 3072 2048 1024EEPROM size(bytes)

2048 1536 1024 512

Pin quantity 64 48 32 64 48 32 64 48 32 48 32ACMP1 yesACMP2 yes yes1

1 ACMP2O is not available.

no yes yes1 no yes yes1 no yes1 noADC channels 24 16 10 24 16 10 24 16 10 16 10DBG yesIIC yesIRQ yesMCG yesMSCAN yesRTC yesSCI1 yesSCI2 yesSPI yesTPM1 channels 6 6 4 6 6 4 6 6 4 6 4TPM2 channels 2XOSC yesCOP Watchdog yes




Figure 1-1. MC9S08DZ60 Block Diagram

ANALOG COMPARATOR(ACMP1)

ACMP1OACMP1-ACMP1+

VSS

VDD IIC MODULE (IIC)

SERIAL PERIPHERAL INTERFACE MODULE (SPI)

USER Flash

USER RAM

MC9S08DZ60 = 60K

HCS08 CORE

CPU

BDC

6-CHANNEL TIMER/PWMMODULE (TPM1)

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTSMODES OF OPERATIONPOWER MANAGEMENT

VOLTAGEREGULATOR

COP

IRQ

LVD

OSCILLATOR (XOSC)

MULTI-PURPOSECLOCK GENERATOR

RESET

VREFL

VREFHANALOG-TO-DIGITALCONVERTER (ADC)

MC9S08DZ60 = 4K

24-CHANNEL,12-BIT

BKGD/MS

INTERFACE (SCI1)SERIAL COMMUNICATIONS

SDASCL

MISO

SSSPSCK

TxD1RxD1

XTALEXTAL

8

(MCG)

2-CHANNEL TIMER/PWMMODULE (TPM2)

REAL-TIME COUNTER (RTC)

DEBUG MODULE (DBG)

IRQ

PTA3/PIA3/ADP3/ACMP1OPTA4/PIA4/ADP4PTA5/PIA5/ADP5

PTA2/PIA2/ADP2/ACMP1-PTA1/PIA1/ADP1/ACMP1+PTA0/PIA0/ADP0/MCLK

PORT

A

PTA6/PIA6/ADP6PTA7/PIA7/ADP7/IRQ

MOSI

PTB3/PIB3/ADP11PTB4/PIB4/ADP12PTB5/PIB5/ADP13

PTB2/PIB2/ADP10PTB1/PIB1/ADP9PTB0/PIB0/ADP8

PORT

B

PTB6/PIB6/ADP14PTB7/PIB7/ADP15

PTC3/ADP19PTC4/ADP20PTC5/ADP21

PTC2/ADP18PTC1/ADP17PTC0/ADP16

PORT

C

PTC6/ADP22PTC7/ADP23

PTD3/PID3/TPM1CH1PTD4/PID4/TPM1CH2PTD5/PID5/TPM1CH3

PTD2/PID2/TPM1CH0PTD1/PID1/TPM2CH1PTD0/PID0/TPM2CH0

PORT

D

PTD6/PID6/TPM1CH4PTD7/PID7/TPM1CH5

PTE3/SPSCKPTE4/SCL/MOSIPTE5/SDA/MISO

PTE2/SSPTE1/RxD1PTE0/TxD1

PORT

EPTE6/TxD2/TXCANPTE7/RxD2/RXCAN

PTF3/TPM2CLK/SDAPTF4/ACMP2+PTF5/ACMP2-

PTF2/TPM1CLK/SCLPTF1/RxD2PTF0/TxD2

PORT

F

PTF6/ACMP2OPTF7

PTG1/XTALPTG2PTG3

PORT

G

PTG4PTG5

PTG0/EXTAL

VSS

VDD

VSSA

VDDA

BKP

INT

ANALOG COMPARATOR(ACMP2)

ACMP2OACMP2-ACMP2+

INTERFACE (SCI2)SERIAL COMMUNICATIONS TxD2

RxD2

NETWORK (MSCAN)CONTROLLER AREA

TXCANRxCAN

USER EEPROMMC9S08DZ60 = 2K

ADP7-ADP0

ADP15-ADP8ADP23-ADP16

6TPM1CH5 -

TPM2CH1,TPM2CH0

TPM2CLK

TPM1CLKTPM1CH0

- Pin not connected in 48-pin and 32-pin packages- Pin not connected in 32-pin package

- VREFH/VREFL internally connected to VDDA/VSSA in 48-pin and 32-pin packages- VDD and VSS pins are each internally connected to two pads in 32-pin package

MC9S08DZ48 = 48KMC9S08DZ32 = 32KMC9S08DZ16 = 16K




Table 1-2 provides the functional version of the on-chip modules.

1.3 System Clock DistributionFigure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clockinputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the modulefunction.

The following are the clocks used in this MCU: BUSCLK The frequency of the bus is always half of MCGOUT. LPO Independent 1-kHz clock that can be selected as the source for the COP and RTC modules. MCGOUT Primary output of the MCG and is twice the bus frequency. MCGLCLK Development tools can select this clock source to speed up BDC communications

in systems where BUSCLK is configured to run at a very slow frequency. MCGERCLK External reference clock can be selected as the RTC clock source. It can also be

used as the alternate clock for the ADC and MSCAN. MCGIRCLK Internal reference clock can be selected as the RTC clock source. MCGFFCLK Fixed frequency clock can be selected as clock source for the TPM1 and TPM2. TPM1CLK External input clock source for TPM1. TPM2CLK External input clock source for TPM2.

Table 1-2. Module Versions

Module VersionCentral Processor Unit (CPU) 3Multi-Purpose Clock Generator (MCG) 1Analog Comparator (ACMP) 3Analog-to-Digital Converter (ADC) 1Inter-Integrated Circuit (IIC) 2Freescales CAN (MSCAN) 1Serial Peripheral Interface (SPI) 3Serial Communications Interface (SCI) 4Real-Time Counter (RTC) 1Timer Pulse Width Modulator (TPM) 31

1 3M05C and older masks have TPM version 2.Debug Module (DBG) 2




Figure 1-2. MC9S08DZ60 System Clock Distribution Diagram

TPM1 TPM2 IIC SCI1 SCI2

BDCCPU ADC MSCAN FLASH

MCG

MCGOUT2

BUSCLK

MCGLCLK

MCGERCLK

COP

* The fixed frequency clock (FFCLK) is internallysynchronized to the bus clock and must not exceed one halfof the bus clock frequency.

Flash andEEPROM havefrequencyrequirements forprogram anderase operation.See theelectricalsappendix fordetails.

ADC has min andmax frequencyrequirements.Seethe ADC chapter andelectricals appendixfor details.

XOSC

EXTAL XTAL

EEPROM

SPI

FFCLK*MCGFFCLK

RTC1 kHZLPO

TPM1CLK TPM2CLK

MCGIRCLK

2 1

0

MCGFFCLKVALID



Chapter 2Pins and ConnectionsThis section describes signals that connect to package pins. It includes pinout diagrams, recommendedsystem connections, and detailed discussions of signals.

2.1 Device Pin AssignmentThis section shows the pin assignments for MC9S08DZ60 Series MCUs in the available packages.

Figure 2-1. 64-Pin LQFP

12345678910111213141516

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

48474645444342414039383736353433

64-PinLQFP


PTA6

/PIA

6/AD

P6PT

E2/S

S

PTC2/ADP18PTC5/ADP21PTA0/PIA0/ADP0/MCLKPTA7/PIA7/ADP7/IRQPTC1/ADP17PTC6/ADP22PTB0/PIB0/ADP8PTB7/PIB7/ADP15PTC0/ADP16PTC7/ADP23BKGD/MSVDDPTD7/PID7/TPM1CH5VSSPTD6/PID6/TPM1CH4PTG0/EXTALVDDPTG1/XTALVSSRESETPTF7PTF4/ACMP2+PTD5/PID5/TPM1CH3PTF5/ACMP2-PTD4/PID4/TPM1CH2PTF6/ACMP2OPTD3/PID3/TPM1CH1PTE0/TxD1PTD2/PID2/TPM1CH0PTE1/RxD1

PTB5

/PIB

5/AD

P13

PTE3

/SPS

CK

PTA5

/PIA

5/AD

P5PT

E4/S

CL/

MO

SIPT

C4/

ADP2

0PT

E5/S

DA/M

ISO

PTB4

/PIB

4/AD

P12

PTG

2PT

A4/P

IA4/

ADP4

PTG

3V D

DAPT

F0/T

xD2

V REF

HPT

F1/R

xD2

V REF

LPT

F2/T

PM1C

LK/S

CL

V SSA

PTF3

/TPM

2CLK

/SDA

PTA3

/PIA

3/AD

P3/A

CM

P1O

PTG

4PT

B3/P

IB3/

ADP1

1PT

G5

PTC

3/AD

P19

PTE6

/TxD

2/TX

CAN

PTA2

/PIA

2/AD

P2/A

CM

P1-

PTE7

/RxD

2/R

XCAN

PTB2

/PIB

2/AD

P10

PTD

0/PI

D0/

TPM

2CH

0PT

A1/P

IA1/

ADP1

/AC

MP1

+PT

D1/

PID

1/TP

M2C

H1

Chapter 2 Pins and Connections





PTA6

/PIA

6/AD

P6PT

E2/S

S

PTA0/PIA0/ADP0/MCLKPTA7/PIA7/ADP7/IRQPTB0/PIB0/ADP8PTB7/PIB7/ADP15BKGD/MSVDDPTD7/PID7/TPM1CH5VSSPTD6/PID6/TPM1CH4PTG0/EXTALVDDPTG1/XTALVSSRESET

PTF4/ACMP2+ PTD5/PID5/TPM1CH3PTF5/ACMP2- PTD4/PID4/TPM1CH2

PTD3/PID3/TPM1CH1PTE0/TxD1PTD2/PID2/TPM1CH0PTE1/RxD1

PTB5

/PIB

5/AD

P13

PTE3

/SPS

CK

PTA5

/PIA

5/AD

P5PT

E4/S

CL/

MO

SIPT

E5/S

DA/M

ISO

PTB4

/PIB

4/AD

P12

PTA4

/PIA

4/AD

P4V D

DA/V

REF

H

PTF0

/TxD

2PT

F1/R

xD2

PTF2

/TPM

1CLK

/SC

LV S

SA/V

REF

LPT

F3/T

PM2C

LK/S

DAPT

A3/P

IA3/

ADP3

/AC

MP1

OPT

B3/P

IB3/

ADP1

1PT

E6/T

xD2/

TXC

ANPT

A2/P

IA2/

ADP2

/AC

MP1

-PT

E7/R

xD2/

RXC

AN

PTB2

/PIB

2/AD

P10

PTD

0/PI

D0/

TPM

2CH

0

PTA1

/PIA

1/AD

P1/A

CM

P1+

PTD

1/PI

D1/

TPM

2CH

1

123456789101112

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

363534333231302928272625

48-Pin LQFP

VREFH and VREFL are internally connected to VDDA and VSSA, respectively.





RESET

1

2

3

4

5

6

7

8

VSS

PTG0/EXTAL

PTD

1/PI

D1/

TPM

2CH

1

PTD

0/PI

D0/

TPM

2CH

0

PTE7

/RxD

2/R

XCAN

PTE6

/TxD

2/TX

CAN

PTE5

/SDA

/MIS

O

PTE4

/SC

L/M

OSI

PTD3/PID3/TPM1CH1

PTD4/PID4/TPM1CH2

PTD5/PID5/TPM1CH3

BKGD/MS

PTA6

/PIA

6/AD

P6

PTA1

/AD

P1/A

CM

P+

PTB1/PIB1/ADP9

22

21

20

19

18

1710 11 12 13 14 15

25

9

24

32

PTE0/TxD1

PTE1/RxD1

16

PTD2/PID2/TPM1CH0

PTA2

/AD

P2/A

CM

P-

V SSA

/VR

EFL

26

V DDA

/VR

EFH

27

PTG1/XTAL

PTB0/PIB0/ADP8

23 PTA0/PIA0/ADP0/MCLK

PTA5

/PIA

5/AD

P5

31 30 29

PTA4

/PIA

4/AD

P4

28PTA7/PIA7/ADP7/IRQ

VDD

PTE2

/SS

PTE3

/SPS

CK

32-Pin LQFP

PTA3

/AD

P3/A

CM

PO

VREFH and VREFL are internally connected to VDDA and VSSA, respectively.




2.2 Recommended System ConnectionsFigure 2-4 shows pin connections that are common to MC9S08DZ60 Series application systems.

Figure 2-4. Basic System Connections (Shown in 64-Pin Package)

NOTES:1. External crystal circuit not

required if using theinternal clock option.

2. RESET pin can only beused to reset into usermode, you can not enterBDM using RESET pin.BDM can be entered byholding MS low duringPOR or writing a 1 toBDFR in SBDFR with MSlow after issuing BDMcommand.

3. RC filter on RESET pinrecommended for noisyenvironments.

4. For 32-pin and 48-pinpackages: VDDA and VSSAare double bonded toVREFH and VREFLrespectively.

PORTA

C2C1 X1

RF RS

PTA0/PIA0/ADP0/MCLK

PTA1/PIA1/ADP1/ACMP1+

PTA2/PIA2/ADP2/ACMP1-

PTA3/PIA3/ADP3/ACMP1O

PTA4/PIA4/ADP4

PTA5/PIA5/ADP5

PTA6/PIA6/ADP6

PTA7/PIA7/ADP7/IRQ

PORTB

PTB0/PIB0/ADP8

PTB1/PIB1/ADP9

PORTC

PORTD

PTD2/PID2/TPM1CH0

PTD3/PID3/TPM1CH1

PTD4/PID4/TPM1CH2

PTD5/PID5/TPM1CH3

PORTE

PORT

GPTG2

PTG3

PTG4

PTG5

PORT

F

IRQ

MC9S08DZ60

PTG0/EXTAL

PTG1/XTAL

PTF0/TxD2

PTF1/RxD2

PTF2/TPM1CLK/SCL

PTF3/TPM2CLK/SDA

PTF4/ACMP2+

PTF5/ACMP2

PTF6/ACMP2O

PTF7

PTE0/TxD1

PTE1/RxD1

PTE2/SS

PTE3/SPSCK

PTE4/SCL/MOSI

PTE5/SDA/MISO

PTE6/TxD2/TXCAN

PTE7/RxD2/RXCAN

PTD0/PID0/TPM2CH0

PTD1/PID1/TPM2CH1

PTB2/PIB2/ADP10

PTB3/PIB3/ADP11

PTB4/PIB4/ADP12

PTB5/PIB5/ADP13

PTB6/PIB6/ADP14

PTB7/PIB7/ADP15

PTC0/ADP16

PTC1/ADP17

PTC2/ADP18

PTC3/ADP19

PTC4/ADP20

PTC5/ADP21

PTC6/ADP22

PTC7/ADP23

PTD6/PID6/TPM1CH4

PTD7/PID7/TPM1CH5

CBY0.1 F

VREFH

VREFLVSSA

VDDA

VDD

VSS

CBY0.1 F

CBLK10 F

+5 V

+

SYSTEMPOWER

BKGD/MS

RESET

OPTIONALMANUALRESET

VDD

BACKGROUND HEADER

0.1 F

VDD

4.7 k10 k




2.2.1 PowerVDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to allI/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulatedlower-voltage source to the CPU and other internal circuitry of the MCU.

Typically, application systems have two separate capacitors across the power pins. In this case, thereshould be a bulk electrolytic capacitor, such as a 10-F tantalum capacitor, to provide bulk charge storagefor the overall system and a 0.1-F ceramic bypass capacitor located as near to the MCU power pins aspractical to suppress high-frequency noise. The MC9S08DZ60 Series has two VDD pins except on the32-pin package. Each pin must have a bypass capacitor for best noise suppression.

VDDA and VSSA are the analog power supply pins for the MCU. This voltage source supplies power to theADC module. A 0.1-F ceramic bypass capacitor should be located as near to the MCU power pins aspractical to suppress high-frequency noise.

2.2.2 OscillatorImmediately after reset, the MCU uses an internally generated clock provided by the multi-purpose clockgenerator (MCG) module. For more information on the MCG, see Chapter 8, Multi-Purpose ClockGenerator (S08MCGV1).The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramicresonator. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTALinput pin.

Refer to Figure 2-4 for the following discussion. RS (when used) and RF should be low-inductanceresistors such as carbon composition resistors. Wire-wound resistors and some metal film resistors havetoo much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specificallydesigned for high-frequency applications.

RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup; its valueis not generally critical. Typical systems use 1 M to 10 M. Higher values are sensitive to humidity, andlower values reduce gain and (in extreme cases) could prevent startup.C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specificcrystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pincapacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitancewhich is the series combination of C1 and C2 (which are usually the same size). As a first-orderapproximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin(EXTAL and XTAL).

2.2.3 RESETRESET is a dedicated pin with a pull-up device built in. It has input hysteresis, a high current output driver,and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically makeexternal reset circuitry unnecessary. This pin is normally connected to the standard 6-pin backgrounddebug connector so a development system can directly reset the MCU system. If desired, a manual externalreset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).




Whenever any reset is initiated (whether from an external signal or from an internal system), the RESETpin is driven low for about 34 bus cycles. The reset circuitry decodes the cause of reset and records it bysetting a corresponding bit in the system reset status register (SRS).

2.2.4 Background / Mode Select (BKGD/MS)While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises, the pinfunctions as the background pin and can be used for background debug communication. While functioningas a background or mode select pin, the pin includes an internal pull-up device, input hysteresis, a standardoutput driver, and no output slew rate control.

If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD lowduring the rising edge of reset which forces the MCU to active background mode.

The BKGD/MS pin is used primarily for background debug controller (BDC) communications using acustom protocol that uses 16 clock cycles of the target MCUs BDC clock per bit time. The target MCUsBDC clock could be as fast as the bus clock rate, so there should never be any significant capacitanceconnected to the BKGD/MS pin that could interfere with background serial communications.

Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocolprovides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances fromcables and the absolute value of the internal pull-up device play almost no role in determining rise and falltimes on the BKGD/MS pin.

2.2.5 ADC Reference Pins (VREFH, VREFL)The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs, respectively,for the ADC module.

2.2.6 General-Purpose I/O and Peripheral PortsThe MC9S08DZ60 Series series of MCUs support up to 53 general-purpose I/O pins and 1 input-only pin,which are shared with on-chip peripheral functions (timers, serial I/O, ADC, MSCAN, etc.).When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,software can select one of two drive strengths and enable or disable slew rate control. When a port pin isconfigured as a general-purpose input or a peripheral uses the port pin as an input, software can enable apull-up device. Immediately after reset, all of these pins are configured as high-impedance general-purposeinputs with internal pull-up devices disabled.

When an on-chip peripheral system is controlling a pin, data direction control bits still determine what isread from port data registers even though the peripheral module controls the pin direction by controllingthe enable for the pins output buffer. For information about controlling these pins as general-purpose I/Opins, see Chapter 6, Parallel Input/Output Control.




NOTETo avoid extra current drain from floating input pins, the reset initializationroutine in the application program should either enable on-chip pull-updevices or change the direction of unused or non-bonded pins to outputs sothey do not float.




3

PinNumber Highest

64 48 32 PortPin/Interrupt Alt 1 Alt 2

1 1 PTB6 PIB6 ADP142 PTC5 ADP213 2 1 PTA7 PIA7 ADP7 IRQ4 PTC6 ADP225 3 PTB7 PIB7 ADP156 PTC7 ADP237 4 2 VDD8 5 3 VSS9 6 4 PTG0 EXTAL

10 7 5 PTG1 XTAL11 8 6 RESET12 9 PTF4 ACMP2+13 10 PTF5 ACMP2-14 PTF6 ACMP2O15 11 7 PTE0 TxD116 12 8 PTE12 RxD12

17 13 9 PTE2 SS18 14 10 PTE3 SPSCK19 15 11 PTE4 SCL3 MOSI20 16 12 PTE5 SDA3 MISO21 PTG222 PTG323 17 PTF0 TxD24

24 18 PTF1 RxD24

25 19 PTF2 TPM1CLK SCL3

26 20 PTF3 TPM2CLK SDA3

27 PTG428 PTG529 21 13 PTE6 TxD24 TXCAN30 22 14 PTE7 RxD24 RxCAN31 23 15 PTD0 PID0 TPM2CH032 24 16 PTD1 PID1 TPM2CH1

33 25 17 PTD2 PID2 TPM1CH034 26 18 PTD3 PID3 TPM1CH135 27 19 PTD4 PID4 TPM1CH236 28 20 PTD5 PID5 TPM1CH337 PTF738 29 VSS39 30 VDD40 31 PTD6 PID6 TPM1CH441 32 PTD7 PID7 TPM1CH542 33 21 BKGD MS43 PTC0 ADP1644 34 22 PTB0 PIB0 ADP845 PTC1 ADP1746 35 23 PTA0 PIA0 ADP0 MCLK47 PTC2 ADP1848 36 24 PTB1 PIB1 ADP949 37 25 PTA1 PIA1 ADP11 ACMP1+1

50 38 PTB2 PIB2 ADP1051 39 26 PTA2 PIA2 ADP21 ACMP1-1

52 PTC3 ADP1953 40 PTB3 PIB3 ADP1154 41 27 PTA3 PIA3 ADP3 ACMP1O55

42 28VSSA

56 VREFL57

43 29VREFH

58 VDDA59 44 30 PTA4 PIA4 ADP460 45 PTB4 PIB4 ADP1261 PTC4 ADP2062 46 31 PTA5 PIA5 ADP563 47 PTB5 PIB5 ADP1364 48 32 PTA6 PIA6 ADP6

PinNumber Highest

64 48 32 PortPin/Interrupt Alt 1 Alt 2

Table 2-1. Pin Availability by Package Pin-Count

1. If both of these analog modules are enabled, they both will have access to the pin.2. Pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on this pin when internal

pull-up is enabled may be as low as VDD 0.7 V. The internal gates connected to this pin are pulled to VDD.3. The IIC module pins can be repositioned using IICPS bit in the SOPT1 register. The default reset locations are on PTF2 and PTF3.4. The SCI2 module pins can be repositioned using SCI2PS bit in the SOPT1 register. The default reset locations are on PTF0 and

PTF1.



Chapter 3Modes of Operation3.1 IntroductionThe operating modes of the MC9S08DZ60 Series are described in this chapter. Entry into each mode, exitfrom each mode, and functionality while in each of the modes are described.

3.2 Features Active background mode for code development Wait mode CPU shuts down to conserve power; system clocks are running and full regulation

is maintained Stop modes System clocks are stopped and voltage regulator is in standby

Stop3 All internal circuits are powered for fast recovery Stop2 Partial power down of internal circuits; RAM content is retained

3.3 Run ModeThis is the normal operating mode for the MC9S08DZ60 Series. This mode is selected when theBKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internalmemory with execution beginning at the address fetched from memory at 0xFFFE0xFFFF after reset.

3.4 Active Background ModeThe active background mode functions are managed through the background debug controller (BDC) inthe HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means foranalyzing MCU operation during software development.

Active background mode is entered in any of five ways: When the BKGD/MS pin is low at the rising edge of reset When a BACKGROUND command is received through the BKGD/MS pin When a BGND instruction is executed When encountering a BDC breakpoint When encountering a DBG breakpoint

After entering active background mode, the CPU is held in a suspended state waiting for serial backgroundcommands rather than executing instructions from the user application program.

Chapter 3 Modes of Operation



Background commands are of two types: Non-intrusive commands, defined as commands that can be issued while the user program is

running. Non-intrusive commands can be issued through the BKGD/MS pin while the MCU is inrun mode; non-intrusive commands can also be executed when the MCU is in the activebackground mode. Non-intrusive commands include: Memory access commands Memory-access-with-status commands BDC register access commands The BACKGROUND command

Active background commands, which can only be executed while the MCU is in active backgroundmode. Active background commands include commands to: Read or write CPU registers Trace one user program instruction at a time Leave active background mode to return to the user application program (GO)

The active background mode is used to program a bootloader or user application program into the Flashprogram memory before the MCU is operated in run mode for the first time. When the MC9S08DZ60Series is shipped from the Freescale Semiconductor factory, the Flash program memory is erased bydefault unless specifically noted so there is no program that could be executed in run mode until the Flashmemory is initially programmed. The active background mode can also be used to erase and reprogramthe Flash memory after it has been previously programmed.

For additional information about the active background mode, refer to the Development Support chapter.

3.5 Wait ModeWait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPUenters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters thewait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode andresumes processing, beginning with the stacking operations leading to the interrupt service routine.

While the MCU is in wait mode, there are some restrictions on which background debug commands canbe used. Only the BACKGROUND command and memory-access-with-status commands are availablewhen the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUNDcommand can be used to wake the MCU from wait mode and enter active background mode.




3.6 Stop ModesOne of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in SOPT1register is set. In both stop modes, all internal clocks are halted. The MCG module can be configured toleave the reference clocks running. See Chapter 8, Multi-Purpose Clock Generator (S08MCGV1), formore information.

Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under variousconditions. The selected mode is entered following the execution of a STOP instruction.

3.6.1 Stop3 ModeStop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Thestates of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.

Exit from stop3 is done by asserting RESET or an asynchronous interrupt pin. The asynchronous interruptpins are IRQ, PIA0PIA7, PIB0PIB7, and PID0PID7. Exit from stop3 can also be done by thelow-voltage detect (LVD) reset, low-voltage warning (LVW) interrupt, ADC conversion completeinterrupt, real-time clock (RTC) interrupt, MSCAN wake-up interrupt, or SCI receiver interrupt.If stop3 is exited by means of the RESET pin, the MCU will be reset and operation will resume afterfetching the reset vector. Exit by means of an interrupt will result in the MCU fetching the appropriateinterrupt vector.

3.6.1.1 LVD Enabled in Stop3 ModeThe LVD system is capable of generating either an interrupt or a reset when the supply voltage drops belowthe LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the timethe CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.

For the ADC to operate the LVD must be left enabled when entering stop3.

Table 3-1. Stop Mode Selection

STOPE ENBDM 1

1 ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see Section 17.4.1.1, BDC Status andControl Register (BDCSCR).

LVDE LVDSE PPDC Stop Mode

0 x x x Stop modes disabled; illegal opcode reset if STOP instruction executed

1 1 x x Stop3 with BDM enabled 2

2 When in Stop3 mode with BDM enabled, The SIDD will be near RIDD levels because internal clocks are enabled.

1 0 Both bits must be 1 x Stop3 with voltage regulator active

1 0 Either bit a 0 0 Stop3

1 0 Either bit a 0 1 Stop2




3.6.1.2 Active BDM Enabled in Stop3 ModeEntry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. Thisregister is described in Chapter 17, Development Support. If ENBDM is set when the CPU executes aSTOP instruction, the system clocks to the background debug logic remain active when the MCU entersstop mode. Because of this, background debug communication remains possible. In addition, the voltageregulator does not enter its low-power standby state but maintains full internal regulation.

Most background comm

mc9s08dz60

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