mc33078, mc33079, ncv33078, ncv33079 - low noise...

© Semiconductor Components Industries, LLC, 2011

November, 2011 − Rev. 91 Publication Order Number:

MC33078/D

MC33078, MC33079,NCV33078, NCV33079

Low Noise Dual/QuadOperational Amplifiers

The MC33078/9 series is a family of high quality monolithicamplifiers employing Bipolar technology with innovative highperformance concepts for quality audio and data signal processingapplications. This family incorporates the use of high frequency PNPinput transistors to produce amplifiers exhibiting low input voltagenoise with high gain bandwidth product and slew rate. The all NPNoutput stage exhibits no deadband crossover distortion, large outputvoltage swing, excellent phase and gain margins, low open loop highfrequency output impedance and symmetrical source and sink ACfrequency performance.

The MC33078/9 family offers both dual and quad amplifierversions and is available in the plastic DIP and SOIC packages (P andD suffixes).

Features• Dual Supply Operation: �5.0 V to �18 V

• Low Voltage Noise: 4.5 nV/ Hz�

• Low Input Offset Voltage: 0.15 mV

• Low T.C. of Input Offset Voltage: 2.0 �V/°C

• Low Total Harmonic Distortion: 0.002%

• High Gain Bandwidth Product: 16 MHz

• High Slew Rate: 7.0 V/�s

• High Open Loop AC Gain: 800 @ 20 kHz

• Excellent Frequency Stability

• Large Output Voltage Swing: +14.1 V/ −14.6 V

• ESD Diodes Provided on the Inputs

• NCV Prefix for Automotive and Other Applications RequiringUnique Site and Control Change Requirements

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHSCompliant

Figure 1. Representative Schematic Diagram(Each Amplifier)

VCCD1

Q4Q9

Q3 Q5

PosD3

C2R7

Q11Neg

R2

Q8 D4 C3 R9

Q10Q2 D2

Q6

R4Q7

R5

R6

Q12

R3C1R1Q1Z1

J1 AmplifierBiasing

VEE

Q3

Vout

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MARKINGDIAGRAMS

SOIC−14D SUFFIX

CASE 751A

14

1

MC33079DGAWLYWW

1

14

14

1

PDIP−14P SUFFIXCASE 646

MC33079PAWLYYWWG

1

14

PDIP−8P SUFFIXCASE 626

1

8

SOIC−8D SUFFIXCASE 751

1

8

DUAL

QUAD

1

8

MC33078P AWL

YYWWG

33078ALYW

�1

8

See detailed ordering and shipping information in the packagedimensions section on page 10 of this data sheet.

ORDERING INFORMATION

A = Assembly LocationWL, L = Wafer LotYY, Y = YearWW, W = Work WeekG or � = Pb−Free Package

MC33078, MC33079, NCV33078, NCV33079

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PIN CONNECTIONS

CASE 626/751

DUAL

(Dual, Top View)

4VEE

1

2

3

5

6

7

8 VCC

Output 2

Inputs 2

Inputs 1

-+

1

-+

2

Output 1

CASE 646/751A

QUAD

��

��

��

��

(Quad, Top View)

1

2

3

4

5

6

7

14

8

9

10

11

12

13

Output 1

VCC

Output 4

Inputs 4

Output 2

VEE

Inputs 3

Output 3

1 4

2 3

Inputs 1

Inputs 2

MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage (VCC to VEE) VS +36 V

Input Differential Voltage Range VIDR Note 1 V

Input Voltage Range VIR Note 1 V

Output Short Circuit Duration (Note 2) tSC Indefinite sec

Maximum Junction Temperature TJ +150 °C

Storage Temperature Tstg −�60 to +150 °C

ESD Protection at any PinMC33078/NCV33078 − Human Body Model

− Machine ModelMC33079/NCV33079 − Human Body Model

− Machine Model

Vesd600200550150

V

Maximum Power Dissipation PD Note 2 mW

Operating Temperature Range TA −40 to +85 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.1. Either or both input voltages must not exceed the magnitude of VCC or VEE.2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).

MC33078, MC33079, NCV33078, NCV33079

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DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)

Characteristics Symbol Min Typ Max Unit

Input Offset Voltage (RS = 10 �, VCM = 0 V, VO = 0 V)(MC33078)TA = +25°C

TA = −40° to +85°C(MC33079)TA = +25°C

TA = −40° to +85°C

|VIO|−−−−

0.15−

0.15−

2.03.02.53.5

mV

Average Temperature Coefficient of Input Offset VoltageRS = 10 �, VCM = 0 V, VO = 0 V, TA = Tlow to Thigh

�VIO/�T − 2.0 − �V/°C

Input Bias Current (VCM = 0 V, VO = 0 V)TA = +25°CTA = −40° to +85°C

IIB−−

300−

750800

nA

Input Offset Current (VCM = 0 V, VO = 0 V)TA = +25°CTA = −40° to +85°C

IIO−−

25−

150175

nA

Common Mode Input Voltage Range (�VIO = 5.0 mV, VO = 0 V) VICR ±13 ±14 − V

Large Signal Voltage Gain (VO = �10 V, RL = 2.0 k�)TA = +25°CTA = −40° to +85°C

AVOL9085

110−

−−

dB

Output Voltage Swing (VID = �1.0V)RL = 600 �RL = 600 �RL = 2.0 k�RL = 2.0 k�RL = 10 k�RL = 10 k�

VO�+VO�−VO�+VO�−VO�+VO�−

−−

+13.2−

+13.5−

+10.7−11.9+13.8−13.7+14.1−14.6

−−−

−13.2−−14

V

Common Mode Rejection (Vin = ±13V) CMR 80 100 − dB

Power Supply Rejection (Note 3)VCC/VEE = +15 V/ −15 V to +5.0 V/ −5.0 V

PSR 80 105 − dB

Output Short Circuit Current (VID = 1.0 V, Output to Ground)SourceSink

ISC+15−20

+29−37

−−

mA

Power Supply Current (VO = 0 V, All Amplifiers)(MC33078) TA = +25°C(MC33078) TA = −40° to +85°C(MC33079) TA = +25°C(MC33079) TA = −40° to +85°C

ID−−−−

4.1−

8.4−

5.05.51011

mA

3. Measured with VCC and VEE differentially varied simultaneously.

MC33078, MC33079, NCV33078, NCV33079

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AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)

Characteristics Symbol Min Typ Max Unit

Slew Rate (Vin = −10 V to +10 V, RL = 2.0 k�, CL = 100 pF AV = +1.0) SR 5.0 7.0 − V/�s

Gain Bandwidth Product (f = 100 kHz) GBW 10 16 − MHz

Unity Gain Bandwidth (Open Loop) BW − 9.0 − MHz

Gain Margin (RL = 2.0 k�)CL = 0 pFCL = 100 pF

Am−−

−11−�6.0

−−

dB

Phase Margin (RL = 2.0 k�)CL = 0 pFCL = 100 pF

�m−−

5540

−−

Deg

Channel Separation (f = 20 Hz to 20 kHz) CS − −120 − dB

Power Bandwidth (VO = 27 Vpp, RL = 2.0 k�, THD � 1.0%) BWp − 120 − kHz

Total Harmonic Distortion(RL = 2.0 k�, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0)

THD − 0.002 − %

Open Loop Output Impedance (VO = 0 V, f = 9.0 MHz) |ZO| − 37 − �

Differential Input Resistance (VCM = 0 V) Rin − 175 − k�

Differential Input Capacitance (VCM = 0 V) Cin − 12 − pF

Equivalent Input Noise Voltage (RS = 100 �, f = 1.0 kHz) en − 4.5 − nV/ Hz√

Equivalent Input Noise Current (f = 1.0 kHz) in − 0.5 − pA/Hz √

VCM = 0 VTA = 25°C

Figure 2. Maximum Power Dissipationversus Temperature

Figure 3. Input Bias Current versusSupply Voltage

Figure 4. Input Bias Current versus Temperature Figure 5. Input Offset Voltage versus Temperature

P�, M

AXIM

UM

PO

WER

DIS

SIPA

TIO

N (m

W)

D

-20 0 20 40 60 80 100 120 140 160

TA, AMBIENT TEMPERATURE (°C)

-55 -40

MC33078P & MC33079P

MC33079D

MC33078D

0 10 15 20

VCC, | VEE |, SUPPLY VOLTAGE (V)

I�, I

NPU

T BI

AS C

UR

REN

T (n

A)IB


0 25 50 75 100 125-55 -25

VCC = +15 VVEE = -15 VVCM = 0 V

V�, I

NPU

T O

FFSE

T VO

LTAG

E (m

V)IO


-55 -25 0 25 50 75 100 125

Unit 1

Unit 2

Unit 3

VCC = +15 VVEE = -15 VRS = 10 �VCM = 0 VAV = +1

I�, I

NPU

T BI

AS C

UR

REN

T (n

A)IB

2400

2000

1600

1200

800

400

0

800

600

400

200

0

1000

800

600

400

200

0

2.0

1.0

0

-1.0

-2.0

5.0

MC33078, MC33079, NCV33078, NCV33079

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Sink

Source

VCC = +15 VVEE = -15 VRL < 100 �VID = 1.0 V

-55°C

25°CVCC = +15 VVEE = -15 V

125°C

-55°C

125°C25°C

Figure 6. Input Bias Current versusCommon Mode Voltage

Figure 7. Input Common Mode VoltageRange versus Temperature

Figure 8. Output Saturation Voltage versusLoad Resistance to Ground

Figure 9. Output Short Circuit Currentversus Temperature

Figure 10. Supply Current versusTemperature

Figure 11. Common Mode Rejectionversus Frequency

I�, I

NPU

T BI

AS C

UR

REN

T (n

A)IB

-15 -10 -�5.0 0 5.0 10 15

VCM, COMMON MODE VOLTAGE (V)

VCC = +15 VVEE = -15 VTA = 25°C

VIC

R

VoltageRange

-VCM

-�55 -�25 0 25 50 75 100 125


+VCMVCC = +3.0 V to +15 VVEE = -3.0 V to -15 V�VIO = 5.0 mVVO = 0 V

| I�

�|, O

UTP

UT

SHO

RT C

IRC

UIT

CU

RR

ENT

(mA)

SC


-�55 -�25 0 25 50 75 100 125

I��,

SU

PPLY

CU

RR

ENT

(mA)

CC


-�55 -�25 0 25 50 75 100 125

±10 V

±15 V

±15 V

±10 V

±5.0 V

±5.0 V

VCM = 0 VRL = ∞VO = 0 V

MC33078

MC33079

Supply Voltages

CM

R, C

OM

MO

N M

OD

E R

EJEC

TIO

N (d

B)

100 1.0 k 10 k 100 k 1.0 M 10 M

f, FREQUENCY (Hz)

VCC = +15 VVEE = -15 VVCM = 0 V�VCM = ±1.5 VTA = 25°C

, OU

TPU

T SA

TUR

ATIO

N V

OLT

AGE

(V)

sat

RL, LOAD RESISTANCE TO GROUND (k�)

0 1.0 2.0 3.0 4.0

, IN

PUT

CO

MM

ON

MO

DE

VOLT

AGE

RAN

GE

(V)

V600

500

400

300

200

100

0

VCC -0

VCC -0.5

VCC -1.0

VCC -1.5

VEE +1.5

VEE +1.0

VEE +0.5

VEE +0

50

30

20

10

40

10

8.0

6.0

4.0

2.0

0

160

140

120

100

80

60

40

20

VCC -1.0

VCC -3.0

VCC -5.0

VEE +5.0

VEE +3.0

VEE +1.0

CMR = 20Log

-

+� VCM ADM

� VCM

� VO

× ADM

� VO9.0

7.0

5.0

3.0

1.0

±4.0 V

MC33078, MC33079, NCV33078, NCV33079

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V O,O

UTP

UT

VOLT

AGE

(V)

pp

RL = 2.0 k�f ≤ 10 Hz�VO = 2/3 (VCC -VEE)TA = 25°C

RL = 10 k�CL = 0 pFf = 100 kHzTA = 25°C

Figure 12. Power Supply Rejectionversus Frequency

Figure 13. Gain Bandwidth Productversus Supply Voltage

Figure 14. Gain Bandwidth Productversus Temperature

Figure 15. Maximum Output Voltageversus Supply Voltage

Figure 16. Output Voltage versus Frequency Figure 17. Open Loop Voltage Gainversus Supply Voltage

f, FREQUENCY (Hz)

PSR

, PO

WER

SU

PPLY

REJ

ECTI

ON

(dB)

100 1.0 k 10 k 100 k 1.0 M 10 M

+PSR

-PSR

VCC = +15 VVEE = -15 VTA = 25°C

VCC |VEE| , SUPPLY VOLTAGE (V)

GW

B, G

AIN

BAN

DW

IDTH

PR

OD

UC

T (M

Hz)

0 10 15 20


GW

B, G

AIN

BAN

DW

IDTH

PR

OD

UC

T (M

Hz)

-55 -25 0 50 75 10025 125

VCC = +15 VVEE = -15 Vf = 100 kHzRL = 10 k�CL = 0 pF


V ,

OU

TPU

T VO

LTAG

E (V

p)O

0 10 15 20

VO -

VO +TA = 25°C

RL = 10 k�

RL = 10 k�

RL = 2.0 k�

RL = 2.0 k�

f, FREQUENCY (Hz)

10 100 1.0 k 10 k 100 k 1.0 M 10 M

VCC = +15 VVCC = -15 VRL = 2.0 k�AV = +1.0THD ≤ 1.0%TA = 25°C


VOL

A��

, OPE

N L

OO

P VO

LTAG

E G

AIN

(dB)

0 10 15 20

140

120

100

80

60

40

20

0

30

20

10

0

20

15

10

5.0

0

20

15

10

5.0

0

-5.0

-10

-15

-20

35

30

25

20

15

10

5.0

0

110

100

90

80

+PSR = 20Log�VO/ADM

�VCC

ADM-

+�VO

VEE

-PSR = 20Log�VO/ADM

�VCC

�VCC

5.0

5.0

5.0

MC33078, MC33079, NCV33078, NCV33079

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VOL

A��

, OPE

N L

OO

P VO

LTAG

E G

AIN

(dB)

Figure 18. Open Loop Voltage Gainversus Temperature

Figure 19. Output Impedanceversus Frequency

Figure 20. Channel Separationversus Frequency

Figure 21. Total Harmonic Distortionversus Frequency

Figure 22. Total Harmonic Distortionversus Output Voltage

Figure 23. Slew Rate versus Supply Voltage


-55 -25 0 25 50 75 100 125

VCC = +15 VVEE = -15 VRL = 2.0 k�f ≤ 10 Hz�VO = -10 V to +10 V

f, FREQUENCY (Hz)

| Z�

|, O

UTP

UT

IMPE

DAN

CE

(��)

Ω

1.0 k 10 k 100 k 1.0 M 10 M

O

VCC = +15 VVEE = -15 VVO = 0 VTA = 25°C

AV = 1000 AV = 100 AV = 10AV = 1.0

f, FREQUENCY (Hz)

CS,

CH

ANN

EL S

EPAR

ATIO

N (d

B)

CS = 20 Log�VOA

�VOM

10 100 1.0 k 100 k10 k

Drive ChannelVCC = +15 VVEE = -15 VRL = 2.0 K��VOD = 20 VppTA = 25°C

MC33078

MC33079

f, FREQUENCY (Hz)

THD

, TO

TAL

HAR

MO

NIC

DIS

TORT

ION

(%)

10 100 1.0 k 10 k 100 k

VCC = +15 VVEE = -15 VVO = 1.0 VrmsTA = 25°C

VO, OUTPUT VOLTAGE (Vrms)

THD

, TO

TAL

HAR

MO

NIC

DIS

TORT

ION

(%)

0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0

VCC = +15 VVEE = -15 Vf = 2.0 kHzTA = 25°C

AV = 1000

AV = 100

AV = 10

AV = 1.0

VCC |VEE| , SUPPLY VOLTAGE (V)4 12 16 20

SR, S

LEW

RAT

E (V

/� s

)μ

Vin = 2/3 (VCC -VEE)TA = 25°C

Rising

110

105

100

95

90

50

40

30

20

10

0

160

150

140

130

120

110

100

1.0

0.1

0.01

0.001

1.0

0.5

0.1

0.05

0.01

0.005

0.001

10

8.0

6.0

4.0

2.0

0

10 k�

VOM

Measurement Channel

-

+

100 �

100 �

VO

2.0 k�+

-

�VinVO

2.0k�

-

+

RA

Vin2.0 k�

VO+

-10 k�

6 8 10 14 18

Falling9.0

7.0

5.0

3.0

1.0

MC33078, MC33079, NCV33078, NCV33079

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25°C

-�55°C

125°C

VCC = +15 VVEE = -15 V�Vin = 100 mV

�VinVO

CL

-

+

VCC = +15 VVEE = -15 VVO = 0 V

Phase

Gain

125°C

-55°C25°C

25°C-55°C

125°C

VinVO

CL2.0 k�

-

+

GainPhase

VCC = +15 VVEE = -15 VRL = 2.0 k�TA = 25°C

Figure 24. Slew Rate versus Temperature Figure 25. Voltage Gain and Phaseversus Frequency

Figure 26. Open Loop Gain Margin andPhase Margin versus Load Capacitance

Figure 27. Overshoot versus OutputLoad Capacitance

Figure 28. Input Referred Noise Voltage andCurrent versus Frequency

Figure 29. Total Input Referred Noise Voltageversus Source Resistance

SR, S

LEW

RAT

E (V

/�s)

μVCC = +15 VVEE = -15 V�Vin = 20 V


Falling

Rising

-55 -25 0 25 50 75 100 125

f, FREQUENCY (Hz)

VOL

A��

, OPE

N L

OO

P VO

LTAG

E G

AIN

(dB)

1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M

0

45

90

135

180

, EXC

ESS

PHAS

E (D

EGR

EES)

φ

A�, O

PEN

LO

OP

GAI

N M

ARG

IN (d

B)m

1 10 100 1000

0

10

20

30

40

50

60 φ, P

HAS

E M

ARG

IN (D

EGR

EES)

m

70

CL, OUTPUT LOAD CAPACITANCE (pF) CL, OUTPUT LOAD CAPACITANCE (pF)

10 100 1.0 k 10 k

os, O

VER

SHO

OT

(%)

10 100 1.0 k 10 k 100 k

10

0.1

f, FREQUENCY (Hz)e�, I

NPU

T R

EFER

RED

NO

ISE

VOLT

AGE

(��

��

)n

nV/

Hz

√

VCC = +15 VVEE = -15 VTA = 25°C

Voltage

Current

pA/

Hz

√

nV/

Hz

√

RS, SOURCE RESISTANCE (�)

i

, REF

ERR

ED N

OIS

E VO

LTAG

E (

n

VCC = +15 VVEE = -15 Vf = 1.0 kHzTA = 25°CVn(total) =

10 100 1.0 k 10 k 100 k 1.0 M, IN

PUT

REF

ERR

ED N

OIS

E C

UR

REN

T (

)n

V)

10

8.0

6.0

4.0

2.0

120

100

80

60

40

20

0

14

12

10

8.0

6.0

4.0

2.0

0

100

80

60

40

20

0

10080

50

3020

108.0

5.0

3.02.0

1.0

1000

100

10

1.0

�VinVO

2.0k�

-

+

(inRs)2� �� en2� �� 4KTRS�

MC33078, MC33079, NCV33078, NCV33079

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+

-Phase

Gain

R1

R2

VO

VCC = +15 VVEE = -15 VRT = R1 +R2AV = +100VO = 0 VTA = 25°C

Figure 30. Phase Margin and Gain Margin versusDifferential Source Resistance

Figure 31. Inverting Amplifier Slew Rate Figure 32. Non−inverting Amplifier Slew Rate

Figure 33. Non−inverting Amplifier Overshoot Figure 34. Low Frequency Noise Voltageversus Time

, PH

ASE

MAR

GIN

(DEG

REE

S)

A ,

GAI

N M

ARG

IN (d

B)

RT, DIFFERENTIAL SOURCE RESISTANCE (�)

φm

10 100 1.0 k 10 k 100 k

VCC = +15 VVEE = -15 VAV = -1.0RL = 2.0 k�CL = 100 pFTA = 25°C

V�, O

UTP

UT

VOLT

AGE

(5.0

V/D

IV)

O

t, TIME (2.0 �s/DIV)

VCC = +15 VVEE = -15 VAV = +1.0RL = 2.0 k�CL = 100 pFTA = 25°C

V�, O

UTP

UT

VOLT

AGE

(5.0

V/D

IV)

O

t, TIME (2.0 �s/DIV)

VCC = +15 VVEE = -15 VRL = 2.0 k�CL = 100 pFAV = +1.0TA = 25°C

V�, O

UTP

UT

VOLT

AGE

(5.0

V/D

IV)

O

t, TIME (200 �s/DIV)

e�, I

NPU

T N

OIS

E VO

LTAG

E (1

00 n

V/D

IV)

n

t, TIME (1.0 sec/DIV)

m

14

12

10

8.0

6.0

4.0

2.0

0

70

60

50

40

30

20

10

0

VCC = +15 VVEE = -15 VBW = 0.1 Hz to 10 HzTA = 25°C

MC33078, MC33079, NCV33078, NCV33079

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Figure 35. Voltage Noise Test Circuit(0.1 Hz to 10 Hzp−p)

+

-

0.1 �F

10 � 100 k�

2.0 k�

4.7 �F

Voltage Gain = 50,000

Scope× 1

Rin = 1.0 M�

1/2MC33078-

+D.U.T.

100 k�

0.1 �F

2.2 �F

22 �F

24.3 k�

4.3 k�

110 k�

Note: All capacitors are non−polarized.

ORDERING INFORMATION

Device Package Shipping†

MC33078DGSOIC−8

(Pb−Free)

98 Units / Rail

MC33078DR2G2500 / Tape & Reel

NCV33078DR2G*

MC33078P PDIP−8

50 Units / RailMC33078PG PDIP−8(Pb−Free)

MC33079DG SOIC−14(Pb−Free) 55 Units / Rail

MC33079DR2G SOIC−14(Pb−Free) 2500 / Tape & Reel

NCV33079DR2G*

MC33079P PDIP−14

25 Units / RailMC33079PG PDIP−14(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

*NCV devices are qualified for automotive use.

MC33078, MC33079, NCV33078, NCV33079

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PACKAGE DIMENSIONS

PDIP−8N SUFFIX

CASE 626−05ISSUE M

1 4

58

FNOTE 5

D

eb

L

A1

A

E3

E

A

TOP VIEW

C SEATINGPLANE

0.010 C ASIDE VIEW

END VIEW

END VIEW

NOTE 3

DIM MIN NOM MAXINCHES

A −−−− −−−− 0.210A1 0.015 −−−− −−−−b 0.014 0.018 0.022C 0.008 0.010 0.014D 0.355 0.365 0.400D1 0.005 −−−− −−−−

e 0.100 BSC

E 0.300 0.310 0.325

L 0.115 0.130 0.150

−−−− −−−− 5.330.38 −−−− −−−−0.35 0.46 0.560.20 0.25 0.369.02 9.27 10.020.13 −−−− −−−−

2.54 BSC

7.62 7.87 8.26

2.92 3.30 3.81

MIN NOM MAXMILLIMETERS

NOTES:1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.2. CONTROLLING DIMENSION: INCHES.3. DIMENSION E IS MEASURED WITH THE LEADS RE-

STRAINED PARALLEL AT WIDTH E2.4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

E1 0.240 0.250 0.280 6.10 6.35 7.11E2E3 −−−− −−−− 0.430 −−−− −−−− 10.92

0.300 BSC 7.62 BSC

E1

D1

M

8X

e/2

E2c

MC33078, MC33079, NCV33078, NCV33079

http://onsemi.com12

PACKAGE DIMENSIONS

SOIC−8 NBCASE 751−07

ISSUE AK

SEATINGPLANE

14

58

N

J

X 45�

K

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

A

B S

DH

C

0.10 (0.004)

DIMA

MIN MAX MIN MAXINCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244

−X−

−Y−

G

MYM0.25 (0.010)

−Z−

YM0.25 (0.010) Z S X S

M� � � �

1.520.060

7.00.275

0.60.024

1.2700.050

4.00.155

� mminches

�SCALE 6:1

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MC33078, MC33079, NCV33078, NCV33079

http://onsemi.com13

PACKAGE DIMENSIONS

PDIP−14CASE 646−06

ISSUE P

1 7

14 8

B

A DIM MIN MAX MIN MAXMILLIMETERSINCHES

A 0.715 0.770 18.16 19.56B 0.240 0.260 6.10 6.60C 0.145 0.185 3.69 4.69D 0.015 0.021 0.38 0.53F 0.040 0.070 1.02 1.78G 0.100 BSC 2.54 BSCH 0.052 0.095 1.32 2.41J 0.008 0.015 0.20 0.38K 0.115 0.135 2.92 3.43LM −−− 10 −−− 10 N 0.015 0.039 0.38 1.01

� �

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

F

H G DK

C

SEATINGPLANE

N

−T−

14 PL

M0.13 (0.005)

L

MJ

0.290 0.310 7.37 7.87

MC33078, MC33079, NCV33078, NCV33079

http://onsemi.com14

PACKAGE DIMENSIONS

SOIC−14 NBCASE 751A−03

ISSUE K

NOTES:1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSIONSHALL BE 0.13 TOTAL IN EXCESS OF ATMAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDEMOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PERSIDE.

H

14 8

71

M0.25 B M

C

hX 45

SEATINGPLANE

A1

A

M

�

SAM0.25 B SC

b13X

BA

E

D

e

DETAIL A

L

A3

DETAIL A

DIM MIN MAX MIN MAXINCHESMILLIMETERS

D 8.55 8.75 0.337 0.344E 3.80 4.00 0.150 0.157

A 1.35 1.75 0.054 0.068

b 0.35 0.49 0.014 0.019

L 0.40 1.25 0.016 0.049

e 1.27 BSC 0.050 BSC

A3 0.19 0.25 0.008 0.010A1 0.10 0.25 0.004 0.010

M 0 7 0 7

H 5.80 6.20 0.228 0.244h 0.25 0.50 0.010 0.019

� � � �

6.50

14X0.58

14X

1.18

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATIONN. American Technical Support: 800−282−9855 Toll FreeUSA/Canada

Europe, Middle East and Africa Technical Support:Phone: 421 33 790 2910

Japan Customer Focus CenterPhone: 81−3−5817−1050

MC33078/D

LITERATURE FULFILLMENT:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303−675−2175 or 800−344−3860 Toll Free USA/CanadaFax: 303−675−2176 or 800−344−3867 Toll Free USA/CanadaEmail: [email protected]

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